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stm32lib/STM32F7xx_HAL_Driver/Inc/stm32f7xx_ll_adc.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32f7xx_ll_adc.h

  4.   * @author  MCD Application Team

  5.   * @version V1.2.2

  6.   * @date    14-April-2017

  7.   * @brief   Header file of ADC LL module.

  8.   ******************************************************************************

  9.   * @attention

  10.   *

  11.   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

  12.   *

  13.   * Redistribution and use in source and binary forms, with or without modification,

  14.   * are permitted provided that the following conditions are met:

  15.   *   1. Redistributions of source code must retain the above copyright notice,

  16.   *      this list of conditions and the following disclaimer.

  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,

  18.   *      this list of conditions and the following disclaimer in the documentation

  19.   *      and/or other materials provided with the distribution.

  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors

  21.   *      may be used to endorse or promote products derived from this software

  22.   *      without specific prior written permission.

  23.   *

  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  34.   *

  35.   ******************************************************************************

  36.   */

  37. 

  38. /* Define to prevent recursive inclusion -------------------------------------*/

  39. #ifndef __STM32F7xx_LL_ADC_H

  40. #define __STM32F7xx_LL_ADC_H

  41. 

  42. #ifdef __cplusplus

  43. extern "C" {

  44. #endif

  45. 

  46. /* Includes ------------------------------------------------------------------*/

  47. #include "stm32f7xx.h"

  48. 

  49. /** @addtogroup STM32F7xx_LL_Driver

  50.   * @{

  51.   */

  52. 

  53. #if defined (ADC1) || defined (ADC2) || defined (ADC3)

  54. 

  55. /** @defgroup ADC_LL ADC

  56.   * @{

  57.   */

  58. 

  59. /* Private types -------------------------------------------------------------*/

  60. /* Private variables ---------------------------------------------------------*/

  61. 

  62. /* Private constants ---------------------------------------------------------*/

  63. /** @defgroup ADC_LL_Private_Constants ADC Private Constants

  64.   * @{

  65.   */

  66. 

  67. /* Internal mask for ADC group regular sequencer:                             */

  68. /* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */

  69. /* - sequencer register offset                                                */

  70. /* - sequencer rank bits position into the selected register                  */

  71. 

  72. /* Internal register offset for ADC group regular sequencer configuration */

  73. /* (offset placed into a spare area of literal definition) */

  74. #define ADC_SQR1_REGOFFSET                 0x00000000U

  75. #define ADC_SQR2_REGOFFSET                 0x00000100U

  76. #define ADC_SQR3_REGOFFSET                 0x00000200U

  77. #define ADC_SQR4_REGOFFSET                 0x00000300U

  78. 

  79. #define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

  80. #define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  81. 

  82. /* Definition of ADC group regular sequencer bits information to be inserted  */

  83. /* into ADC group regular sequencer ranks literals definition.                */

  84. #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */

  85. #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */

  86. #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */

  87. #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */

  88. #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */

  89. #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */

  90. #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */

  91. #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */

  92. #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */

  93. #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */

  94. #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */

  95. #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */

  96. #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */

  97. #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */

  98. #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */

  99. #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */

  100. 

  101. /* Internal mask for ADC group injected sequencer:                            */

  102. /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */

  103. /* - data register offset                                                     */

  104. /* - offset register offset                                                   */

  105. /* - sequencer rank bits position into the selected register                  */

  106. 

  107. /* Internal register offset for ADC group injected data register */

  108. /* (offset placed into a spare area of literal definition) */

  109. #define ADC_JDR1_REGOFFSET                 0x00000000U

  110. #define ADC_JDR2_REGOFFSET                 0x00000100U

  111. #define ADC_JDR3_REGOFFSET                 0x00000200U

  112. #define ADC_JDR4_REGOFFSET                 0x00000300U

  113. 

  114. /* Internal register offset for ADC group injected offset configuration */

  115. /* (offset placed into a spare area of literal definition) */

  116. #define ADC_JOFR1_REGOFFSET                0x00000000U

  117. #define ADC_JOFR2_REGOFFSET                0x00001000U

  118. #define ADC_JOFR3_REGOFFSET                0x00002000U

  119. #define ADC_JOFR4_REGOFFSET                0x00003000U

  120. 

  121. #define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

  122. #define ADC_INJ_JOFRX_REGOFFSET_MASK       (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)

  123. #define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

  124. 

  125. /* Internal mask for ADC group regular trigger:                               */

  126. /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */

  127. /* - regular trigger source                                                   */

  128. /* - regular trigger edge                                                     */

  129. #define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  130. 

  131. /* Mask containing trigger source masks for each of possible                  */

  132. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  133. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  134. #define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4U * 0U)) | \

  135.                                              ((ADC_CR2_EXTSEL)                            >> (4U * 1U)) | \

  136.                                              ((ADC_CR2_EXTSEL)                            >> (4U * 2U)) | \

  137.                                              ((ADC_CR2_EXTSEL)                            >> (4U * 3U)))

  138. 

  139. /* Mask containing trigger edge masks for each of possible                    */

  140. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  141. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  142. #define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4U * 0U)) | \

  143.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 1U)) | \

  144.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 2U)) | \

  145.                                              ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)            >> (4U * 3U)))

  146. 

  147. /* Definition of ADC group regular trigger bits information.                  */

  148. #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (24U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */

  149. #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (28U) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */

  150. 

  151. 

  152. 

  153. /* Internal mask for ADC group injected trigger:                              */

  154. /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */

  155. /* - injected trigger source                                                  */

  156. /* - injected trigger edge                                                    */

  157. #define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

  158. 

  159. /* Mask containing trigger source masks for each of possible                  */

  160. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  161. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  162. #define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4U * 0U)) | \

  163.                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 1U)) | \

  164.                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 2U)) | \

  165.                                              ((ADC_CR2_JEXTSEL)                            >> (4U * 3U)))

  166. 

  167. /* Mask containing trigger edge masks for each of possible                    */

  168. /* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

  169. /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

  170. #define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4U * 0U)) | \

  171.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 1U)) | \

  172.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 2U)) | \

  173.                                              ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)             >> (4U * 3U)))

  174. 

  175. /* Definition of ADC group injected trigger bits information.                 */

  176. #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (16U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */

  177. #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (20U) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */

  178. 

  179. /* Internal mask for ADC channel:                                             */

  180. /* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */

  181. /* - channel identifier defined by number                                     */

  182. /* - channel differentiation between external channels (connected to          */

  183. /*   GPIO pins) and internal channels (connected to internal paths)           */

  184. /* - channel sampling time defined by SMPRx register offset                   */

  185. /*   and SMPx bits positions into SMPRx register                              */

  186. #define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CR1_AWDCH)

  187. #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */

  188. #define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  189. /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */

  190. #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */

  191. 

  192. /* Channel differentiation between external and internal channels */

  193. #define ADC_CHANNEL_ID_INTERNAL_CH         0x80000000U   /* Marker of internal channel */

  194. #define ADC_CHANNEL_ID_INTERNAL_CH_2       0x40000000U   /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */

  195. #define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U  /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */

  196. #define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)

  197. 

  198. /* Internal register offset for ADC channel sampling time configuration */

  199. /* (offset placed into a spare area of literal definition) */

  200. #define ADC_SMPR1_REGOFFSET                0x00000000U

  201. #define ADC_SMPR2_REGOFFSET                0x02000000U

  202. #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

  203. 

  204. #define ADC_CHANNEL_SMPx_BITOFFSET_MASK    0x01F00000U

  205. #define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20U)           /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */

  206. 

  207. /* Definition of channels ID number information to be inserted into           */

  208. /* channels literals definition.                                              */

  209. #define ADC_CHANNEL_0_NUMBER               0x00000000U

  210. #define ADC_CHANNEL_1_NUMBER               (                                                                        ADC_CR1_AWDCH_0)

  211. #define ADC_CHANNEL_2_NUMBER               (                                                      ADC_CR1_AWDCH_1                  )

  212. #define ADC_CHANNEL_3_NUMBER               (                                                      ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  213. #define ADC_CHANNEL_4_NUMBER               (                                    ADC_CR1_AWDCH_2                                    )

  214. #define ADC_CHANNEL_5_NUMBER               (                                    ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)

  215. #define ADC_CHANNEL_6_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )

  216. #define ADC_CHANNEL_7_NUMBER               (                                    ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  217. #define ADC_CHANNEL_8_NUMBER               (                  ADC_CR1_AWDCH_3                                                      )

  218. #define ADC_CHANNEL_9_NUMBER               (                  ADC_CR1_AWDCH_3                                     | ADC_CR1_AWDCH_0)

  219. #define ADC_CHANNEL_10_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1                  )

  220. #define ADC_CHANNEL_11_NUMBER              (                  ADC_CR1_AWDCH_3                   | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  221. #define ADC_CHANNEL_12_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                                    )

  222. #define ADC_CHANNEL_13_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2                   | ADC_CR1_AWDCH_0)

  223. #define ADC_CHANNEL_14_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1                  )

  224. #define ADC_CHANNEL_15_NUMBER              (                  ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)

  225. #define ADC_CHANNEL_16_NUMBER              (ADC_CR1_AWDCH_4                                                                        )

  226. #define ADC_CHANNEL_17_NUMBER              (ADC_CR1_AWDCH_4                                                       | ADC_CR1_AWDCH_0)

  227. #define ADC_CHANNEL_18_NUMBER              (ADC_CR1_AWDCH_4                                     | ADC_CR1_AWDCH_1                  )

  228. 

  229. /* Definition of channels sampling time information to be inserted into       */

  230. /* channels literals definition.                                              */

  231. #define ADC_CHANNEL_0_SMP                  (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */

  232. #define ADC_CHANNEL_1_SMP                  (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */

  233. #define ADC_CHANNEL_2_SMP                  (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */

  234. #define ADC_CHANNEL_3_SMP                  (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */

  235. #define ADC_CHANNEL_4_SMP                  (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */

  236. #define ADC_CHANNEL_5_SMP                  (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */

  237. #define ADC_CHANNEL_6_SMP                  (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */

  238. #define ADC_CHANNEL_7_SMP                  (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */

  239. #define ADC_CHANNEL_8_SMP                  (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */

  240. #define ADC_CHANNEL_9_SMP                  (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */

  241. #define ADC_CHANNEL_10_SMP                 (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */

  242. #define ADC_CHANNEL_11_SMP                 (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */

  243. #define ADC_CHANNEL_12_SMP                 (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */

  244. #define ADC_CHANNEL_13_SMP                 (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */

  245. #define ADC_CHANNEL_14_SMP                 (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */

  246. #define ADC_CHANNEL_15_SMP                 (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */

  247. #define ADC_CHANNEL_16_SMP                 (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */

  248. #define ADC_CHANNEL_17_SMP                 (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */

  249. #define ADC_CHANNEL_18_SMP                 (ADC_SMPR1_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */

  250. 

  251. /* Internal mask for ADC analog watchdog:                                     */

  252. /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */

  253. /* (concatenation of multiple bits used in different analog watchdogs,        */

  254. /* (feature of several watchdogs not available on all STM32 families)).       */

  255. /* - analog watchdog 1: monitored channel defined by number,                  */

  256. /*   selection of ADC group (ADC groups regular and-or injected).             */

  257. 

  258. /* Internal register offset for ADC analog watchdog channel configuration */

  259. #define ADC_AWD_CR1_REGOFFSET              0x00000000U

  260. 

  261. #define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET)

  262. 

  263. #define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)

  264. #define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK)

  265. 

  266. /* Internal register offset for ADC analog watchdog threshold configuration */

  267. #define ADC_AWD_TR1_HIGH_REGOFFSET         0x00000000U

  268. #define ADC_AWD_TR1_LOW_REGOFFSET          0x00000001U

  269. #define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)

  270. 

  271. /* ADC registers bits positions */

  272. #define ADC_CR1_RES_BITOFFSET_POS          (24U) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */

  273. #define ADC_TR_HT_BITOFFSET_POS            (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */

  274. /* ADC internal channels related definitions */

  275. /* Internal voltage reference VrefInt */

  276. #define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF07A4A))  /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  277. #define VREFINT_CAL_VREF                   ( 3300U)                    /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

  278. /* Temperature sensor */

  279. #define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF07A4C))  /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  280. #define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF07A4E))  /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

  281. #define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  282. #define TEMPSENSOR_CAL2_TEMP               (( int32_t)  110)           /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

  283. #define TEMPSENSOR_CAL_VREFANALOG          ( 3300U)                    /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

  284. /**

  285.   * @}

  286.   */

  287. 

  288. 

  289. /* Private macros ------------------------------------------------------------*/

  290. /** @defgroup ADC_LL_Private_Macros ADC Private Macros

  291.   * @{

  292.   */

  293. 

  294. /**

  295.   * @brief  Driver macro reserved for internal use: isolate bits with the

  296.   *         selected mask and shift them to the register LSB

  297.   *         (shift mask on register position bit 0).

  298.   * @param  __BITS__ Bits in register 32 bits

  299.   * @param  __MASK__ Mask in register 32 bits

  300.   * @retval Bits in register 32 bits

  301.   */

  302. #define __ADC_MASK_SHIFT(__BITS__, __MASK__)                                   \

  303.   (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))

  304. 

  305. /**

  306.   * @brief  Driver macro reserved for internal use: set a pointer to

  307.   *         a register from a register basis from which an offset

  308.   *         is applied.

  309.   * @param  __REG__ Register basis from which the offset is applied.

  310.   * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

  311.   * @retval Pointer to register address

  312.   */

  313. #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

  314.  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))

  315. 

  316. /**

  317.   * @}

  318.   */

  319. 

  320. 

  321. /* Exported types ------------------------------------------------------------*/

  322. #if defined(USE_FULL_LL_DRIVER)

  323. /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure

  324.   * @{

  325.   */

  326. 

  327. /**

  328.   * @brief  Structure definition of some features of ADC common parameters

  329.   *         and multimode

  330.   *         (all ADC instances belonging to the same ADC common instance).

  331.   * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()

  332.   *         is conditioned to ADC instances state (all ADC instances

  333.   *         sharing the same ADC common instance):

  334.   *         All ADC instances sharing the same ADC common instance must be

  335.   *         disabled.

  336.   */

  337. typedef struct

  338. {

  339.   uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.

  340.                                              This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE

  341. 

  342.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */

  343. 

  344.   uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

  345.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE

  346. 

  347.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */

  348. 

  349.   uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.

  350.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER

  351. 

  352.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */

  353. 

  354.   uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.

  355.                                              This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY

  356. 

  357.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */

  358. 

  359. } LL_ADC_CommonInitTypeDef;

  360. 

  361. /**

  362.   * @brief  Structure definition of some features of ADC instance.

  363.   * @note   These parameters have an impact on ADC scope: ADC instance.

  364.   *         Affects both group regular and group injected (availability

  365.   *         of ADC group injected depends on STM32 families).

  366.   *         Refer to corresponding unitary functions into

  367.   *         @ref ADC_LL_EF_Configuration_ADC_Instance .

  368.   * @note   The setting of these parameters by function @ref LL_ADC_Init()

  369.   *         is conditioned to ADC state:

  370.   *         ADC instance must be disabled.

  371.   *         This condition is applied to all ADC features, for efficiency

  372.   *         and compatibility over all STM32 families. However, the different

  373.   *         features can be set under different ADC state conditions

  374.   *         (setting possible with ADC enabled without conversion on going,

  375.   *         ADC enabled with conversion on going, ...)

  376.   *         Each feature can be updated afterwards with a unitary function

  377.   *         and potentially with ADC in a different state than disabled,

  378.   *         refer to description of each function for setting

  379.   *         conditioned to ADC state.

  380.   */

  381. typedef struct

  382. {

  383.   uint32_t Resolution;                  /*!< Set ADC resolution.

  384.                                              This parameter can be a value of @ref ADC_LL_EC_RESOLUTION

  385. 

  386.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */

  387. 

  388.   uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.

  389.                                              This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN

  390. 

  391.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */

  392. 

  393.   uint32_t SequencersScanMode;          /*!< Set ADC scan selection.

  394.                                              This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION

  395. 

  396.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */

  397. 

  398. } LL_ADC_InitTypeDef;

  399. 

  400. /**

  401.   * @brief  Structure definition of some features of ADC group regular.

  402.   * @note   These parameters have an impact on ADC scope: ADC group regular.

  403.   *         Refer to corresponding unitary functions into

  404.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  405.   *         (functions with prefix "REG").

  406.   * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()

  407.   *         is conditioned to ADC state:

  408.   *         ADC instance must be disabled.

  409.   *         This condition is applied to all ADC features, for efficiency

  410.   *         and compatibility over all STM32 families. However, the different

  411.   *         features can be set under different ADC state conditions

  412.   *         (setting possible with ADC enabled without conversion on going,

  413.   *         ADC enabled with conversion on going, ...)

  414.   *         Each feature can be updated afterwards with a unitary function

  415.   *         and potentially with ADC in a different state than disabled,

  416.   *         refer to description of each function for setting

  417.   *         conditioned to ADC state.

  418.   */

  419. typedef struct

  420. {

  421.   uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

  422.                                              This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE

  423.                                              @note On this STM32 serie, setting of external trigger edge is performed

  424.                                                    using function @ref LL_ADC_REG_StartConversionExtTrig().

  425. 

  426.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */

  427. 

  428.   uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.

  429.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

  430.                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

  431. 

  432.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */

  433. 

  434.   uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  435.                                              This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE

  436.                                              @note This parameter has an effect only if group regular sequencer is enabled

  437.                                                    (scan length of 2 ranks or more).

  438. 

  439.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */

  440. 

  441.   uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).

  442.                                              This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE

  443.                                              Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

  444. 

  445.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */

  446. 

  447.   uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.

  448.                                              This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER

  449. 

  450.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */

  451. 

  452. } LL_ADC_REG_InitTypeDef;

  453. 

  454. /**

  455.   * @brief  Structure definition of some features of ADC group injected.

  456.   * @note   These parameters have an impact on ADC scope: ADC group injected.

  457.   *         Refer to corresponding unitary functions into

  458.   *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

  459.   *         (functions with prefix "INJ").

  460.   * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()

  461.   *         is conditioned to ADC state:

  462.   *         ADC instance must be disabled.

  463.   *         This condition is applied to all ADC features, for efficiency

  464.   *         and compatibility over all STM32 families. However, the different

  465.   *         features can be set under different ADC state conditions

  466.   *         (setting possible with ADC enabled without conversion on going,

  467.   *         ADC enabled with conversion on going, ...)

  468.   *         Each feature can be updated afterwards with a unitary function

  469.   *         and potentially with ADC in a different state than disabled,

  470.   *         refer to description of each function for setting

  471.   *         conditioned to ADC state.

  472.   */

  473. typedef struct

  474. {

  475.   uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).

  476.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE

  477.                                              @note On this STM32 serie, setting of external trigger edge is performed

  478.                                                    using function @ref LL_ADC_INJ_StartConversionExtTrig().

  479. 

  480.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */

  481. 

  482.   uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.

  483.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

  484.                                              @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').

  485. 

  486.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */

  487. 

  488.   uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

  489.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE

  490.                                              @note This parameter has an effect only if group injected sequencer is enabled

  491.                                                    (scan length of 2 ranks or more).

  492. 

  493.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */

  494. 

  495.   uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.

  496.                                              This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO

  497.                                              Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

  498. 

  499.                                              This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */

  500. 

  501. } LL_ADC_INJ_InitTypeDef;

  502. 

  503. /**

  504.   * @}

  505.   */

  506. #endif /* USE_FULL_LL_DRIVER */

  507. 

  508. /* Exported constants --------------------------------------------------------*/

  509. /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants

  510.   * @{

  511.   */

  512. 

  513. /** @defgroup ADC_LL_EC_FLAG ADC flags

  514.   * @brief    Flags defines which can be used with LL_ADC_ReadReg function

  515.   * @{

  516.   */

  517. #define LL_ADC_FLAG_STRT                   ADC_SR_STRT        /*!< ADC flag ADC group regular conversion start */

  518. #define LL_ADC_FLAG_EOCS                   ADC_SR_EOC         /*!< ADC flag ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  519. #define LL_ADC_FLAG_OVR                    ADC_SR_OVR         /*!< ADC flag ADC group regular overrun */

  520. #define LL_ADC_FLAG_JSTRT                  ADC_SR_JSTRT       /*!< ADC flag ADC group injected conversion start */

  521. #define LL_ADC_FLAG_JEOS                   ADC_SR_JEOC        /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  522. #define LL_ADC_FLAG_AWD1                   ADC_SR_AWD         /*!< ADC flag ADC analog watchdog 1 */

  523. #define LL_ADC_FLAG_EOCS_MST               ADC_CSR_EOC1       /*!< ADC flag ADC multimode master group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  524. #define LL_ADC_FLAG_EOCS_SLV1              ADC_CSR_EOC2       /*!< ADC flag ADC multimode slave 1 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  525. #define LL_ADC_FLAG_EOCS_SLV2              ADC_CSR_EOC3       /*!< ADC flag ADC multimode slave 2 group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  526. #define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR1    /*!< ADC flag ADC multimode master group regular overrun */

  527. #define LL_ADC_FLAG_OVR_SLV1               ADC_CSR_OVR2   /*!< ADC flag ADC multimode slave 1 group regular overrun */

  528. #define LL_ADC_FLAG_OVR_SLV2               ADC_CSR_OVR3   /*!< ADC flag ADC multimode slave 2 group regular overrun */

  529. #define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOC1     /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  530. #define LL_ADC_FLAG_JEOS_SLV1              ADC_CSR_JEOC2  /*!< ADC flag ADC multimode slave 1 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  531. #define LL_ADC_FLAG_JEOS_SLV2              ADC_CSR_JEOC3  /*!< ADC flag ADC multimode slave 2 group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  532. #define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1       /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */

  533. #define LL_ADC_FLAG_AWD1_SLV1              ADC_CSR_AWD2       /*!< ADC flag ADC multimode slave 1 analog watchdog 1 */

  534. #define LL_ADC_FLAG_AWD1_SLV2              ADC_CSR_AWD3       /*!< ADC flag ADC multimode slave 2 analog watchdog 1 */

  535. /**

  536.   * @}

  537.   */

  538. 

  539. /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)

  540.   * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions

  541.   * @{

  542.   */

  543. #define LL_ADC_IT_EOCS                     ADC_CR1_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion or sequence conversions (to configure flag of end of conversion, use function @ref LL_ADC_REG_SetFlagEndOfConversion() ) */

  544. #define LL_ADC_IT_OVR                      ADC_CR1_OVRIE      /*!< ADC interruption ADC group regular overrun */

  545. #define LL_ADC_IT_JEOS                     ADC_CR1_JEOCIE     /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */

  546. #define LL_ADC_IT_AWD1                     ADC_CR1_AWDIE      /*!< ADC interruption ADC analog watchdog 1 */

  547. /**

  548.   * @}

  549.   */

  550. 

  551. /** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose

  552.   * @{

  553.   */

  554. /* List of ADC registers intended to be used (most commonly) with             */

  555. /* DMA transfer.                                                              */

  556. /* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */

  557. #define LL_ADC_DMA_REG_REGULAR_DATA          0x00000000U   /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

  558. #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    0x00000001U   /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

  559. /**

  560.   * @}

  561.   */

  562. 

  563. /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

  564.   * @{

  565.   */

  566. #define LL_ADC_CLOCK_SYNC_PCLK_DIV2        0x00000000U                                           /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */

  567. #define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (                   ADC_CCR_ADCPRE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */

  568. #define LL_ADC_CLOCK_SYNC_PCLK_DIV6        (ADC_CCR_ADCPRE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 6 */

  569. #define LL_ADC_CLOCK_SYNC_PCLK_DIV8        (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 8 */

  570. /**

  571.   * @}

  572.   */

  573. 

  574. /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels

  575.   * @{

  576.   */

  577. /* Note: Other measurement paths to internal channels may be available        */

  578. /*       (connections to other peripherals).                                  */

  579. /*       If they are not listed below, they do not require any specific       */

  580. /*       path enable. In this case, Access to measurement path is done        */

  581. /*       only by selecting the corresponding ADC internal channel.            */

  582. #define LL_ADC_PATH_INTERNAL_NONE          0x00000000U            /*!< ADC measurement pathes all disabled */

  583. #define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel VrefInt */

  584. #define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSVREFE)      /*!< ADC measurement path to internal channel temperature sensor */

  585. #define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATE)        /*!< ADC measurement path to internal channel Vbat */

  586. /**

  587.   * @}

  588.   */

  589. 

  590. /** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution

  591.   * @{

  592.   */

  593. #define LL_ADC_RESOLUTION_12B              0x00000000U                         /*!< ADC resolution 12 bits */

  594. #define LL_ADC_RESOLUTION_10B              (                ADC_CR1_RES_0)     /*!< ADC resolution 10 bits */

  595. #define LL_ADC_RESOLUTION_8B               (ADC_CR1_RES_1                )     /*!< ADC resolution  8 bits */

  596. #define LL_ADC_RESOLUTION_6B               (ADC_CR1_RES_1 | ADC_CR1_RES_0)     /*!< ADC resolution  6 bits */

  597. /**

  598.   * @}

  599.   */

  600. 

  601. /** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment

  602.   * @{

  603.   */

  604. #define LL_ADC_DATA_ALIGN_RIGHT            0x00000000U            /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/

  605. #define LL_ADC_DATA_ALIGN_LEFT             (ADC_CR2_ALIGN)        /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/

  606. /**

  607.   * @}

  608.   */

  609. 

  610. /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection

  611.   * @{

  612.   */

  613. #define LL_ADC_SEQ_SCAN_DISABLE            0x00000000U    /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/

  614. #define LL_ADC_SEQ_SCAN_ENABLE             (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */

  615. /**

  616.   * @}

  617.   */

  618. 

  619. /** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups

  620.   * @{

  621.   */

  622. #define LL_ADC_GROUP_REGULAR               0x00000001U   /*!< ADC group regular (available on all STM32 devices) */

  623. #define LL_ADC_GROUP_INJECTED              0x00000002U   /*!< ADC group injected (not available on all STM32 devices)*/

  624. #define LL_ADC_GROUP_REGULAR_INJECTED      0x00000003U   /*!< ADC both groups regular and injected */

  625. /**

  626.   * @}

  627.   */

  628. 

  629. /** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number

  630.   * @{

  631.   */

  632. #define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

  633. #define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

  634. #define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

  635. #define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

  636. #define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

  637. #define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

  638. #define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

  639. #define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

  640. #define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

  641. #define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP)  /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

  642. #define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

  643. #define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

  644. #define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

  645. #define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

  646. #define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

  647. #define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

  648. #define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

  649. #define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

  650. #define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

  651. #define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F7, ADC channel available only on ADC instance: ADC1. */

  652. #define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F7, ADC channel available only on ADC instance: ADC1. */

  653. #define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F7, ADC channel available only on ADC instance: ADC1. */

  654. 

  655. /**

  656.   * @}

  657.   */

  658. 

  659. /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source

  660.   * @{

  661.   */

  662. #define LL_ADC_REG_TRIG_SOFTWARE           0x00000000U                                                                                                 /*!< ADC group regular conversion trigger internal: SW start. */

  663. #define LL_ADC_REG_TRIG_EXT_TIM1_CH1       ((uint32_t)ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  664. #define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  665. #define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  666. #define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  667. #define LL_ADC_REG_TRIG_EXT_TIM5_TRGO      (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */

  668. #define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  669. #define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  670. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */

  671. #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                          /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */

  672. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */

  673. #define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */

  674. #define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                    /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  675. #define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                       /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */

  676. #define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CR2_EXTSEL_3 |ADC_CR2_EXTSEL_2| ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                      /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */

  677. #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */

  678. 

  679. /**

  680.   * @}

  681.   */

  682. 

  683. /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge

  684.   * @{

  685.   */

  686. #define LL_ADC_REG_TRIG_EXT_RISING         (                  ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to rising edge */

  687. #define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CR2_EXTEN_1                  )     /*!< ADC group regular conversion trigger polarity set to falling edge */

  688. #define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0)     /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

  689. /**

  690.   * @}

  691.   */

  692. 

  693. /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode

  694. * @{

  695. */

  696. #define LL_ADC_REG_CONV_SINGLE             0x00000000U             /*!< ADC conversions are performed in single mode: one conversion per trigger */

  697. #define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CR2_CONT)          /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */

  698. /**

  699.   * @}

  700.   */

  701. 

  702. /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data

  703.   * @{

  704.   */

  705. #define LL_ADC_REG_DMA_TRANSFER_NONE       0x00000000U              /*!< ADC conversions are not transferred by DMA */

  706. #define LL_ADC_REG_DMA_TRANSFER_LIMITED    (              ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */

  707. #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CR2_DDS | ADC_CR2_DMA)          /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */

  708. /**

  709.   * @}

  710.   */

  711. 

  712. /** @defgroup ADC_LL_EC_REG_FLAG_EOC_SELECTION ADC group regular - Flag EOC selection (unitary or sequence conversions)

  713.   * @{

  714.   */

  715. #define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV       0x00000000U    /*!< ADC flag EOC (end of unitary conversion) selected */

  716. #define LL_ADC_REG_FLAG_EOC_UNITARY_CONV        (ADC_CR2_EOCS) /*!< ADC flag EOS (end of sequence conversions) selected */

  717. /**

  718.   * @}

  719.   */

  720. 

  721. /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length

  722.   * @{

  723.   */

  724. #define LL_ADC_REG_SEQ_SCAN_DISABLE        0x00000000U                                                 /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  725. #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

  726. #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

  727. #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

  728. #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

  729. #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

  730. #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

  731. #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

  732. #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */

  733. #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */

  734. #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */

  735. #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */

  736. #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */

  737. #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */

  738. #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */

  739. #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */

  740. /**

  741.   * @}

  742.   */

  743. 

  744. /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode

  745.   * @{

  746.   */

  747. #define LL_ADC_REG_SEQ_DISCONT_DISABLE     0x00000000U                                                                  /*!< ADC group regular sequencer discontinuous mode disable */

  748. #define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                            ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

  749. #define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                        ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */

  750. #define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                    ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */

  751. #define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                    ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */

  752. #define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CR1_DISCNUM_2                                         | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */

  753. #define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CR1_DISCNUM_2                     | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */

  754. #define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1                     | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */

  755. #define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */

  756. /**

  757.   * @}

  758.   */

  759. 

  760. /** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

  761.   * @{

  762.   */

  763. #define LL_ADC_REG_RANK_1                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

  764. #define LL_ADC_REG_RANK_2                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

  765. #define LL_ADC_REG_RANK_3                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

  766. #define LL_ADC_REG_RANK_4                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

  767. #define LL_ADC_REG_RANK_5                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

  768. #define LL_ADC_REG_RANK_6                  (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

  769. #define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

  770. #define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

  771. #define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */

  772. #define LL_ADC_REG_RANK_10                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */

  773. #define LL_ADC_REG_RANK_11                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */

  774. #define LL_ADC_REG_RANK_12                 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */

  775. #define LL_ADC_REG_RANK_13                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */

  776. #define LL_ADC_REG_RANK_14                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */

  777. #define LL_ADC_REG_RANK_15                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */

  778. #define LL_ADC_REG_RANK_16                 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */

  779. /**

  780.   * @}

  781.   */

  782. 

  783. /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source

  784.   * @{

  785.   */

  786. #define LL_ADC_INJ_TRIG_SOFTWARE           0x00000000U                                                                                                     /*!< ADC group injected conversion trigger internal: SW start. */

  787. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                 /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */

  788. #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  789. #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */

  790. #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  791. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  792. #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */

  793. #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  794. #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                             /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */

  795. #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */

  796. #define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */

  797. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  798. #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                         /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */

  799. #define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

  800. #define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */

  801. 

  802. /**

  803.   * @}

  804.   */

  805. 

  806. /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge

  807.   * @{

  808.   */

  809. #define LL_ADC_INJ_TRIG_EXT_RISING         (                   ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to rising edge */

  810. #define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_CR2_JEXTEN_1                   )   /*!< ADC group injected conversion trigger polarity set to falling edge */

  811. #define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0)   /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */

  812. /**

  813.   * @}

  814.   */

  815. 

  816. /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode

  817. * @{

  818. */

  819. #define LL_ADC_INJ_TRIG_INDEPENDENT        0x00000000U            /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */

  820. #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CR1_JAUTO)        /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */

  821. /**

  822.   * @}

  823.   */

  824. 

  825. 

  826. /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length

  827.   * @{

  828.   */

  829. #define LL_ADC_INJ_SEQ_SCAN_DISABLE        0x00000000U                     /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

  830. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */

  831. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */

  832. #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */

  833. /**

  834.   * @}

  835.   */

  836. 

  837. /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode

  838.   * @{

  839.   */

  840. #define LL_ADC_INJ_SEQ_DISCONT_DISABLE     0x00000000U            /*!< ADC group injected sequencer discontinuous mode disable */

  841. #define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CR1_JDISCEN)      /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */

  842. /**

  843.   * @}

  844.   */

  845. 

  846. /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

  847.   * @{

  848.   */

  849. #define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */

  850. #define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */

  851. #define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */

  852. #define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */

  853. /**

  854.   * @}

  855.   */

  856. 

  857. /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

  858.   * @{

  859.   */

  860. #define LL_ADC_SAMPLINGTIME_3CYCLES        0x00000000U                                              /*!< Sampling time 3 ADC clock cycles */

  861. #define LL_ADC_SAMPLINGTIME_15CYCLES       (ADC_SMPR1_SMP10_0)                                      /*!< Sampling time 15 ADC clock cycles */

  862. #define LL_ADC_SAMPLINGTIME_28CYCLES       (ADC_SMPR1_SMP10_1)                                      /*!< Sampling time 28 ADC clock cycles */

  863. #define LL_ADC_SAMPLINGTIME_56CYCLES       (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)                  /*!< Sampling time 56 ADC clock cycles */

  864. #define LL_ADC_SAMPLINGTIME_84CYCLES       (ADC_SMPR1_SMP10_2)                                      /*!< Sampling time 84 ADC clock cycles */

  865. #define LL_ADC_SAMPLINGTIME_112CYCLES      (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)                  /*!< Sampling time 112 ADC clock cycles */

  866. #define LL_ADC_SAMPLINGTIME_144CYCLES      (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)                  /*!< Sampling time 144 ADC clock cycles */

  867. #define LL_ADC_SAMPLINGTIME_480CYCLES      (ADC_SMPR1_SMP10)                                        /*!< Sampling time 480 ADC clock cycles */

  868. /**

  869.   * @}

  870.   */

  871. 

  872. /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

  873.   * @{

  874.   */

  875. #define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */

  876. /**

  877.   * @}

  878.   */

  879. 

  880. /** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels

  881.   * @{

  882.   */

  883. #define LL_ADC_AWD_DISABLE                 0x00000000U                                                                                   /*!< ADC analog watchdog monitoring disabled */

  884. #define LL_ADC_AWD_ALL_CHANNELS_REG        (                                                             ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

  885. #define LL_ADC_AWD_ALL_CHANNELS_INJ        (                                            ADC_CR1_JAWDEN                                 ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */

  886. #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (                                            ADC_CR1_JAWDEN | ADC_CR1_AWDEN                 ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */

  887. #define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

  888. #define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */

  889. #define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */

  890. #define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

  891. #define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */

  892. #define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */

  893. #define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

  894. #define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */

  895. #define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */

  896. #define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

  897. #define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */

  898. #define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */

  899. #define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

  900. #define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */

  901. #define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */

  902. #define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

  903. #define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */

  904. #define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */

  905. #define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

  906. #define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */

  907. #define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */

  908. #define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

  909. #define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */

  910. #define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */

  911. #define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

  912. #define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */

  913. #define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */

  914. #define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

  915. #define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */

  916. #define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */

  917. #define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

  918. #define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */

  919. #define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */

  920. #define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

  921. #define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */

  922. #define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */

  923. #define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

  924. #define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */

  925. #define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */

  926. #define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

  927. #define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */

  928. #define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */

  929. #define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

  930. #define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */

  931. #define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */

  932. #define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

  933. #define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */

  934. #define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */

  935. #define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

  936. #define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */

  937. #define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */

  938. #define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

  939. #define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */

  940. #define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */

  941. #define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

  942. #define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */

  943. #define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */

  944. #define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */

  945. #define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */

  946. #define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */

  947. #define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */

  948. #define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */

  949. #define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT       & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */

  950. #define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK)                  | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */

  951. #define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN                 | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */

  952. #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */

  953. /**

  954.   * @}

  955.   */

  956. 

  957. /** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds

  958.   * @{

  959.   */

  960. #define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */

  961. #define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD_TR1_LOW_REGOFFSET)  /*!< ADC analog watchdog threshold low */

  962. /**

  963.   * @}

  964.   */

  965. 

  966. /** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode

  967.   * @{

  968.   */

  969. #define LL_ADC_MULTI_INDEPENDENT           0x00000000U                                                             /*!< ADC dual mode disabled (ADC independent mode) */

  970. #define LL_ADC_MULTI_DUAL_REG_SIMULT       (                  ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1                  ) /*!< ADC dual mode enabled: group regular simultaneous */

  971. #define LL_ADC_MULTI_DUAL_REG_INTERL       (                  ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved */

  972. #define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                  ADC_CCR_MULTI_2                   | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected simultaneous */

  973. #define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_MULTI_3                                     | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */

  974. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                      ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */

  975. #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                    ADC_CCR_MULTI_1                  ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */

  976. #define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                    ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */

  977. #if defined(ADC3)

  978. #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM  (ADC_CCR_MULTI_4                                                       | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected simultaneous */

  979. #define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT  (ADC_CCR_MULTI_4                                     | ADC_CCR_MULTI_1                  ) /*!< ADC triple mode enabled: Combined group regular simultaneous + group injected alternate trigger */

  980. #define LL_ADC_MULTI_TRIPLE_INJ_SIMULT       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2                   | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected simultaneous */

  981. #define LL_ADC_MULTI_TRIPLE_REG_SIMULT       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1                  ) /*!< ADC triple mode enabled: group regular simultaneous */

  982. #define LL_ADC_MULTI_TRIPLE_REG_INTERL       (ADC_CCR_MULTI_4                   | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: Combined group regular interleaved */

  983. #define LL_ADC_MULTI_TRIPLE_INJ_ALTERN       (ADC_CCR_MULTI_4                                                       | ADC_CCR_MULTI_0) /*!< ADC triple mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */

  984. #endif

  985. /**

  986.   * @}

  987.   */

  988. 

  989. /** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer

  990.   * @{

  991.   */

  992. #define LL_ADC_MULTI_REG_DMA_EACH_ADC        0x00000000U                                   /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */

  993. #define LL_ADC_MULTI_REG_DMA_LIMIT_1         (                              ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */

  994. #define LL_ADC_MULTI_REG_DMA_LIMIT_2         (              ADC_CCR_DMA_1                ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words one by one, ADC2&1 then ADC1&3 then ADC3&2. */

  995. #define LL_ADC_MULTI_REG_DMA_LIMIT_3         (              ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */

  996. #define LL_ADC_MULTI_REG_DMA_UNLMT_1         (ADC_CCR_DDS |                 ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 1: 2 or 3 (dual or triple mode) half-words one by one, ADC1 then ADC2 then ADC3. */

  997. #define LL_ADC_MULTI_REG_DMA_UNLMT_2         (ADC_CCR_DDS | ADC_CCR_DMA_1                ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 2: 2 or 3 (dual or triple mode) half-words by pairs, ADC2&1 then ADC1&3 then ADC3&2. */

  998. #define LL_ADC_MULTI_REG_DMA_UNLMT_3         (ADC_CCR_DDS | ADC_CCR_DMA_0 | ADC_CCR_DMA_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for all ADC instances (DMA of ADC master), in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. Setting of DMA mode 3: 2 or 3 (dual or triple mode) bytes one by one, ADC2&1 then ADC1&3 then ADC3&2. */

  999. /**

  1000.   * @}

  1001.   */

  1002. 

  1003. /** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases

  1004.   * @{

  1005.   */

  1006. #define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  0x00000000U                                                             /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles*/

  1007. #define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */

  1008. #define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */

  1009. #define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */

  1010. #define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */

  1011. #define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */

  1012. #define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */

  1013. #define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */

  1014. #define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 13 ADC clock cycles */

  1015. #define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3                                     | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 14 ADC clock cycles */

  1016. #define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 15 ADC clock cycles */

  1017. #define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3                   | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 16 ADC clock cycles */

  1018. #define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 17 ADC clock cycles */

  1019. #define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 18 ADC clock cycles */

  1020. #define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 19 ADC clock cycles */

  1021. #define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 20 ADC clock cycles */

  1022. /**

  1023.   * @}

  1024.   */

  1025. 

  1026. /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave

  1027.   * @{

  1028.   */

  1029. #define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */

  1030. #define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */

  1031. #define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */

  1032. /**

  1033.   * @}

  1034.   */

  1035. 

  1036. 

  1037. 

  1038. /** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays

  1039.   * @note   Only ADC IP HW delays are defined in ADC LL driver driver,

  1040.   *         not timeout values.

  1041.   *         For details on delays values, refer to descriptions in source code

  1042.   *         above each literal definition.

  1043.   * @{

  1044.   */

  1045. 

  1046. /* Note: Only ADC IP HW delays are defined in ADC LL driver driver,           */

  1047. /*       not timeout values.                                                  */

  1048. /*       Timeout values for ADC operations are dependent to device clock      */

  1049. /*       configuration (system clock versus ADC clock),                       */

  1050. /*       and therefore must be defined in user application.                   */

  1051. /*       Indications for estimation of ADC timeout delays, for this           */

  1052. /*       STM32 serie:                                                         */

  1053. /*       - ADC enable time: maximum delay is 2us                              */

  1054. /*         (refer to device datasheet, parameter "tSTAB")                     */

  1055. /*       - ADC conversion time: duration depending on ADC clock and ADC       */

  1056. /*         configuration.                                                     */

  1057. /*         (refer to device reference manual, section "Timing")               */

  1058. 

  1059. /* Delay for internal voltage reference stabilization time.                   */

  1060. /* Delay set to maximum value (refer to device datasheet,                     */

  1061. /* parameter "tSTART").                                                       */

  1062. /* Unit: us                                                                   */

  1063. #define LL_ADC_DELAY_VREFINT_STAB_US       (  10U)  /*!< Delay for internal voltage reference stabilization time */

  1064. 

  1065. /* Delay for temperature sensor stabilization time.                           */

  1066. /* Literal set to maximum value (refer to device datasheet,                   */

  1067. /* parameter "tSTART").                                                       */

  1068. /* Unit: us                                                                   */

  1069. #define LL_ADC_DELAY_TEMPSENSOR_STAB_US    (  10U)  /*!< Delay for internal voltage reference stabilization time */

  1070. 

  1071. /**

  1072.   * @}

  1073.   */

  1074. 

  1075. /**

  1076.   * @}

  1077.   */

  1078. 

  1079. 

  1080. /* Exported macro ------------------------------------------------------------*/

  1081. /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros

  1082.   * @{

  1083.   */

  1084. 

  1085. /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros

  1086.   * @{

  1087.   */

  1088. 

  1089. /**

  1090.   * @brief  Write a value in ADC register

  1091.   * @param  __INSTANCE__ ADC Instance

  1092.   * @param  __REG__ Register to be written

  1093.   * @param  __VALUE__ Value to be written in the register

  1094.   * @retval None

  1095.   */

  1096. #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

  1097. 

  1098. /**

  1099.   * @brief  Read a value in ADC register

  1100.   * @param  __INSTANCE__ ADC Instance

  1101.   * @param  __REG__ Register to be read

  1102.   * @retval Register value

  1103.   */

  1104. #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

  1105. /**

  1106.   * @}

  1107.   */

  1108. 

  1109. /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro

  1110.   * @{

  1111.   */

  1112. 

  1113. /**

  1114.   * @brief  Helper macro to get ADC channel number in decimal format

  1115.   *         from literals LL_ADC_CHANNEL_x.

  1116.   * @note   Example:

  1117.   *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)

  1118.   *           will return decimal number "4".

  1119.   * @note   The input can be a value from functions where a channel

  1120.   *         number is returned, either defined with number

  1121.   *         or with bitfield (only one bit must be set).

  1122.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1123.   *         @arg @ref LL_ADC_CHANNEL_0

  1124.   *         @arg @ref LL_ADC_CHANNEL_1

  1125.   *         @arg @ref LL_ADC_CHANNEL_2

  1126.   *         @arg @ref LL_ADC_CHANNEL_3

  1127.   *         @arg @ref LL_ADC_CHANNEL_4

  1128.   *         @arg @ref LL_ADC_CHANNEL_5

  1129.   *         @arg @ref LL_ADC_CHANNEL_6

  1130.   *         @arg @ref LL_ADC_CHANNEL_7

  1131.   *         @arg @ref LL_ADC_CHANNEL_8

  1132.   *         @arg @ref LL_ADC_CHANNEL_9

  1133.   *         @arg @ref LL_ADC_CHANNEL_10

  1134.   *         @arg @ref LL_ADC_CHANNEL_11

  1135.   *         @arg @ref LL_ADC_CHANNEL_12

  1136.   *         @arg @ref LL_ADC_CHANNEL_13

  1137.   *         @arg @ref LL_ADC_CHANNEL_14

  1138.   *         @arg @ref LL_ADC_CHANNEL_15

  1139.   *         @arg @ref LL_ADC_CHANNEL_16

  1140.   *         @arg @ref LL_ADC_CHANNEL_17

  1141.   *         @arg @ref LL_ADC_CHANNEL_18

  1142.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1143.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  1144.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1145.   *

  1146.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  1147.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  1148.   * @retval Value between Min_Data=0 and Max_Data=18

  1149.   */

  1150. #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \

  1151.   (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)

  1152. 

  1153. /**

  1154.   * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x

  1155.   *         from number in decimal format.

  1156.   * @note   Example:

  1157.   *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)

  1158.   *           will return a data equivalent to "LL_ADC_CHANNEL_4".

  1159.   * @param  __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18

  1160.   * @retval Returned value can be one of the following values:

  1161.   *         @arg @ref LL_ADC_CHANNEL_0

  1162.   *         @arg @ref LL_ADC_CHANNEL_1

  1163.   *         @arg @ref LL_ADC_CHANNEL_2

  1164.   *         @arg @ref LL_ADC_CHANNEL_3

  1165.   *         @arg @ref LL_ADC_CHANNEL_4

  1166.   *         @arg @ref LL_ADC_CHANNEL_5

  1167.   *         @arg @ref LL_ADC_CHANNEL_6

  1168.   *         @arg @ref LL_ADC_CHANNEL_7

  1169.   *         @arg @ref LL_ADC_CHANNEL_8

  1170.   *         @arg @ref LL_ADC_CHANNEL_9

  1171.   *         @arg @ref LL_ADC_CHANNEL_10

  1172.   *         @arg @ref LL_ADC_CHANNEL_11

  1173.   *         @arg @ref LL_ADC_CHANNEL_12

  1174.   *         @arg @ref LL_ADC_CHANNEL_13

  1175.   *         @arg @ref LL_ADC_CHANNEL_14

  1176.   *         @arg @ref LL_ADC_CHANNEL_15

  1177.   *         @arg @ref LL_ADC_CHANNEL_16

  1178.   *         @arg @ref LL_ADC_CHANNEL_17

  1179.   *         @arg @ref LL_ADC_CHANNEL_18

  1180.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1181.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  1182.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1183.   *

  1184.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  1185.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n

  1186.   *         (1) For ADC channel read back from ADC register,

  1187.   *             comparison with internal channel parameter to be done

  1188.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1189.   */

  1190. #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                          \

  1191.   (((__DECIMAL_NB__) <= 9U)                                                                                     \

  1192.     ? (                                                                                                         \

  1193.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                       |        \

  1194.        (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))         \

  1195.       )                                                                                                         \

  1196.       :                                                                                                         \

  1197.       (                                                                                                         \

  1198.        ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                              | \

  1199.        (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \

  1200.       )                                                                                                         \

  1201.   )

  1202. 

  1203. /**

  1204.   * @brief  Helper macro to determine whether the selected channel

  1205.   *         corresponds to literal definitions of driver.

  1206.   * @note   The different literal definitions of ADC channels are:

  1207.   *         - ADC internal channel:

  1208.   *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...

  1209.   *         - ADC external channel (channel connected to a GPIO pin):

  1210.   *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...

  1211.   * @note   The channel parameter must be a value defined from literal

  1212.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1213.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1214.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),

  1215.   *         must not be a value from functions where a channel number is

  1216.   *         returned from ADC registers,

  1217.   *         because internal and external channels share the same channel

  1218.   *         number in ADC registers. The differentiation is made only with

  1219.   *         parameters definitions of driver.

  1220.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1221.   *         @arg @ref LL_ADC_CHANNEL_0

  1222.   *         @arg @ref LL_ADC_CHANNEL_1

  1223.   *         @arg @ref LL_ADC_CHANNEL_2

  1224.   *         @arg @ref LL_ADC_CHANNEL_3

  1225.   *         @arg @ref LL_ADC_CHANNEL_4

  1226.   *         @arg @ref LL_ADC_CHANNEL_5

  1227.   *         @arg @ref LL_ADC_CHANNEL_6

  1228.   *         @arg @ref LL_ADC_CHANNEL_7

  1229.   *         @arg @ref LL_ADC_CHANNEL_8

  1230.   *         @arg @ref LL_ADC_CHANNEL_9

  1231.   *         @arg @ref LL_ADC_CHANNEL_10

  1232.   *         @arg @ref LL_ADC_CHANNEL_11

  1233.   *         @arg @ref LL_ADC_CHANNEL_12

  1234.   *         @arg @ref LL_ADC_CHANNEL_13

  1235.   *         @arg @ref LL_ADC_CHANNEL_14

  1236.   *         @arg @ref LL_ADC_CHANNEL_15

  1237.   *         @arg @ref LL_ADC_CHANNEL_16

  1238.   *         @arg @ref LL_ADC_CHANNEL_17

  1239.   *         @arg @ref LL_ADC_CHANNEL_18

  1240.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1241.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  1242.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1243.   *

  1244.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  1245.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  1246.   * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

  1247.   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

  1248.   */

  1249. #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \

  1250.   (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)

  1251. 

  1252. /**

  1253.   * @brief  Helper macro to convert a channel defined from parameter

  1254.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1255.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1256.   *         to its equivalent parameter definition of a ADC external channel

  1257.   *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

  1258.   * @note   The channel parameter can be, additionally to a value

  1259.   *         defined from parameter definition of a ADC internal channel

  1260.   *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1261.   *         a value defined from parameter definition of

  1262.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1263.   *         or a value from functions where a channel number is returned

  1264.   *         from ADC registers.

  1265.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1266.   *         @arg @ref LL_ADC_CHANNEL_0

  1267.   *         @arg @ref LL_ADC_CHANNEL_1

  1268.   *         @arg @ref LL_ADC_CHANNEL_2

  1269.   *         @arg @ref LL_ADC_CHANNEL_3

  1270.   *         @arg @ref LL_ADC_CHANNEL_4

  1271.   *         @arg @ref LL_ADC_CHANNEL_5

  1272.   *         @arg @ref LL_ADC_CHANNEL_6

  1273.   *         @arg @ref LL_ADC_CHANNEL_7

  1274.   *         @arg @ref LL_ADC_CHANNEL_8

  1275.   *         @arg @ref LL_ADC_CHANNEL_9

  1276.   *         @arg @ref LL_ADC_CHANNEL_10

  1277.   *         @arg @ref LL_ADC_CHANNEL_11

  1278.   *         @arg @ref LL_ADC_CHANNEL_12

  1279.   *         @arg @ref LL_ADC_CHANNEL_13

  1280.   *         @arg @ref LL_ADC_CHANNEL_14

  1281.   *         @arg @ref LL_ADC_CHANNEL_15

  1282.   *         @arg @ref LL_ADC_CHANNEL_16

  1283.   *         @arg @ref LL_ADC_CHANNEL_17

  1284.   *         @arg @ref LL_ADC_CHANNEL_18

  1285.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1286.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  1287.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1288.   *

  1289.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  1290.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  1291.   * @retval Returned value can be one of the following values:

  1292.   *         @arg @ref LL_ADC_CHANNEL_0

  1293.   *         @arg @ref LL_ADC_CHANNEL_1

  1294.   *         @arg @ref LL_ADC_CHANNEL_2

  1295.   *         @arg @ref LL_ADC_CHANNEL_3

  1296.   *         @arg @ref LL_ADC_CHANNEL_4

  1297.   *         @arg @ref LL_ADC_CHANNEL_5

  1298.   *         @arg @ref LL_ADC_CHANNEL_6

  1299.   *         @arg @ref LL_ADC_CHANNEL_7

  1300.   *         @arg @ref LL_ADC_CHANNEL_8

  1301.   *         @arg @ref LL_ADC_CHANNEL_9

  1302.   *         @arg @ref LL_ADC_CHANNEL_10

  1303.   *         @arg @ref LL_ADC_CHANNEL_11

  1304.   *         @arg @ref LL_ADC_CHANNEL_12

  1305.   *         @arg @ref LL_ADC_CHANNEL_13

  1306.   *         @arg @ref LL_ADC_CHANNEL_14

  1307.   *         @arg @ref LL_ADC_CHANNEL_15

  1308.   *         @arg @ref LL_ADC_CHANNEL_16

  1309.   *         @arg @ref LL_ADC_CHANNEL_17

  1310.   *         @arg @ref LL_ADC_CHANNEL_18

  1311.   */

  1312. #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \

  1313.   ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

  1314. 

  1315. /**

  1316.   * @brief  Helper macro to determine whether the internal channel

  1317.   *         selected is available on the ADC instance selected.

  1318.   * @note   The channel parameter must be a value defined from parameter

  1319.   *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

  1320.   *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

  1321.   *         must not be a value defined from parameter definition of

  1322.   *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

  1323.   *         or a value from functions where a channel number is

  1324.   *         returned from ADC registers,

  1325.   *         because internal and external channels share the same channel

  1326.   *         number in ADC registers. The differentiation is made only with

  1327.   *         parameters definitions of driver.

  1328.   * @param  __ADC_INSTANCE__ ADC instance

  1329.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1330.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1331.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  1332.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1333.   *

  1334.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.

  1335.   *         (2) On devices STM32F7x, limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  1336.   * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

  1337.   *         Value "1" if the internal channel selected is available on the ADC instance selected.

  1338.   */

  1339. #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

  1340.   (                                                                            \

  1341.    ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                             \

  1342.    ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)                                      \

  1343.   )

  1344. /**

  1345.   * @brief  Helper macro to define ADC analog watchdog parameter:

  1346.   *         define a single channel to monitor with analog watchdog

  1347.   *         from sequencer channel and groups definition.

  1348.   * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

  1349.   *         Example:

  1350.   *           LL_ADC_SetAnalogWDMonitChannels(

  1351.   *             ADC1, LL_ADC_AWD1,

  1352.   *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

  1353.   * @param  __CHANNEL__ This parameter can be one of the following values:

  1354.   *         @arg @ref LL_ADC_CHANNEL_0

  1355.   *         @arg @ref LL_ADC_CHANNEL_1

  1356.   *         @arg @ref LL_ADC_CHANNEL_2

  1357.   *         @arg @ref LL_ADC_CHANNEL_3

  1358.   *         @arg @ref LL_ADC_CHANNEL_4

  1359.   *         @arg @ref LL_ADC_CHANNEL_5

  1360.   *         @arg @ref LL_ADC_CHANNEL_6

  1361.   *         @arg @ref LL_ADC_CHANNEL_7

  1362.   *         @arg @ref LL_ADC_CHANNEL_8

  1363.   *         @arg @ref LL_ADC_CHANNEL_9

  1364.   *         @arg @ref LL_ADC_CHANNEL_10

  1365.   *         @arg @ref LL_ADC_CHANNEL_11

  1366.   *         @arg @ref LL_ADC_CHANNEL_12

  1367.   *         @arg @ref LL_ADC_CHANNEL_13

  1368.   *         @arg @ref LL_ADC_CHANNEL_14

  1369.   *         @arg @ref LL_ADC_CHANNEL_15

  1370.   *         @arg @ref LL_ADC_CHANNEL_16

  1371.   *         @arg @ref LL_ADC_CHANNEL_17

  1372.   *         @arg @ref LL_ADC_CHANNEL_18

  1373.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  1374.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  1375.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  1376.   *

  1377.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  1378.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n

  1379.   *         (1) For ADC channel read back from ADC register,

  1380.   *             comparison with internal channel parameter to be done

  1381.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  1382.   * @param  __GROUP__ This parameter can be one of the following values:

  1383.   *         @arg @ref LL_ADC_GROUP_REGULAR

  1384.   *         @arg @ref LL_ADC_GROUP_INJECTED

  1385.   *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED

  1386.   * @retval Returned value can be one of the following values:

  1387.   *         @arg @ref LL_ADC_AWD_DISABLE

  1388.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG

  1389.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ

  1390.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  1391.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG

  1392.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ

  1393.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  1394.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG

  1395.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ

  1396.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  1397.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG

  1398.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ

  1399.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  1400.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG

  1401.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ

  1402.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  1403.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG

  1404.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ

  1405.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  1406.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG

  1407.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ

  1408.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  1409.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG

  1410.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ

  1411.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  1412.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG

  1413.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ

  1414.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  1415.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG

  1416.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ

  1417.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  1418.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG

  1419.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ

  1420.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  1421.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG

  1422.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ

  1423.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  1424.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG

  1425.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ

  1426.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  1427.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG

  1428.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ

  1429.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  1430.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG

  1431.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ

  1432.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  1433.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG

  1434.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ

  1435.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  1436.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG

  1437.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ

  1438.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  1439.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG

  1440.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ

  1441.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  1442.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG

  1443.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ

  1444.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  1445.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG

  1446.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ

  1447.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  1448.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)

  1449.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)

  1450.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)

  1451.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)(2)

  1452.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)(2)

  1453.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)(2)

  1454.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (1)

  1455.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (1)

  1456.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ         (1)

  1457.   *

  1458.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  1459.   *         (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  1460.   */

  1461. #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

  1462.   (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \

  1463.     ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)                            \

  1464.       :                                                                                                   \

  1465.       ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                              \

  1466.        ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)                        \

  1467.          :                                                                                                \

  1468.          (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)        \

  1469.   )

  1470. 

  1471. /**

  1472.   * @brief  Helper macro to set the value of ADC analog watchdog threshold high

  1473.   *         or low in function of ADC resolution, when ADC resolution is

  1474.   *         different of 12 bits.

  1475.   * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().

  1476.   *         Example, with a ADC resolution of 8 bits, to set the value of

  1477.   *         analog watchdog threshold high (on 8 bits):

  1478.   *           LL_ADC_SetAnalogWDThresholds

  1479.   *            (< ADCx param >,

  1480.   *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)

  1481.   *            );

  1482.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1483.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1484.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1485.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1486.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1487.   * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1488.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1489.   */

  1490. #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \

  1491.   ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))

  1492. 

  1493. /**

  1494.   * @brief  Helper macro to get the value of ADC analog watchdog threshold high

  1495.   *         or low in function of ADC resolution, when ADC resolution is

  1496.   *         different of 12 bits.

  1497.   * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

  1498.   *         Example, with a ADC resolution of 8 bits, to get the value of

  1499.   *         analog watchdog threshold high (on 8 bits):

  1500.   *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION

  1501.   *            (LL_ADC_RESOLUTION_8B,

  1502.   *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)

  1503.   *            );

  1504.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1505.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1506.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1507.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1508.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1509.   * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1510.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1511.   */

  1512. #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \

  1513.   ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U )))

  1514. 

  1515. /**

  1516.   * @brief  Helper macro to get the ADC multimode conversion data of ADC master

  1517.   *         or ADC slave from raw value with both ADC conversion data concatenated.

  1518.   * @note   This macro is intended to be used when multimode transfer by DMA

  1519.   *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().

  1520.   *         In this case the transferred data need to processed with this macro

  1521.   *         to separate the conversion data of ADC master and ADC slave.

  1522.   * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:

  1523.   *         @arg @ref LL_ADC_MULTI_MASTER

  1524.   *         @arg @ref LL_ADC_MULTI_SLAVE

  1525.   * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF

  1526.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  1527.   */

  1528. #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \

  1529.   (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

  1530. 

  1531. /**

  1532.   * @brief  Helper macro to select the ADC common instance

  1533.   *         to which is belonging the selected ADC instance.

  1534.   * @note   ADC common register instance can be used for:

  1535.   *         - Set parameters common to several ADC instances

  1536.   *         - Multimode (for devices with several ADC instances)

  1537.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1538.   * @param  __ADCx__ ADC instance

  1539.   * @retval ADC common register instance

  1540.   */

  1541. #if defined(ADC1) && defined(ADC2) && defined(ADC3)

  1542. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  1543.   (ADC123_COMMON)

  1544. #elif defined(ADC1) && defined(ADC2)

  1545. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  1546.   (ADC12_COMMON)

  1547. #else

  1548. #define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

  1549.   (ADC1_COMMON)

  1550. #endif

  1551. 

  1552. /**

  1553.   * @brief  Helper macro to check if all ADC instances sharing the same

  1554.   *         ADC common instance are disabled.

  1555.   * @note   This check is required by functions with setting conditioned to

  1556.   *         ADC state:

  1557.   *         All ADC instances of the ADC common group must be disabled.

  1558.   *         Refer to functions having argument "ADCxy_COMMON" as parameter.

  1559.   * @note   On devices with only 1 ADC common instance, parameter of this macro

  1560.   *         is useless and can be ignored (parameter kept for compatibility

  1561.   *         with devices featuring several ADC common instances).

  1562.   * @param  __ADCXY_COMMON__ ADC common instance

  1563.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1564.   * @retval Value "0" if all ADC instances sharing the same ADC common instance

  1565.   *         are disabled.

  1566.   *         Value "1" if at least one ADC instance sharing the same ADC common instance

  1567.   *         is enabled.

  1568.   */

  1569. #if defined(ADC1) && defined(ADC2) && defined(ADC3)

  1570. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  1571.   (LL_ADC_IsEnabled(ADC1) |                                                    \

  1572.    LL_ADC_IsEnabled(ADC2) |                                                    \

  1573.    LL_ADC_IsEnabled(ADC3)  )

  1574. #elif defined(ADC1) && defined(ADC2)

  1575. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  1576.   (LL_ADC_IsEnabled(ADC1) |                                                    \

  1577.    LL_ADC_IsEnabled(ADC2)  )

  1578. #else

  1579. #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

  1580.   (LL_ADC_IsEnabled(ADC1))

  1581. #endif

  1582. 

  1583. /**

  1584.   * @brief  Helper macro to define the ADC conversion data full-scale digital

  1585.   *         value corresponding to the selected ADC resolution.

  1586.   * @note   ADC conversion data full-scale corresponds to voltage range

  1587.   *         determined by analog voltage references Vref+ and Vref-

  1588.   *         (refer to reference manual).

  1589.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1590.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1591.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1592.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1593.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1594.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  1595.   */

  1596. #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

  1597.   (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))

  1598. 

  1599. /**

  1600.   * @brief  Helper macro to convert the ADC conversion data from

  1601.   *         a resolution to another resolution.

  1602.   * @param  __DATA__ ADC conversion data to be converted

  1603.   * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted

  1604.   *         This parameter can be one of the following values:

  1605.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1606.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1607.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1608.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1609.   * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

  1610.   *         This parameter can be one of the following values:

  1611.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1612.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1613.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1614.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1615.   * @retval ADC conversion data to the requested resolution

  1616.   */

  1617. #define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \

  1618.   (((__DATA__)                                                                 \

  1619.     << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U)))     \

  1620.    >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1U))        \

  1621.   )

  1622. 

  1623. /**

  1624.   * @brief  Helper macro to calculate the voltage (unit: mVolt)

  1625.   *         corresponding to a ADC conversion data (unit: digital value).

  1626.   * @note   Analog reference voltage (Vref+) must be either known from

  1627.   *         user board environment or can be calculated using ADC measurement

  1628.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  1629.   * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

  1630.   * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)

  1631.   *                       (unit: digital value).

  1632.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1633.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1634.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1635.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1636.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1637.   * @retval ADC conversion data equivalent voltage value (unit: mVolt)

  1638.   */

  1639. #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

  1640.                                       __ADC_DATA__,\

  1641.                                       __ADC_RESOLUTION__)                      \

  1642.   ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \

  1643.    / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \

  1644.   )

  1645. 

  1646. /**

  1647.   * @brief  Helper macro to calculate analog reference voltage (Vref+)

  1648.   *         (unit: mVolt) from ADC conversion data of internal voltage

  1649.   *         reference VrefInt.

  1650.   * @note   Computation is using VrefInt calibration value

  1651.   *         stored in system memory for each device during production.

  1652.   * @note   This voltage depends on user board environment: voltage level

  1653.   *         connected to pin Vref+.

  1654.   *         On devices with small package, the pin Vref+ is not present

  1655.   *         and internally bonded to pin Vdda.

  1656.   * @note   On this STM32 serie, calibration data of internal voltage reference

  1657.   *         VrefInt corresponds to a resolution of 12 bits,

  1658.   *         this is the recommended ADC resolution to convert voltage of

  1659.   *         internal voltage reference VrefInt.

  1660.   *         Otherwise, this macro performs the processing to scale

  1661.   *         ADC conversion data to 12 bits.

  1662.   * @param  __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits)

  1663.   *         of internal voltage reference VrefInt (unit: digital value).

  1664.   * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

  1665.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1666.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1667.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1668.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1669.   * @retval Analog reference voltage (unit: mV)

  1670.   */

  1671. #define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

  1672.                                          __ADC_RESOLUTION__)                   \

  1673.   (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \

  1674.     / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                 \

  1675.                                        (__ADC_RESOLUTION__),                   \

  1676.                                        LL_ADC_RESOLUTION_12B)                  \

  1677.   )

  1678. 

  1679. /**

  1680.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  1681.   *         from ADC conversion data of internal temperature sensor.

  1682.   * @note   Computation is using temperature sensor calibration values

  1683.   *         stored in system memory for each device during production.

  1684.   * @note   Calculation formula:

  1685.   *           Temperature = ((TS_ADC_DATA - TS_CAL1)

  1686.   *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

  1687.   *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

  1688.   *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

  1689.   *                Avg_Slope = (TS_CAL2 - TS_CAL1)

  1690.   *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

  1691.   *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

  1692.   *                            TEMP_DEGC_CAL1 (calibrated in factory)

  1693.   *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

  1694.   *                            TEMP_DEGC_CAL2 (calibrated in factory)

  1695.   *         Caution: Calculation relevancy under reserve that calibration

  1696.   *                  parameters are correct (address and data).

  1697.   *                  To calculate temperature using temperature sensor

  1698.   *                  datasheet typical values (generic values less, therefore

  1699.   *                  less accurate than calibrated values),

  1700.   *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

  1701.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  1702.   *         defined as it impacts the ADC LSB equivalent voltage.

  1703.   * @note   Analog reference voltage (Vref+) must be either known from

  1704.   *         user board environment or can be calculated using ADC measurement

  1705.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  1706.   * @note   On this STM32 serie, calibration data of temperature sensor

  1707.   *         corresponds to a resolution of 12 bits,

  1708.   *         this is the recommended ADC resolution to convert voltage of

  1709.   *         temperature sensor.

  1710.   *         Otherwise, this macro performs the processing to scale

  1711.   *         ADC conversion data to 12 bits.

  1712.   * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

  1713.   * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

  1714.   *                                 temperature sensor (unit: digital value).

  1715.   * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

  1716.   *                                 sensor voltage has been measured.

  1717.   *         This parameter can be one of the following values:

  1718.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1719.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1720.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1721.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1722.   * @retval Temperature (unit: degree Celsius)

  1723.   */

  1724. #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

  1725.                                   __TEMPSENSOR_ADC_DATA__,\

  1726.                                   __ADC_RESOLUTION__)                              \

  1727.   (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \

  1728.                                                     (__ADC_RESOLUTION__),          \

  1729.                                                     LL_ADC_RESOLUTION_12B)         \

  1730.                    * (__VREFANALOG_VOLTAGE__))                                     \

  1731.                   / TEMPSENSOR_CAL_VREFANALOG)                                     \

  1732.         - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \

  1733.      ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \

  1734.     ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \

  1735.    ) + TEMPSENSOR_CAL1_TEMP                                                        \

  1736.   )

  1737. 

  1738. /**

  1739.   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

  1740.   *         from ADC conversion data of internal temperature sensor.

  1741.   * @note   Computation is using temperature sensor typical values

  1742.   *         (refer to device datasheet).

  1743.   * @note   Calculation formula:

  1744.   *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

  1745.   *                         / Avg_Slope + CALx_TEMP

  1746.   *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

  1747.   *                                   (unit: digital value)

  1748.   *                Avg_Slope        = temperature sensor slope

  1749.   *                                   (unit: uV/Degree Celsius)

  1750.   *                TS_TYP_CALx_VOLT = temperature sensor digital value at

  1751.   *                                   temperature CALx_TEMP (unit: mV)

  1752.   *         Caution: Calculation relevancy under reserve the temperature sensor

  1753.   *                  of the current device has characteristics in line with

  1754.   *                  datasheet typical values.

  1755.   *                  If temperature sensor calibration values are available on

  1756.   *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

  1757.   *                  temperature calculation will be more accurate using

  1758.   *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

  1759.   * @note   As calculation input, the analog reference voltage (Vref+) must be

  1760.   *         defined as it impacts the ADC LSB equivalent voltage.

  1761.   * @note   Analog reference voltage (Vref+) must be either known from

  1762.   *         user board environment or can be calculated using ADC measurement

  1763.   *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

  1764.   * @note   ADC measurement data must correspond to a resolution of 12bits

  1765.   *         (full scale digital value 4095). If not the case, the data must be

  1766.   *         preliminarily rescaled to an equivalent resolution of 12 bits.

  1767.   * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

  1768.   *                                       On STM32F7, refer to device datasheet parameter "Avg_Slope".

  1769.   * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

  1770.   *                                       On STM32F4, refer to device datasheet parameter "V25".

  1771.   * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

  1772.   * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

  1773.   * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

  1774.   * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

  1775.   *         This parameter can be one of the following values:

  1776.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1777.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1778.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1779.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1780.   * @retval Temperature (unit: degree Celsius)

  1781.   */

  1782. #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

  1783.                                              __TEMPSENSOR_TYP_CALX_V__,\

  1784.                                              __TEMPSENSOR_CALX_TEMP__,\

  1785.                                              __VREFANALOG_VOLTAGE__,\

  1786.                                              __TEMPSENSOR_ADC_DATA__,\

  1787.                                              __ADC_RESOLUTION__)               \

  1788.   ((( (                                                                        \

  1789.        (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \

  1790.                  * 1000)                                                       \

  1791.        -                                                                       \

  1792.        (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \

  1793.                   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \

  1794.                  * 1000)                                                       \

  1795.       )                                                                        \

  1796.     ) / (__TEMPSENSOR_TYP_AVGSLOPE__)                                          \

  1797.    ) + (__TEMPSENSOR_CALX_TEMP__)                                              \

  1798.   )

  1799. 

  1800. /**

  1801.   * @}

  1802.   */

  1803. 

  1804. /**

  1805.   * @}

  1806.   */

  1807. 

  1808. 

  1809. /* Exported functions --------------------------------------------------------*/

  1810. /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions

  1811.   * @{

  1812.   */

  1813. 

  1814. /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management

  1815.   * @{

  1816.   */

  1817. /* Note: LL ADC functions to set DMA transfer are located into sections of    */

  1818. /*       configuration of ADC instance, groups and multimode (if available):  */

  1819. /*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */

  1820. 

  1821. /**

  1822.   * @brief  Function to help to configure DMA transfer from ADC: retrieve the

  1823.   *         ADC register address from ADC instance and a list of ADC registers

  1824.   *         intended to be used (most commonly) with DMA transfer.

  1825.   * @note   These ADC registers are data registers:

  1826.   *         when ADC conversion data is available in ADC data registers,

  1827.   *         ADC generates a DMA transfer request.

  1828.   * @note   This macro is intended to be used with LL DMA driver, refer to

  1829.   *         function "LL_DMA_ConfigAddresses()".

  1830.   *         Example:

  1831.   *           LL_DMA_ConfigAddresses(DMA1,

  1832.   *                                  LL_DMA_CHANNEL_1,

  1833.   *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),

  1834.   *                                  (uint32_t)&< array or variable >,

  1835.   *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

  1836.   * @note   For devices with several ADC: in multimode, some devices

  1837.   *         use a different data register outside of ADC instance scope

  1838.   *         (common data register). This macro manages this register difference,

  1839.   *         only ADC instance has to be set as parameter.

  1840.   * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n

  1841.   *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n

  1842.   *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr

  1843.   * @param  ADCx ADC instance

  1844.   * @param  Register This parameter can be one of the following values:

  1845.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA

  1846.   *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)

  1847.   *

  1848.   *         (1) Available on devices with several ADC instances.

  1849.   * @retval ADC register address

  1850.   */

  1851. __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)

  1852. {

  1853.   register uint32_t data_reg_addr = 0U;

  1854. 

  1855.   if (Register == LL_ADC_DMA_REG_REGULAR_DATA)

  1856.   {

  1857.     /* Retrieve address of register DR */

  1858.     data_reg_addr = (uint32_t)&(ADCx->DR);

  1859.   }

  1860.   else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */

  1861.   {

  1862.     /* Retrieve address of register CDR */

  1863.     data_reg_addr = (uint32_t)&((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);

  1864.   }

  1865. 

  1866.   return data_reg_addr;

  1867. }

  1868. 

  1869. /**

  1870.   * @}

  1871.   */

  1872. 

  1873. /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances

  1874.   * @{

  1875.   */

  1876. 

  1877. /**

  1878.   * @brief  Set parameter common to several ADC: Clock source and prescaler.

  1879.   * @rmtoll CCR      ADCPRE         LL_ADC_SetCommonClock

  1880.   * @param  ADCxy_COMMON ADC common instance

  1881.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1882.   * @param  CommonClock This parameter can be one of the following values:

  1883.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  1884.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  1885.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6

  1886.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8

  1887.   * @retval None

  1888.   */

  1889. __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)

  1890. {

  1891.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);

  1892. }

  1893. 

  1894. /**

  1895.   * @brief  Get parameter common to several ADC: Clock source and prescaler.

  1896.   * @rmtoll CCR      ADCPRE         LL_ADC_GetCommonClock

  1897.   * @param  ADCxy_COMMON ADC common instance

  1898.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1899.   * @retval Returned value can be one of the following values:

  1900.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

  1901.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

  1902.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV6

  1903.   *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8

  1904.   */

  1905. __STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)

  1906. {

  1907.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));

  1908. }

  1909. 

  1910. /**

  1911.   * @brief  Set parameter common to several ADC: measurement path to internal

  1912.   *         channels (VrefInt, temperature sensor, ...).

  1913.   * @note   One or several values can be selected.

  1914.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  1915.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  1916.   * @note   Stabilization time of measurement path to internal channel:

  1917.   *         After enabling internal paths, before starting ADC conversion,

  1918.   *         a delay is required for internal voltage reference and

  1919.   *         temperature sensor stabilization time.

  1920.   *         Refer to device datasheet.

  1921.   *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

  1922.   *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

  1923.   * @note   ADC internal channel sampling time constraint:

  1924.   *         For ADC conversion of internal channels,

  1925.   *         a sampling time minimum value is required.

  1926.   *         Refer to device datasheet.

  1927.   * @rmtoll CCR      TSVREFE        LL_ADC_SetCommonPathInternalCh\n

  1928.   *         CCR      VBATE          LL_ADC_SetCommonPathInternalCh

  1929.   * @param  ADCxy_COMMON ADC common instance

  1930.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1931.   * @param  PathInternal This parameter can be a combination of the following values:

  1932.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  1933.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  1934.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  1935.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  1936.   * @retval None

  1937.   */

  1938. __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

  1939. {

  1940.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);

  1941. }

  1942. 

  1943. /**

  1944.   * @brief  Get parameter common to several ADC: measurement path to internal

  1945.   *         channels (VrefInt, temperature sensor, ...).

  1946.   * @note   One or several values can be selected.

  1947.   *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

  1948.   *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

  1949.   * @rmtoll CCR      TSVREFE        LL_ADC_GetCommonPathInternalCh\n

  1950.   *         CCR      VBATE          LL_ADC_GetCommonPathInternalCh

  1951.   * @param  ADCxy_COMMON ADC common instance

  1952.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  1953.   * @retval Returned value can be a combination of the following values:

  1954.   *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

  1955.   *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

  1956.   *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

  1957.   *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

  1958.   */

  1959. __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)

  1960. {

  1961.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));

  1962. }

  1963. 

  1964. /**

  1965.   * @}

  1966.   */

  1967. 

  1968. /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance

  1969.   * @{

  1970.   */

  1971. 

  1972. /**

  1973.   * @brief  Set ADC resolution.

  1974.   *         Refer to reference manual for alignments formats

  1975.   *         dependencies to ADC resolutions.

  1976.   * @rmtoll CR1      RES            LL_ADC_SetResolution

  1977.   * @param  ADCx ADC instance

  1978.   * @param  Resolution This parameter can be one of the following values:

  1979.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1980.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1981.   *         @arg @ref LL_ADC_RESOLUTION_8B

  1982.   *         @arg @ref LL_ADC_RESOLUTION_6B

  1983.   * @retval None

  1984.   */

  1985. __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)

  1986. {

  1987.   MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);

  1988. }

  1989. 

  1990. /**

  1991.   * @brief  Get ADC resolution.

  1992.   *         Refer to reference manual for alignments formats

  1993.   *         dependencies to ADC resolutions.

  1994.   * @rmtoll CR1      RES            LL_ADC_GetResolution

  1995.   * @param  ADCx ADC instance

  1996.   * @retval Returned value can be one of the following values:

  1997.   *         @arg @ref LL_ADC_RESOLUTION_12B

  1998.   *         @arg @ref LL_ADC_RESOLUTION_10B

  1999.   *         @arg @ref LL_ADC_RESOLUTION_8B

  2000.   *         @arg @ref LL_ADC_RESOLUTION_6B

  2001.   */

  2002. __STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)

  2003. {

  2004.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));

  2005. }

  2006. 

  2007. /**

  2008.   * @brief  Set ADC conversion data alignment.

  2009.   * @note   Refer to reference manual for alignments formats

  2010.   *         dependencies to ADC resolutions.

  2011.   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment

  2012.   * @param  ADCx ADC instance

  2013.   * @param  DataAlignment This parameter can be one of the following values:

  2014.   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT

  2015.   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT

  2016.   * @retval None

  2017.   */

  2018. __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)

  2019. {

  2020.   MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);

  2021. }

  2022. 

  2023. /**

  2024.   * @brief  Get ADC conversion data alignment.

  2025.   * @note   Refer to reference manual for alignments formats

  2026.   *         dependencies to ADC resolutions.

  2027.   * @rmtoll CR2      ALIGN          LL_ADC_SetDataAlignment

  2028.   * @param  ADCx ADC instance

  2029.   * @retval Returned value can be one of the following values:

  2030.   *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT

  2031.   *         @arg @ref LL_ADC_DATA_ALIGN_LEFT

  2032.   */

  2033. __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)

  2034. {

  2035.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));

  2036. }

  2037. 

  2038. /**

  2039.   * @brief  Set ADC sequencers scan mode, for all ADC groups

  2040.   *         (group regular, group injected).

  2041.   * @note  According to sequencers scan mode :

  2042.   *         - If disabled: ADC conversion is performed in unitary conversion

  2043.   *           mode (one channel converted, that defined in rank 1).

  2044.   *           Configuration of sequencers of all ADC groups

  2045.   *           (sequencer scan length, ...) is discarded: equivalent to

  2046.   *           scan length of 1 rank.

  2047.   *         - If enabled: ADC conversions are performed in sequence conversions

  2048.   *           mode, according to configuration of sequencers of

  2049.   *           each ADC group (sequencer scan length, ...).

  2050.   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()

  2051.   *           and to function @ref LL_ADC_INJ_SetSequencerLength().

  2052.   * @rmtoll CR1      SCAN           LL_ADC_SetSequencersScanMode

  2053.   * @param  ADCx ADC instance

  2054.   * @param  ScanMode This parameter can be one of the following values:

  2055.   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE

  2056.   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE

  2057.   * @retval None

  2058.   */

  2059. __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)

  2060. {

  2061.   MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);

  2062. }

  2063. 

  2064. /**

  2065.   * @brief  Get ADC sequencers scan mode, for all ADC groups

  2066.   *         (group regular, group injected).

  2067.   * @note  According to sequencers scan mode :

  2068.   *         - If disabled: ADC conversion is performed in unitary conversion

  2069.   *           mode (one channel converted, that defined in rank 1).

  2070.   *           Configuration of sequencers of all ADC groups

  2071.   *           (sequencer scan length, ...) is discarded: equivalent to

  2072.   *           scan length of 1 rank.

  2073.   *         - If enabled: ADC conversions are performed in sequence conversions

  2074.   *           mode, according to configuration of sequencers of

  2075.   *           each ADC group (sequencer scan length, ...).

  2076.   *           Refer to function @ref LL_ADC_REG_SetSequencerLength()

  2077.   *           and to function @ref LL_ADC_INJ_SetSequencerLength().

  2078.   * @rmtoll CR1      SCAN           LL_ADC_GetSequencersScanMode

  2079.   * @param  ADCx ADC instance

  2080.   * @retval Returned value can be one of the following values:

  2081.   *         @arg @ref LL_ADC_SEQ_SCAN_DISABLE

  2082.   *         @arg @ref LL_ADC_SEQ_SCAN_ENABLE

  2083.   */

  2084. __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)

  2085. {

  2086.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));

  2087. }

  2088. 

  2089. /**

  2090.   * @}

  2091.   */

  2092. 

  2093. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular

  2094.   * @{

  2095.   */

  2096. 

  2097. /**

  2098.   * @brief  Set ADC group regular conversion trigger source:

  2099.   *         internal (SW start) or from external IP (timer event,

  2100.   *         external interrupt line).

  2101.   * @note   On this STM32 serie, setting of external trigger edge is performed

  2102.   *         using function @ref LL_ADC_REG_StartConversionExtTrig().

  2103.   * @note   Availability of parameters of trigger sources from timer

  2104.   *         depends on timers availability on the selected device.

  2105.   * @rmtoll CR2      EXTSEL         LL_ADC_REG_SetTriggerSource\n

  2106.   *         CR2      EXTEN          LL_ADC_REG_SetTriggerSource

  2107.   * @param  ADCx ADC instance

  2108.   * @param  TriggerSource This parameter can be one of the following values:

  2109.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  2110.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

  2111.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

  2112.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

  2113.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  2114.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO

  2115.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  2116.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

  2117.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

  2118.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

  2119.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

  2120.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  2121.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  2122.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  2123.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  2124.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  2125.   * @retval None

  2126.   */

  2127. __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  2128. {

  2129. /* Note: On this STM32 serie, ADC group regular external trigger edge        */

  2130. /*       is used to perform a ADC conversion start.                           */

  2131. /*       This function does not set external trigger edge.                    */

  2132. /*       This feature is set using function                                   */

  2133. /*       @ref LL_ADC_REG_StartConversionExtTrig().                            */

  2134.   MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));

  2135. }

  2136. 

  2137. /**

  2138.   * @brief  Get ADC group regular conversion trigger source:

  2139.   *         internal (SW start) or from external IP (timer event,

  2140.   *         external interrupt line).

  2141.   * @note   To determine whether group regular trigger source is

  2142.   *         internal (SW start) or external, without detail

  2143.   *         of which peripheral is selected as external trigger,

  2144.   *         (equivalent to

  2145.   *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")

  2146.   *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.

  2147.   * @note   Availability of parameters of trigger sources from timer

  2148.   *         depends on timers availability on the selected device.

  2149.   * @rmtoll CR2      EXTSEL         LL_ADC_REG_GetTriggerSource\n

  2150.   *         CR2      EXTEN          LL_ADC_REG_GetTriggerSource

  2151.   * @param  ADCx ADC instance

  2152.   * @retval Returned value can be one of the following values:

  2153.   *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

  2154.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

  2155.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

  2156.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

  2157.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

  2158.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_TRGO

  2159.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

  2160.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

  2161.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

  2162.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

  2163.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

  2164.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

  2165.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

  2166.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

  2167.   *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

  2168.   *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

  2169.   */

  2170. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)

  2171. {

  2172.   register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);

  2173. 

  2174.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  2175.   /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}.                             */

  2176.   register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U));

  2177. 

  2178.   /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL           */

  2179.   /* to match with triggers literals definition.                              */

  2180.   return ((TriggerSource

  2181.            & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)

  2182.           | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)

  2183.          );

  2184. }

  2185. 

  2186. /**

  2187.   * @brief  Get ADC group regular conversion trigger source internal (SW start)

  2188.             or external.

  2189.   * @note   In case of group regular trigger source set to external trigger,

  2190.   *         to determine which peripheral is selected as external trigger,

  2191.   *         use function @ref LL_ADC_REG_GetTriggerSource().

  2192.   * @rmtoll CR2      EXTEN          LL_ADC_REG_IsTriggerSourceSWStart

  2193.   * @param  ADCx ADC instance

  2194.   * @retval Value "0" if trigger source external trigger

  2195.   *         Value "1" if trigger source SW start.

  2196.   */

  2197. __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  2198. {

  2199.   return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));

  2200. }

  2201. 

  2202. /**

  2203.   * @brief  Get ADC group regular conversion trigger polarity.

  2204.   * @note   Applicable only for trigger source set to external trigger.

  2205.   * @note   On this STM32 serie, setting of external trigger edge is performed

  2206.   *         using function @ref LL_ADC_REG_StartConversionExtTrig().

  2207.   * @rmtoll CR2      EXTEN          LL_ADC_REG_GetTriggerEdge

  2208.   * @param  ADCx ADC instance

  2209.   * @retval Returned value can be one of the following values:

  2210.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  2211.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  2212.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  2213.   */

  2214. __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)

  2215. {

  2216.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));

  2217. }

  2218. 

  2219. 

  2220. /**

  2221.   * @brief  Set ADC group regular sequencer length and scan direction.

  2222.   * @note   Description of ADC group regular sequencer features:

  2223.   *         - For devices with sequencer fully configurable

  2224.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  2225.   *           sequencer length and each rank affectation to a channel

  2226.   *           are configurable.

  2227.   *           This function performs configuration of:

  2228.   *           - Sequence length: Number of ranks in the scan sequence.

  2229.   *           - Sequence direction: Unless specified in parameters, sequencer

  2230.   *             scan direction is forward (from rank 1 to rank n).

  2231.   *           Sequencer ranks are selected using

  2232.   *           function "LL_ADC_REG_SetSequencerRanks()".

  2233.   *         - For devices with sequencer not fully configurable

  2234.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  2235.   *           sequencer length and each rank affectation to a channel

  2236.   *           are defined by channel number.

  2237.   *           This function performs configuration of:

  2238.   *           - Sequence length: Number of ranks in the scan sequence is

  2239.   *             defined by number of channels set in the sequence,

  2240.   *             rank of each channel is fixed by channel HW number.

  2241.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  2242.   *           - Sequence direction: Unless specified in parameters, sequencer

  2243.   *             scan direction is forward (from lowest channel number to

  2244.   *             highest channel number).

  2245.   *           Sequencer ranks are selected using

  2246.   *           function "LL_ADC_REG_SetSequencerChannels()".

  2247.   * @note   On this STM32 serie, group regular sequencer configuration

  2248.   *         is conditioned to ADC instance sequencer mode.

  2249.   *         If ADC instance sequencer mode is disabled, sequencers of

  2250.   *         all groups (group regular, group injected) can be configured

  2251.   *         but their execution is disabled (limited to rank 1).

  2252.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  2253.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  2254.   *         ADC conversion on only 1 channel.

  2255.   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

  2256.   * @param  ADCx ADC instance

  2257.   * @param  SequencerNbRanks This parameter can be one of the following values:

  2258.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  2259.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  2260.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  2261.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  2262.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  2263.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  2264.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  2265.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  2266.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  2267.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  2268.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  2269.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  2270.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  2271.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  2272.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  2273.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  2274.   * @retval None

  2275.   */

  2276. __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  2277. {

  2278.   MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);

  2279. }

  2280. 

  2281. /**

  2282.   * @brief  Get ADC group regular sequencer length and scan direction.

  2283.   * @note   Description of ADC group regular sequencer features:

  2284.   *         - For devices with sequencer fully configurable

  2285.   *           (function "LL_ADC_REG_SetSequencerRanks()" available):

  2286.   *           sequencer length and each rank affectation to a channel

  2287.   *           are configurable.

  2288.   *           This function retrieves:

  2289.   *           - Sequence length: Number of ranks in the scan sequence.

  2290.   *           - Sequence direction: Unless specified in parameters, sequencer

  2291.   *             scan direction is forward (from rank 1 to rank n).

  2292.   *           Sequencer ranks are selected using

  2293.   *           function "LL_ADC_REG_SetSequencerRanks()".

  2294.   *         - For devices with sequencer not fully configurable

  2295.   *           (function "LL_ADC_REG_SetSequencerChannels()" available):

  2296.   *           sequencer length and each rank affectation to a channel

  2297.   *           are defined by channel number.

  2298.   *           This function retrieves:

  2299.   *           - Sequence length: Number of ranks in the scan sequence is

  2300.   *             defined by number of channels set in the sequence,

  2301.   *             rank of each channel is fixed by channel HW number.

  2302.   *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

  2303.   *           - Sequence direction: Unless specified in parameters, sequencer

  2304.   *             scan direction is forward (from lowest channel number to

  2305.   *             highest channel number).

  2306.   *           Sequencer ranks are selected using

  2307.   *           function "LL_ADC_REG_SetSequencerChannels()".

  2308.   * @note   On this STM32 serie, group regular sequencer configuration

  2309.   *         is conditioned to ADC instance sequencer mode.

  2310.   *         If ADC instance sequencer mode is disabled, sequencers of

  2311.   *         all groups (group regular, group injected) can be configured

  2312.   *         but their execution is disabled (limited to rank 1).

  2313.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  2314.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  2315.   *         ADC conversion on only 1 channel.

  2316.   * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

  2317.   * @param  ADCx ADC instance

  2318.   * @retval Returned value can be one of the following values:

  2319.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

  2320.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

  2321.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

  2322.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

  2323.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

  2324.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

  2325.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

  2326.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

  2327.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

  2328.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

  2329.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

  2330.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

  2331.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

  2332.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

  2333.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

  2334.   *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

  2335.   */

  2336. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)

  2337. {

  2338.   return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));

  2339. }

  2340. 

  2341. /**

  2342.   * @brief  Set ADC group regular sequencer discontinuous mode:

  2343.   *         sequence subdivided and scan conversions interrupted every selected

  2344.   *         number of ranks.

  2345.   * @note   It is not possible to enable both ADC group regular

  2346.   *         continuous mode and sequencer discontinuous mode.

  2347.   * @note   It is not possible to enable both ADC auto-injected mode

  2348.   *         and ADC group regular sequencer discontinuous mode.

  2349.   * @rmtoll CR1      DISCEN         LL_ADC_REG_SetSequencerDiscont\n

  2350.   *         CR1      DISCNUM        LL_ADC_REG_SetSequencerDiscont

  2351.   * @param  ADCx ADC instance

  2352.   * @param  SeqDiscont This parameter can be one of the following values:

  2353.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  2354.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  2355.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  2356.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  2357.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  2358.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  2359.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  2360.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  2361.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  2362.   * @retval None

  2363.   */

  2364. __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  2365. {

  2366.   MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);

  2367. }

  2368. 

  2369. /**

  2370.   * @brief  Get ADC group regular sequencer discontinuous mode:

  2371.   *         sequence subdivided and scan conversions interrupted every selected

  2372.   *         number of ranks.

  2373.   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont\n

  2374.   *         CR1      DISCNUM        LL_ADC_REG_GetSequencerDiscont

  2375.   * @param  ADCx ADC instance

  2376.   * @retval Returned value can be one of the following values:

  2377.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

  2378.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

  2379.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

  2380.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

  2381.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

  2382.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

  2383.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

  2384.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

  2385.   *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

  2386.   */

  2387. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)

  2388. {

  2389.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));

  2390. }

  2391. 

  2392. /**

  2393.   * @brief  Set ADC group regular sequence: channel on the selected

  2394.   *         scan sequence rank.

  2395.   * @note   This function performs configuration of:

  2396.   *         - Channels ordering into each rank of scan sequence:

  2397.   *           whatever channel can be placed into whatever rank.

  2398.   * @note   On this STM32 serie, ADC group regular sequencer is

  2399.   *         fully configurable: sequencer length and each rank

  2400.   *         affectation to a channel are configurable.

  2401.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  2402.   * @note   Depending on devices and packages, some channels may not be available.

  2403.   *         Refer to device datasheet for channels availability.

  2404.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  2405.   *         TempSensor, ...), measurement paths to internal channels must be

  2406.   *         enabled separately.

  2407.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  2408.   * @rmtoll SQR3     SQ1            LL_ADC_REG_SetSequencerRanks\n

  2409.   *         SQR3     SQ2            LL_ADC_REG_SetSequencerRanks\n

  2410.   *         SQR3     SQ3            LL_ADC_REG_SetSequencerRanks\n

  2411.   *         SQR3     SQ4            LL_ADC_REG_SetSequencerRanks\n

  2412.   *         SQR3     SQ5            LL_ADC_REG_SetSequencerRanks\n

  2413.   *         SQR3     SQ6            LL_ADC_REG_SetSequencerRanks\n

  2414.   *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n

  2415.   *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n

  2416.   *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n

  2417.   *         SQR2     SQ10           LL_ADC_REG_SetSequencerRanks\n

  2418.   *         SQR2     SQ11           LL_ADC_REG_SetSequencerRanks\n

  2419.   *         SQR2     SQ12           LL_ADC_REG_SetSequencerRanks\n

  2420.   *         SQR1     SQ13           LL_ADC_REG_SetSequencerRanks\n

  2421.   *         SQR1     SQ14           LL_ADC_REG_SetSequencerRanks\n

  2422.   *         SQR1     SQ15           LL_ADC_REG_SetSequencerRanks\n

  2423.   *         SQR1     SQ16           LL_ADC_REG_SetSequencerRanks

  2424.   * @param  ADCx ADC instance

  2425.   * @param  Rank This parameter can be one of the following values:

  2426.   *         @arg @ref LL_ADC_REG_RANK_1

  2427.   *         @arg @ref LL_ADC_REG_RANK_2

  2428.   *         @arg @ref LL_ADC_REG_RANK_3

  2429.   *         @arg @ref LL_ADC_REG_RANK_4

  2430.   *         @arg @ref LL_ADC_REG_RANK_5

  2431.   *         @arg @ref LL_ADC_REG_RANK_6

  2432.   *         @arg @ref LL_ADC_REG_RANK_7

  2433.   *         @arg @ref LL_ADC_REG_RANK_8

  2434.   *         @arg @ref LL_ADC_REG_RANK_9

  2435.   *         @arg @ref LL_ADC_REG_RANK_10

  2436.   *         @arg @ref LL_ADC_REG_RANK_11

  2437.   *         @arg @ref LL_ADC_REG_RANK_12

  2438.   *         @arg @ref LL_ADC_REG_RANK_13

  2439.   *         @arg @ref LL_ADC_REG_RANK_14

  2440.   *         @arg @ref LL_ADC_REG_RANK_15

  2441.   *         @arg @ref LL_ADC_REG_RANK_16

  2442.   * @param  Channel This parameter can be one of the following values:

  2443.   *         @arg @ref LL_ADC_CHANNEL_0

  2444.   *         @arg @ref LL_ADC_CHANNEL_1

  2445.   *         @arg @ref LL_ADC_CHANNEL_2

  2446.   *         @arg @ref LL_ADC_CHANNEL_3

  2447.   *         @arg @ref LL_ADC_CHANNEL_4

  2448.   *         @arg @ref LL_ADC_CHANNEL_5

  2449.   *         @arg @ref LL_ADC_CHANNEL_6

  2450.   *         @arg @ref LL_ADC_CHANNEL_7

  2451.   *         @arg @ref LL_ADC_CHANNEL_8

  2452.   *         @arg @ref LL_ADC_CHANNEL_9

  2453.   *         @arg @ref LL_ADC_CHANNEL_10

  2454.   *         @arg @ref LL_ADC_CHANNEL_11

  2455.   *         @arg @ref LL_ADC_CHANNEL_12

  2456.   *         @arg @ref LL_ADC_CHANNEL_13

  2457.   *         @arg @ref LL_ADC_CHANNEL_14

  2458.   *         @arg @ref LL_ADC_CHANNEL_15

  2459.   *         @arg @ref LL_ADC_CHANNEL_16

  2460.   *         @arg @ref LL_ADC_CHANNEL_17

  2461.   *         @arg @ref LL_ADC_CHANNEL_18

  2462.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2463.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  2464.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2465.   *

  2466.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  2467.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  2468.   * @retval None

  2469.   */

  2470. __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  2471. {

  2472.   /* Set bits with content of parameter "Channel" with bits position          */

  2473.   /* in register and register position depending on parameter "Rank".         */

  2474.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  2475.   /* other bits reserved for other purpose.                                   */

  2476.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));

  2477. 

  2478.   MODIFY_REG(*preg,

  2479.              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

  2480.              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

  2481. }

  2482. 

  2483. /**

  2484.   * @brief  Get ADC group regular sequence: channel on the selected

  2485.   *         scan sequence rank.

  2486.   * @note   On this STM32 serie, ADC group regular sequencer is

  2487.   *         fully configurable: sequencer length and each rank

  2488.   *         affectation to a channel are configurable.

  2489.   *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

  2490.   * @note   Depending on devices and packages, some channels may not be available.

  2491.   *         Refer to device datasheet for channels availability.

  2492.   * @note   Usage of the returned channel number:

  2493.   *         - To reinject this channel into another function LL_ADC_xxx:

  2494.   *           the returned channel number is only partly formatted on definition

  2495.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  2496.   *           with parts of literals LL_ADC_CHANNEL_x or using

  2497.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2498.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  2499.   *           as parameter for another function.

  2500.   *         - To get the channel number in decimal format:

  2501.   *           process the returned value with the helper macro

  2502.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  2503.   * @rmtoll SQR3     SQ1            LL_ADC_REG_GetSequencerRanks\n

  2504.   *         SQR3     SQ2            LL_ADC_REG_GetSequencerRanks\n

  2505.   *         SQR3     SQ3            LL_ADC_REG_GetSequencerRanks\n

  2506.   *         SQR3     SQ4            LL_ADC_REG_GetSequencerRanks\n

  2507.   *         SQR3     SQ5            LL_ADC_REG_GetSequencerRanks\n

  2508.   *         SQR3     SQ6            LL_ADC_REG_GetSequencerRanks\n

  2509.   *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n

  2510.   *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n

  2511.   *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n

  2512.   *         SQR2     SQ10           LL_ADC_REG_GetSequencerRanks\n

  2513.   *         SQR2     SQ11           LL_ADC_REG_GetSequencerRanks\n

  2514.   *         SQR2     SQ12           LL_ADC_REG_GetSequencerRanks\n

  2515.   *         SQR1     SQ13           LL_ADC_REG_GetSequencerRanks\n

  2516.   *         SQR1     SQ14           LL_ADC_REG_GetSequencerRanks\n

  2517.   *         SQR1     SQ15           LL_ADC_REG_GetSequencerRanks\n

  2518.   *         SQR1     SQ16           LL_ADC_REG_GetSequencerRanks

  2519.   * @param  ADCx ADC instance

  2520.   * @param  Rank This parameter can be one of the following values:

  2521.   *         @arg @ref LL_ADC_REG_RANK_1

  2522.   *         @arg @ref LL_ADC_REG_RANK_2

  2523.   *         @arg @ref LL_ADC_REG_RANK_3

  2524.   *         @arg @ref LL_ADC_REG_RANK_4

  2525.   *         @arg @ref LL_ADC_REG_RANK_5

  2526.   *         @arg @ref LL_ADC_REG_RANK_6

  2527.   *         @arg @ref LL_ADC_REG_RANK_7

  2528.   *         @arg @ref LL_ADC_REG_RANK_8

  2529.   *         @arg @ref LL_ADC_REG_RANK_9

  2530.   *         @arg @ref LL_ADC_REG_RANK_10

  2531.   *         @arg @ref LL_ADC_REG_RANK_11

  2532.   *         @arg @ref LL_ADC_REG_RANK_12

  2533.   *         @arg @ref LL_ADC_REG_RANK_13

  2534.   *         @arg @ref LL_ADC_REG_RANK_14

  2535.   *         @arg @ref LL_ADC_REG_RANK_15

  2536.   *         @arg @ref LL_ADC_REG_RANK_16

  2537.   * @retval Returned value can be one of the following values:

  2538.   *         @arg @ref LL_ADC_CHANNEL_0

  2539.   *         @arg @ref LL_ADC_CHANNEL_1

  2540.   *         @arg @ref LL_ADC_CHANNEL_2

  2541.   *         @arg @ref LL_ADC_CHANNEL_3

  2542.   *         @arg @ref LL_ADC_CHANNEL_4

  2543.   *         @arg @ref LL_ADC_CHANNEL_5

  2544.   *         @arg @ref LL_ADC_CHANNEL_6

  2545.   *         @arg @ref LL_ADC_CHANNEL_7

  2546.   *         @arg @ref LL_ADC_CHANNEL_8

  2547.   *         @arg @ref LL_ADC_CHANNEL_9

  2548.   *         @arg @ref LL_ADC_CHANNEL_10

  2549.   *         @arg @ref LL_ADC_CHANNEL_11

  2550.   *         @arg @ref LL_ADC_CHANNEL_12

  2551.   *         @arg @ref LL_ADC_CHANNEL_13

  2552.   *         @arg @ref LL_ADC_CHANNEL_14

  2553.   *         @arg @ref LL_ADC_CHANNEL_15

  2554.   *         @arg @ref LL_ADC_CHANNEL_16

  2555.   *         @arg @ref LL_ADC_CHANNEL_17

  2556.   *         @arg @ref LL_ADC_CHANNEL_18

  2557.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2558.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  2559.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2560.   *

  2561.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  2562.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n

  2563.   *         (1) For ADC channel read back from ADC register,

  2564.   *             comparison with internal channel parameter to be done

  2565.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  2566.   */

  2567. __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  2568. {

  2569.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));

  2570. 

  2571.   return (uint32_t) (READ_BIT(*preg,

  2572.                               ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

  2573.                      >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)

  2574.                     );

  2575. }

  2576. 

  2577. /**

  2578.   * @brief  Set ADC continuous conversion mode on ADC group regular.

  2579.   * @note   Description of ADC continuous conversion mode:

  2580.   *         - single mode: one conversion per trigger

  2581.   *         - continuous mode: after the first trigger, following

  2582.   *           conversions launched successively automatically.

  2583.   * @note   It is not possible to enable both ADC group regular

  2584.   *         continuous mode and sequencer discontinuous mode.

  2585.   * @rmtoll CR2      CONT           LL_ADC_REG_SetContinuousMode

  2586.   * @param  ADCx ADC instance

  2587.   * @param  Continuous This parameter can be one of the following values:

  2588.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  2589.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  2590.   * @retval None

  2591.   */

  2592. __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)

  2593. {

  2594.   MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);

  2595. }

  2596. 

  2597. /**

  2598.   * @brief  Get ADC continuous conversion mode on ADC group regular.

  2599.   * @note   Description of ADC continuous conversion mode:

  2600.   *         - single mode: one conversion per trigger

  2601.   *         - continuous mode: after the first trigger, following

  2602.   *           conversions launched successively automatically.

  2603.   * @rmtoll CR2      CONT           LL_ADC_REG_GetContinuousMode

  2604.   * @param  ADCx ADC instance

  2605.   * @retval Returned value can be one of the following values:

  2606.   *         @arg @ref LL_ADC_REG_CONV_SINGLE

  2607.   *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

  2608.   */

  2609. __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)

  2610. {

  2611.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));

  2612. }

  2613. 

  2614. /**

  2615.   * @brief  Set ADC group regular conversion data transfer: no transfer or

  2616.   *         transfer by DMA, and DMA requests mode.

  2617.   * @note   If transfer by DMA selected, specifies the DMA requests

  2618.   *         mode:

  2619.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  2620.   *           when number of DMA data transfers (number of

  2621.   *           ADC conversions) is reached.

  2622.   *           This ADC mode is intended to be used with DMA mode non-circular.

  2623.   *         - Unlimited mode: DMA transfer requests are unlimited,

  2624.   *           whatever number of DMA data transfers (number of

  2625.   *           ADC conversions).

  2626.   *           This ADC mode is intended to be used with DMA mode circular.

  2627.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  2628.   *         mode non-circular:

  2629.   *         when DMA transfers size will be reached, DMA will stop transfers of

  2630.   *         ADC conversions data ADC will raise an overrun error

  2631.   *        (overrun flag and interruption if enabled).

  2632.   * @note   For devices with several ADC instances: ADC multimode DMA

  2633.   *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().

  2634.   * @note   To configure DMA source address (peripheral address),

  2635.   *         use function @ref LL_ADC_DMA_GetRegAddr().

  2636.   * @rmtoll CR2      DMA            LL_ADC_REG_SetDMATransfer\n

  2637.   *         CR2      DDS            LL_ADC_REG_SetDMATransfer

  2638.   * @param  ADCx ADC instance

  2639.   * @param  DMATransfer This parameter can be one of the following values:

  2640.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE

  2641.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  2642.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  2643.   * @retval None

  2644.   */

  2645. __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)

  2646. {

  2647.   MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);

  2648. }

  2649. 

  2650. /**

  2651.   * @brief  Get ADC group regular conversion data transfer: no transfer or

  2652.   *         transfer by DMA, and DMA requests mode.

  2653.   * @note   If transfer by DMA selected, specifies the DMA requests

  2654.   *         mode:

  2655.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  2656.   *           when number of DMA data transfers (number of

  2657.   *           ADC conversions) is reached.

  2658.   *           This ADC mode is intended to be used with DMA mode non-circular.

  2659.   *         - Unlimited mode: DMA transfer requests are unlimited,

  2660.   *           whatever number of DMA data transfers (number of

  2661.   *           ADC conversions).

  2662.   *           This ADC mode is intended to be used with DMA mode circular.

  2663.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  2664.   *         mode non-circular:

  2665.   *         when DMA transfers size will be reached, DMA will stop transfers of

  2666.   *         ADC conversions data ADC will raise an overrun error

  2667.   *         (overrun flag and interruption if enabled).

  2668.   * @note   For devices with several ADC instances: ADC multimode DMA

  2669.   *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().

  2670.   * @note   To configure DMA source address (peripheral address),

  2671.   *         use function @ref LL_ADC_DMA_GetRegAddr().

  2672.   * @rmtoll CR2      DMA            LL_ADC_REG_GetDMATransfer\n

  2673.   *         CR2      DDS            LL_ADC_REG_GetDMATransfer

  2674.   * @param  ADCx ADC instance

  2675.   * @retval Returned value can be one of the following values:

  2676.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE

  2677.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

  2678.   *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

  2679.   */

  2680. __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)

  2681. {

  2682.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));

  2683. }

  2684. 

  2685. /**

  2686.   * @brief  Specify which ADC flag between EOC (end of unitary conversion)

  2687.   *         or EOS (end of sequence conversions) is used to indicate

  2688.   *         the end of conversion.

  2689.   * @note   This feature is aimed to be set when using ADC with

  2690.   *         programming model by polling or interruption

  2691.   *         (programming model by DMA usually uses DMA interruptions

  2692.   *         to indicate end of conversion and data transfer).

  2693.   * @note   For ADC group injected, end of conversion (flag&IT) is raised

  2694.   *         only at the end of the sequence.

  2695.   * @rmtoll CR2      EOCS           LL_ADC_REG_SetFlagEndOfConversion

  2696.   * @param  ADCx ADC instance

  2697.   * @param  EocSelection This parameter can be one of the following values:

  2698.   *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV

  2699.   *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV

  2700.   * @retval None

  2701.   */

  2702. __STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)

  2703. {

  2704.   MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);

  2705. }

  2706. 

  2707. /**

  2708.   * @brief  Get which ADC flag between EOC (end of unitary conversion)

  2709.   *         or EOS (end of sequence conversions) is used to indicate

  2710.   *         the end of conversion.

  2711.   * @rmtoll CR2      EOCS           LL_ADC_REG_GetFlagEndOfConversion

  2712.   * @param  ADCx ADC instance

  2713.   * @retval Returned value can be one of the following values:

  2714.   *         @arg @ref LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV

  2715.   *         @arg @ref LL_ADC_REG_FLAG_EOC_UNITARY_CONV

  2716.   */

  2717. __STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(ADC_TypeDef *ADCx)

  2718. {

  2719.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));

  2720. }

  2721. 

  2722. /**

  2723.   * @}

  2724.   */

  2725. 

  2726. /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected

  2727.   * @{

  2728.   */

  2729. 

  2730. /**

  2731.   * @brief  Set ADC group injected conversion trigger source:

  2732.   *         internal (SW start) or from external IP (timer event,

  2733.   *         external interrupt line).

  2734.   * @note   On this STM32 serie, setting of external trigger edge is performed

  2735.   *         using function @ref LL_ADC_INJ_StartConversionExtTrig().

  2736.   * @note   Availability of parameters of trigger sources from timer

  2737.   *         depends on timers availability on the selected device.

  2738.   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_SetTriggerSource\n

  2739.   *         CR2      JEXTEN         LL_ADC_INJ_SetTriggerSource

  2740.   * @param  ADCx ADC instance

  2741.   * @param  TriggerSource This parameter can be one of the following values:

  2742.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  2743.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  2744.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  2745.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  2746.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  2747.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  2748.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  2749.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  2750.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  2751.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  2752.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  2753.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  2754.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO

  2755.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  2756.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  2757.   * @retval None

  2758.   */

  2759. __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

  2760. {

  2761. /* Note: On this STM32 serie, ADC group injected external trigger edge       */

  2762. /*       is used to perform a ADC conversion start.                           */

  2763. /*       This function does not set external trigger edge.                    */

  2764. /*       This feature is set using function                                   */

  2765. /*       @ref LL_ADC_INJ_StartConversionExtTrig().                            */

  2766.   MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));

  2767. }

  2768. 

  2769. /**

  2770.   * @brief  Get ADC group injected conversion trigger source:

  2771.   *         internal (SW start) or from external IP (timer event,

  2772.   *         external interrupt line).

  2773.   * @note   To determine whether group injected trigger source is

  2774.   *         internal (SW start) or external, without detail

  2775.   *         of which peripheral is selected as external trigger,

  2776.   *         (equivalent to

  2777.   *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")

  2778.   *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.

  2779.   * @note   Availability of parameters of trigger sources from timer

  2780.   *         depends on timers availability on the selected device.

  2781.   * @rmtoll CR2      JEXTSEL        LL_ADC_INJ_GetTriggerSource\n

  2782.   *         CR2      JEXTEN         LL_ADC_INJ_GetTriggerSource

  2783.   * @param  ADCx ADC instance

  2784.   * @retval Returned value can be one of the following values:

  2785.   *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

  2786.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

  2787.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

  2788.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

  2789.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

  2790.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

  2791.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

  2792.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

  2793.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

  2794.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

  2795.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

  2796.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

  2797.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO

  2798.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

  2799.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

  2800.   */

  2801. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)

  2802. {

  2803.   register uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);

  2804. 

  2805.   /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

  2806.   /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}.                            */

  2807.   register uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2U));

  2808. 

  2809.   /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL         */

  2810.   /* to match with triggers literals definition.                              */

  2811.   return ((TriggerSource

  2812.            & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)

  2813.           | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)

  2814.          );

  2815. }

  2816. 

  2817. /**

  2818.   * @brief  Get ADC group injected conversion trigger source internal (SW start)

  2819.             or external

  2820.   * @note   In case of group injected trigger source set to external trigger,

  2821.   *         to determine which peripheral is selected as external trigger,

  2822.   *         use function @ref LL_ADC_INJ_GetTriggerSource.

  2823.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart

  2824.   * @param  ADCx ADC instance

  2825.   * @retval Value "0" if trigger source external trigger

  2826.   *         Value "1" if trigger source SW start.

  2827.   */

  2828. __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

  2829. {

  2830.   return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));

  2831. }

  2832. 

  2833. /**

  2834.   * @brief  Get ADC group injected conversion trigger polarity.

  2835.   *         Applicable only for trigger source set to external trigger.

  2836.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_GetTriggerEdge

  2837.   * @param  ADCx ADC instance

  2838.   * @retval Returned value can be one of the following values:

  2839.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  2840.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  2841.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  2842.   */

  2843. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)

  2844. {

  2845.   return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));

  2846. }

  2847. 

  2848. /**

  2849.   * @brief  Set ADC group injected sequencer length and scan direction.

  2850.   * @note   This function performs configuration of:

  2851.   *         - Sequence length: Number of ranks in the scan sequence.

  2852.   *         - Sequence direction: Unless specified in parameters, sequencer

  2853.   *           scan direction is forward (from rank 1 to rank n).

  2854.   * @note   On this STM32 serie, group injected sequencer configuration

  2855.   *         is conditioned to ADC instance sequencer mode.

  2856.   *         If ADC instance sequencer mode is disabled, sequencers of

  2857.   *         all groups (group regular, group injected) can be configured

  2858.   *         but their execution is disabled (limited to rank 1).

  2859.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  2860.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  2861.   *         ADC conversion on only 1 channel.

  2862.   * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength

  2863.   * @param  ADCx ADC instance

  2864.   * @param  SequencerNbRanks This parameter can be one of the following values:

  2865.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  2866.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  2867.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  2868.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  2869.   * @retval None

  2870.   */

  2871. __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

  2872. {

  2873.   MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);

  2874. }

  2875. 

  2876. /**

  2877.   * @brief  Get ADC group injected sequencer length and scan direction.

  2878.   * @note   This function retrieves:

  2879.   *         - Sequence length: Number of ranks in the scan sequence.

  2880.   *         - Sequence direction: Unless specified in parameters, sequencer

  2881.   *           scan direction is forward (from rank 1 to rank n).

  2882.   * @note   On this STM32 serie, group injected sequencer configuration

  2883.   *         is conditioned to ADC instance sequencer mode.

  2884.   *         If ADC instance sequencer mode is disabled, sequencers of

  2885.   *         all groups (group regular, group injected) can be configured

  2886.   *         but their execution is disabled (limited to rank 1).

  2887.   *         Refer to function @ref LL_ADC_SetSequencersScanMode().

  2888.   * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

  2889.   *         ADC conversion on only 1 channel.

  2890.   * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength

  2891.   * @param  ADCx ADC instance

  2892.   * @retval Returned value can be one of the following values:

  2893.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

  2894.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

  2895.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

  2896.   *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

  2897.   */

  2898. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)

  2899. {

  2900.   return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));

  2901. }

  2902. 

  2903. /**

  2904.   * @brief  Set ADC group injected sequencer discontinuous mode:

  2905.   *         sequence subdivided and scan conversions interrupted every selected

  2906.   *         number of ranks.

  2907.   * @note   It is not possible to enable both ADC group injected

  2908.   *         auto-injected mode and sequencer discontinuous mode.

  2909.   * @rmtoll CR1      DISCEN         LL_ADC_INJ_SetSequencerDiscont

  2910.   * @param  ADCx ADC instance

  2911.   * @param  SeqDiscont This parameter can be one of the following values:

  2912.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  2913.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  2914.   * @retval None

  2915.   */

  2916. __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

  2917. {

  2918.   MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);

  2919. }

  2920. 

  2921. /**

  2922.   * @brief  Get ADC group injected sequencer discontinuous mode:

  2923.   *         sequence subdivided and scan conversions interrupted every selected

  2924.   *         number of ranks.

  2925.   * @rmtoll CR1      DISCEN         LL_ADC_REG_GetSequencerDiscont

  2926.   * @param  ADCx ADC instance

  2927.   * @retval Returned value can be one of the following values:

  2928.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

  2929.   *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

  2930.   */

  2931. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)

  2932. {

  2933.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));

  2934. }

  2935. 

  2936. /**

  2937.   * @brief  Set ADC group injected sequence: channel on the selected

  2938.   *         sequence rank.

  2939.   * @note   Depending on devices and packages, some channels may not be available.

  2940.   *         Refer to device datasheet for channels availability.

  2941.   * @note   On this STM32 serie, to measure internal channels (VrefInt,

  2942.   *         TempSensor, ...), measurement paths to internal channels must be

  2943.   *         enabled separately.

  2944.   *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

  2945.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  2946.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  2947.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  2948.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  2949.   * @param  ADCx ADC instance

  2950.   * @param  Rank This parameter can be one of the following values:

  2951.   *         @arg @ref LL_ADC_INJ_RANK_1

  2952.   *         @arg @ref LL_ADC_INJ_RANK_2

  2953.   *         @arg @ref LL_ADC_INJ_RANK_3

  2954.   *         @arg @ref LL_ADC_INJ_RANK_4

  2955.   * @param  Channel This parameter can be one of the following values:

  2956.   *         @arg @ref LL_ADC_CHANNEL_0

  2957.   *         @arg @ref LL_ADC_CHANNEL_1

  2958.   *         @arg @ref LL_ADC_CHANNEL_2

  2959.   *         @arg @ref LL_ADC_CHANNEL_3

  2960.   *         @arg @ref LL_ADC_CHANNEL_4

  2961.   *         @arg @ref LL_ADC_CHANNEL_5

  2962.   *         @arg @ref LL_ADC_CHANNEL_6

  2963.   *         @arg @ref LL_ADC_CHANNEL_7

  2964.   *         @arg @ref LL_ADC_CHANNEL_8

  2965.   *         @arg @ref LL_ADC_CHANNEL_9

  2966.   *         @arg @ref LL_ADC_CHANNEL_10

  2967.   *         @arg @ref LL_ADC_CHANNEL_11

  2968.   *         @arg @ref LL_ADC_CHANNEL_12

  2969.   *         @arg @ref LL_ADC_CHANNEL_13

  2970.   *         @arg @ref LL_ADC_CHANNEL_14

  2971.   *         @arg @ref LL_ADC_CHANNEL_15

  2972.   *         @arg @ref LL_ADC_CHANNEL_16

  2973.   *         @arg @ref LL_ADC_CHANNEL_17

  2974.   *         @arg @ref LL_ADC_CHANNEL_18

  2975.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  2976.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  2977.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  2978.   *

  2979.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  2980.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  2981.   * @retval None

  2982.   */

  2983. __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

  2984. {

  2985.   /* Set bits with content of parameter "Channel" with bits position          */

  2986.   /* in register depending on parameter "Rank".                               */

  2987.   /* Parameters "Rank" and "Channel" are used with masks because containing   */

  2988.   /* other bits reserved for other purpose.                                   */

  2989.   register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;

  2990. 

  2991.   MODIFY_REG(ADCx->JSQR,

  2992.              ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),

  2993.              (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));

  2994. }

  2995. 

  2996. /**

  2997.   * @brief  Get ADC group injected sequence: channel on the selected

  2998.   *         sequence rank.

  2999.   * @note   Depending on devices and packages, some channels may not be available.

  3000.   *         Refer to device datasheet for channels availability.

  3001.   * @note   Usage of the returned channel number:

  3002.   *         - To reinject this channel into another function LL_ADC_xxx:

  3003.   *           the returned channel number is only partly formatted on definition

  3004.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3005.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3006.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3007.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3008.   *           as parameter for another function.

  3009.   *         - To get the channel number in decimal format:

  3010.   *           process the returned value with the helper macro

  3011.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3012.   * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

  3013.   *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

  3014.   *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

  3015.   *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

  3016.   * @param  ADCx ADC instance

  3017.   * @param  Rank This parameter can be one of the following values:

  3018.   *         @arg @ref LL_ADC_INJ_RANK_1

  3019.   *         @arg @ref LL_ADC_INJ_RANK_2

  3020.   *         @arg @ref LL_ADC_INJ_RANK_3

  3021.   *         @arg @ref LL_ADC_INJ_RANK_4

  3022.   * @retval Returned value can be one of the following values:

  3023.   *         @arg @ref LL_ADC_CHANNEL_0

  3024.   *         @arg @ref LL_ADC_CHANNEL_1

  3025.   *         @arg @ref LL_ADC_CHANNEL_2

  3026.   *         @arg @ref LL_ADC_CHANNEL_3

  3027.   *         @arg @ref LL_ADC_CHANNEL_4

  3028.   *         @arg @ref LL_ADC_CHANNEL_5

  3029.   *         @arg @ref LL_ADC_CHANNEL_6

  3030.   *         @arg @ref LL_ADC_CHANNEL_7

  3031.   *         @arg @ref LL_ADC_CHANNEL_8

  3032.   *         @arg @ref LL_ADC_CHANNEL_9

  3033.   *         @arg @ref LL_ADC_CHANNEL_10

  3034.   *         @arg @ref LL_ADC_CHANNEL_11

  3035.   *         @arg @ref LL_ADC_CHANNEL_12

  3036.   *         @arg @ref LL_ADC_CHANNEL_13

  3037.   *         @arg @ref LL_ADC_CHANNEL_14

  3038.   *         @arg @ref LL_ADC_CHANNEL_15

  3039.   *         @arg @ref LL_ADC_CHANNEL_16

  3040.   *         @arg @ref LL_ADC_CHANNEL_17

  3041.   *         @arg @ref LL_ADC_CHANNEL_18

  3042.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3043.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  3044.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3045.   *

  3046.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  3047.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.\n

  3048.   *         (1) For ADC channel read back from ADC register,

  3049.   *             comparison with internal channel parameter to be done

  3050.   *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

  3051.   */

  3052. __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

  3053. {

  3054.   register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos)  + 1U;

  3055. 

  3056.   return (uint32_t)(READ_BIT(ADCx->JSQR,

  3057.                              ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))

  3058.                     >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))

  3059.                    );

  3060. }

  3061. 

  3062. /**

  3063.   * @brief  Set ADC group injected conversion trigger:

  3064.   *         independent or from ADC group regular.

  3065.   * @note   This mode can be used to extend number of data registers

  3066.   *         updated after one ADC conversion trigger and with data

  3067.   *         permanently kept (not erased by successive conversions of scan of

  3068.   *         ADC sequencer ranks), up to 5 data registers:

  3069.   *         1 data register on ADC group regular, 4 data registers

  3070.   *         on ADC group injected.

  3071.   * @note   If ADC group injected injected trigger source is set to an

  3072.   *         external trigger, this feature must be must be set to

  3073.   *         independent trigger.

  3074.   *         ADC group injected automatic trigger is compliant only with

  3075.   *         group injected trigger source set to SW start, without any

  3076.   *         further action on  ADC group injected conversion start or stop:

  3077.   *         in this case, ADC group injected is controlled only

  3078.   *         from ADC group regular.

  3079.   * @note   It is not possible to enable both ADC group injected

  3080.   *         auto-injected mode and sequencer discontinuous mode.

  3081.   * @rmtoll CR1      JAUTO          LL_ADC_INJ_SetTrigAuto

  3082.   * @param  ADCx ADC instance

  3083.   * @param  TrigAuto This parameter can be one of the following values:

  3084.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  3085.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  3086.   * @retval None

  3087.   */

  3088. __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)

  3089. {

  3090.   MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);

  3091. }

  3092. 

  3093. /**

  3094.   * @brief  Get ADC group injected conversion trigger:

  3095.   *         independent or from ADC group regular.

  3096.   * @rmtoll CR1      JAUTO          LL_ADC_INJ_GetTrigAuto

  3097.   * @param  ADCx ADC instance

  3098.   * @retval Returned value can be one of the following values:

  3099.   *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

  3100.   *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

  3101.   */

  3102. __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)

  3103. {

  3104.   return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));

  3105. }

  3106. 

  3107. /**

  3108.   * @brief  Set ADC group injected offset.

  3109.   * @note   It sets:

  3110.   *         - ADC group injected rank to which the offset programmed

  3111.   *           will be applied

  3112.   *         - Offset level (offset to be subtracted from the raw

  3113.   *           converted data).

  3114.   *         Caution: Offset format is dependent to ADC resolution:

  3115.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  3116.   *         are set to 0.

  3117.   * @note   Offset cannot be enabled or disabled.

  3118.   *         To emulate offset disabled, set an offset value equal to 0.

  3119.   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_SetOffset\n

  3120.   *         JOFR2    JOFFSET2       LL_ADC_INJ_SetOffset\n

  3121.   *         JOFR3    JOFFSET3       LL_ADC_INJ_SetOffset\n

  3122.   *         JOFR4    JOFFSET4       LL_ADC_INJ_SetOffset

  3123.   * @param  ADCx ADC instance

  3124.   * @param  Rank This parameter can be one of the following values:

  3125.   *         @arg @ref LL_ADC_INJ_RANK_1

  3126.   *         @arg @ref LL_ADC_INJ_RANK_2

  3127.   *         @arg @ref LL_ADC_INJ_RANK_3

  3128.   *         @arg @ref LL_ADC_INJ_RANK_4

  3129.   * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF

  3130.   * @retval None

  3131.   */

  3132. __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)

  3133. {

  3134.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));

  3135. 

  3136.   MODIFY_REG(*preg,

  3137.              ADC_JOFR1_JOFFSET1,

  3138.              OffsetLevel);

  3139. }

  3140. 

  3141. /**

  3142.   * @brief  Get ADC group injected offset.

  3143.   * @note   It gives offset level (offset to be subtracted from the raw converted data).

  3144.   *         Caution: Offset format is dependent to ADC resolution:

  3145.   *         offset has to be left-aligned on bit 11, the LSB (right bits)

  3146.   *         are set to 0.

  3147.   * @rmtoll JOFR1    JOFFSET1       LL_ADC_INJ_GetOffset\n

  3148.   *         JOFR2    JOFFSET2       LL_ADC_INJ_GetOffset\n

  3149.   *         JOFR3    JOFFSET3       LL_ADC_INJ_GetOffset\n

  3150.   *         JOFR4    JOFFSET4       LL_ADC_INJ_GetOffset

  3151.   * @param  ADCx ADC instance

  3152.   * @param  Rank This parameter can be one of the following values:

  3153.   *         @arg @ref LL_ADC_INJ_RANK_1

  3154.   *         @arg @ref LL_ADC_INJ_RANK_2

  3155.   *         @arg @ref LL_ADC_INJ_RANK_3

  3156.   *         @arg @ref LL_ADC_INJ_RANK_4

  3157.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  3158.   */

  3159. __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)

  3160. {

  3161.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));

  3162. 

  3163.   return (uint32_t)(READ_BIT(*preg,

  3164.                              ADC_JOFR1_JOFFSET1)

  3165.                    );

  3166. }

  3167. 

  3168. /**

  3169.   * @}

  3170.   */

  3171. 

  3172. /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels

  3173.   * @{

  3174.   */

  3175. 

  3176. /**

  3177.   * @brief  Set sampling time of the selected ADC channel

  3178.   *         Unit: ADC clock cycles.

  3179.   * @note   On this device, sampling time is on channel scope: independently

  3180.   *         of channel mapped on ADC group regular or injected.

  3181.   * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

  3182.   *         converted:

  3183.   *         sampling time constraints must be respected (sampling time can be

  3184.   *         adjusted in function of ADC clock frequency and sampling time

  3185.   *         setting).

  3186.   *         Refer to device datasheet for timings values (parameters TS_vrefint,

  3187.   *         TS_temp, ...).

  3188.   * @note   Conversion time is the addition of sampling time and processing time.

  3189.   *         Refer to reference manual for ADC processing time of

  3190.   *         this STM32 serie.

  3191.   * @note   In case of ADC conversion of internal channel (VrefInt,

  3192.   *         temperature sensor, ...), a sampling time minimum value

  3193.   *         is required.

  3194.   *         Refer to device datasheet.

  3195.   * @rmtoll SMPR1    SMP18          LL_ADC_SetChannelSamplingTime\n

  3196.   *         SMPR1    SMP17          LL_ADC_SetChannelSamplingTime\n

  3197.   *         SMPR1    SMP16          LL_ADC_SetChannelSamplingTime\n

  3198.   *         SMPR1    SMP15          LL_ADC_SetChannelSamplingTime\n

  3199.   *         SMPR1    SMP14          LL_ADC_SetChannelSamplingTime\n

  3200.   *         SMPR1    SMP13          LL_ADC_SetChannelSamplingTime\n

  3201.   *         SMPR1    SMP12          LL_ADC_SetChannelSamplingTime\n

  3202.   *         SMPR1    SMP11          LL_ADC_SetChannelSamplingTime\n

  3203.   *         SMPR1    SMP10          LL_ADC_SetChannelSamplingTime\n

  3204.   *         SMPR2    SMP9           LL_ADC_SetChannelSamplingTime\n

  3205.   *         SMPR2    SMP8           LL_ADC_SetChannelSamplingTime\n

  3206.   *         SMPR2    SMP7           LL_ADC_SetChannelSamplingTime\n

  3207.   *         SMPR2    SMP6           LL_ADC_SetChannelSamplingTime\n

  3208.   *         SMPR2    SMP5           LL_ADC_SetChannelSamplingTime\n

  3209.   *         SMPR2    SMP4           LL_ADC_SetChannelSamplingTime\n

  3210.   *         SMPR2    SMP3           LL_ADC_SetChannelSamplingTime\n

  3211.   *         SMPR2    SMP2           LL_ADC_SetChannelSamplingTime\n

  3212.   *         SMPR2    SMP1           LL_ADC_SetChannelSamplingTime\n

  3213.   *         SMPR2    SMP0           LL_ADC_SetChannelSamplingTime

  3214.   * @param  ADCx ADC instance

  3215.   * @param  Channel This parameter can be one of the following values:

  3216.   *         @arg @ref LL_ADC_CHANNEL_0

  3217.   *         @arg @ref LL_ADC_CHANNEL_1

  3218.   *         @arg @ref LL_ADC_CHANNEL_2

  3219.   *         @arg @ref LL_ADC_CHANNEL_3

  3220.   *         @arg @ref LL_ADC_CHANNEL_4

  3221.   *         @arg @ref LL_ADC_CHANNEL_5

  3222.   *         @arg @ref LL_ADC_CHANNEL_6

  3223.   *         @arg @ref LL_ADC_CHANNEL_7

  3224.   *         @arg @ref LL_ADC_CHANNEL_8

  3225.   *         @arg @ref LL_ADC_CHANNEL_9

  3226.   *         @arg @ref LL_ADC_CHANNEL_10

  3227.   *         @arg @ref LL_ADC_CHANNEL_11

  3228.   *         @arg @ref LL_ADC_CHANNEL_12

  3229.   *         @arg @ref LL_ADC_CHANNEL_13

  3230.   *         @arg @ref LL_ADC_CHANNEL_14

  3231.   *         @arg @ref LL_ADC_CHANNEL_15

  3232.   *         @arg @ref LL_ADC_CHANNEL_16

  3233.   *         @arg @ref LL_ADC_CHANNEL_17

  3234.   *         @arg @ref LL_ADC_CHANNEL_18

  3235.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3236.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  3237.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3238.   *

  3239.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  3240.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  3241.   * @param  SamplingTime This parameter can be one of the following values:

  3242.   *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES

  3243.   *         @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES

  3244.   *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES

  3245.   *         @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES

  3246.   *         @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES

  3247.   *         @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES

  3248.   *         @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES

  3249.   *         @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES

  3250.   * @retval None

  3251.   */

  3252. __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)

  3253. {

  3254.   /* Set bits with content of parameter "SamplingTime" with bits position     */

  3255.   /* in register and register position depending on parameter "Channel".      */

  3256.   /* Parameter "Channel" is used with masks because containing                */

  3257.   /* other bits reserved for other purpose.                                   */

  3258.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));

  3259. 

  3260.   MODIFY_REG(*preg,

  3261.              ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),

  3262.              SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));

  3263. }

  3264. 

  3265. /**

  3266.   * @brief  Get sampling time of the selected ADC channel

  3267.   *         Unit: ADC clock cycles.

  3268.   * @note   On this device, sampling time is on channel scope: independently

  3269.   *         of channel mapped on ADC group regular or injected.

  3270.   * @note   Conversion time is the addition of sampling time and processing time.

  3271.   *         Refer to reference manual for ADC processing time of

  3272.   *         this STM32 serie.

  3273.   * @rmtoll SMPR1    SMP18          LL_ADC_GetChannelSamplingTime\n

  3274.   *         SMPR1    SMP17          LL_ADC_GetChannelSamplingTime\n

  3275.   *         SMPR1    SMP16          LL_ADC_GetChannelSamplingTime\n

  3276.   *         SMPR1    SMP15          LL_ADC_GetChannelSamplingTime\n

  3277.   *         SMPR1    SMP14          LL_ADC_GetChannelSamplingTime\n

  3278.   *         SMPR1    SMP13          LL_ADC_GetChannelSamplingTime\n

  3279.   *         SMPR1    SMP12          LL_ADC_GetChannelSamplingTime\n

  3280.   *         SMPR1    SMP11          LL_ADC_GetChannelSamplingTime\n

  3281.   *         SMPR1    SMP10          LL_ADC_GetChannelSamplingTime\n

  3282.   *         SMPR2    SMP9           LL_ADC_GetChannelSamplingTime\n

  3283.   *         SMPR2    SMP8           LL_ADC_GetChannelSamplingTime\n

  3284.   *         SMPR2    SMP7           LL_ADC_GetChannelSamplingTime\n

  3285.   *         SMPR2    SMP6           LL_ADC_GetChannelSamplingTime\n

  3286.   *         SMPR2    SMP5           LL_ADC_GetChannelSamplingTime\n

  3287.   *         SMPR2    SMP4           LL_ADC_GetChannelSamplingTime\n

  3288.   *         SMPR2    SMP3           LL_ADC_GetChannelSamplingTime\n

  3289.   *         SMPR2    SMP2           LL_ADC_GetChannelSamplingTime\n

  3290.   *         SMPR2    SMP1           LL_ADC_GetChannelSamplingTime\n

  3291.   *         SMPR2    SMP0           LL_ADC_GetChannelSamplingTime

  3292.   * @param  ADCx ADC instance

  3293.   * @param  Channel This parameter can be one of the following values:

  3294.   *         @arg @ref LL_ADC_CHANNEL_0

  3295.   *         @arg @ref LL_ADC_CHANNEL_1

  3296.   *         @arg @ref LL_ADC_CHANNEL_2

  3297.   *         @arg @ref LL_ADC_CHANNEL_3

  3298.   *         @arg @ref LL_ADC_CHANNEL_4

  3299.   *         @arg @ref LL_ADC_CHANNEL_5

  3300.   *         @arg @ref LL_ADC_CHANNEL_6

  3301.   *         @arg @ref LL_ADC_CHANNEL_7

  3302.   *         @arg @ref LL_ADC_CHANNEL_8

  3303.   *         @arg @ref LL_ADC_CHANNEL_9

  3304.   *         @arg @ref LL_ADC_CHANNEL_10

  3305.   *         @arg @ref LL_ADC_CHANNEL_11

  3306.   *         @arg @ref LL_ADC_CHANNEL_12

  3307.   *         @arg @ref LL_ADC_CHANNEL_13

  3308.   *         @arg @ref LL_ADC_CHANNEL_14

  3309.   *         @arg @ref LL_ADC_CHANNEL_15

  3310.   *         @arg @ref LL_ADC_CHANNEL_16

  3311.   *         @arg @ref LL_ADC_CHANNEL_17

  3312.   *         @arg @ref LL_ADC_CHANNEL_18

  3313.   *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

  3314.   *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)(2)

  3315.   *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

  3316.   *

  3317.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  3318.   *         (2) On devices STM32F75x, STM32F74x, STM32F76x, STM32F77x, STM32F72x and STM32F73x: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  3319.   * @retval Returned value can be one of the following values:

  3320.   *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES

  3321.   *         @arg @ref LL_ADC_SAMPLINGTIME_15CYCLES

  3322.   *         @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES

  3323.   *         @arg @ref LL_ADC_SAMPLINGTIME_56CYCLES

  3324.   *         @arg @ref LL_ADC_SAMPLINGTIME_84CYCLES

  3325.   *         @arg @ref LL_ADC_SAMPLINGTIME_112CYCLES

  3326.   *         @arg @ref LL_ADC_SAMPLINGTIME_144CYCLES

  3327.   *         @arg @ref LL_ADC_SAMPLINGTIME_480CYCLES

  3328.   */

  3329. __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

  3330. {

  3331.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));

  3332. 

  3333.   return (uint32_t)(READ_BIT(*preg,

  3334.                              ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))

  3335.                     >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)

  3336.                    );

  3337. }

  3338. 

  3339. /**

  3340.   * @}

  3341.   */

  3342. 

  3343. /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog

  3344.   * @{

  3345.   */

  3346. 

  3347. /**

  3348.   * @brief  Set ADC analog watchdog monitored channels:

  3349.   *         a single channel or all channels,

  3350.   *         on ADC groups regular and-or injected.

  3351.   * @note   Once monitored channels are selected, analog watchdog

  3352.   *         is enabled.

  3353.   * @note   In case of need to define a single channel to monitor

  3354.   *         with analog watchdog from sequencer channel definition,

  3355.   *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().

  3356.   * @note   On this STM32 serie, there is only 1 kind of analog watchdog

  3357.   *         instance:

  3358.   *         - AWD standard (instance AWD1):

  3359.   *           - channels monitored: can monitor 1 channel or all channels.

  3360.   *           - groups monitored: ADC groups regular and-or injected.

  3361.   *           - resolution: resolution is not limited (corresponds to

  3362.   *             ADC resolution configured).

  3363.   * @rmtoll CR1      AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n

  3364.   *         CR1      AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n

  3365.   *         CR1      AWD1EN         LL_ADC_SetAnalogWDMonitChannels

  3366.   * @param  ADCx ADC instance

  3367.   * @param  AWDChannelGroup This parameter can be one of the following values:

  3368.   *         @arg @ref LL_ADC_AWD_DISABLE

  3369.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG

  3370.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ

  3371.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  3372.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG

  3373.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ

  3374.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  3375.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG

  3376.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ

  3377.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  3378.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG

  3379.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ

  3380.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  3381.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG

  3382.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ

  3383.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  3384.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG

  3385.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ

  3386.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  3387.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG

  3388.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ

  3389.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  3390.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG

  3391.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ

  3392.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  3393.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG

  3394.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ

  3395.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  3396.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG

  3397.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ

  3398.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  3399.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG

  3400.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ

  3401.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  3402.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG

  3403.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ

  3404.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  3405.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG

  3406.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ

  3407.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  3408.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG

  3409.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ

  3410.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  3411.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG

  3412.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ

  3413.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  3414.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG

  3415.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ

  3416.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  3417.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG

  3418.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ

  3419.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  3420.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG

  3421.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ

  3422.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  3423.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG

  3424.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ

  3425.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  3426.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG

  3427.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ

  3428.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  3429.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (1)

  3430.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (1)

  3431.   *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ      (1)

  3432.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (1)(2)

  3433.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (1)(2)

  3434.   *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   (1)(2)

  3435.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (1)

  3436.   *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (1)

  3437.   *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ         (1)

  3438.   *

  3439.   *         (1) On STM32F7, parameter available only on ADC instance: ADC1.\n

  3440.   *         (2) On devices STM32F7xx,a limitation: this internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled.

  3441.   * @retval None

  3442.   */

  3443. __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)

  3444. {

  3445.   MODIFY_REG(ADCx->CR1,

  3446.              (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),

  3447.              AWDChannelGroup);

  3448. }

  3449. 

  3450. /**

  3451.   * @brief  Get ADC analog watchdog monitored channel.

  3452.   * @note   Usage of the returned channel number:

  3453.   *         - To reinject this channel into another function LL_ADC_xxx:

  3454.   *           the returned channel number is only partly formatted on definition

  3455.   *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

  3456.   *           with parts of literals LL_ADC_CHANNEL_x or using

  3457.   *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3458.   *           Then the selected literal LL_ADC_CHANNEL_x can be used

  3459.   *           as parameter for another function.

  3460.   *         - To get the channel number in decimal format:

  3461.   *           process the returned value with the helper macro

  3462.   *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

  3463.   *           Applicable only when the analog watchdog is set to monitor

  3464.   *           one channel.

  3465.   * @note   On this STM32 serie, there is only 1 kind of analog watchdog

  3466.   *         instance:

  3467.   *         - AWD standard (instance AWD1):

  3468.   *           - channels monitored: can monitor 1 channel or all channels.

  3469.   *           - groups monitored: ADC groups regular and-or injected.

  3470.   *           - resolution: resolution is not limited (corresponds to

  3471.   *             ADC resolution configured).

  3472.   * @rmtoll CR1      AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n

  3473.   *         CR1      AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n

  3474.   *         CR1      AWD1EN         LL_ADC_GetAnalogWDMonitChannels

  3475.   * @param  ADCx ADC instance

  3476.   * @retval Returned value can be one of the following values:

  3477.   *         @arg @ref LL_ADC_AWD_DISABLE

  3478.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG

  3479.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ

  3480.   *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

  3481.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG

  3482.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ

  3483.   *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

  3484.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG

  3485.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ

  3486.   *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

  3487.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG

  3488.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ

  3489.   *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

  3490.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG

  3491.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ

  3492.   *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

  3493.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG

  3494.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ

  3495.   *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

  3496.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG

  3497.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ

  3498.   *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

  3499.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG

  3500.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ

  3501.   *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

  3502.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG

  3503.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ

  3504.   *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

  3505.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG

  3506.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ

  3507.   *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

  3508.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG

  3509.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ

  3510.   *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

  3511.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG

  3512.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ

  3513.   *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

  3514.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG

  3515.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ

  3516.   *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

  3517.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG

  3518.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ

  3519.   *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

  3520.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG

  3521.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ

  3522.   *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

  3523.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG

  3524.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ

  3525.   *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

  3526.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG

  3527.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ

  3528.   *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

  3529.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG

  3530.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ

  3531.   *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

  3532.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG

  3533.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ

  3534.   *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

  3535.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG

  3536.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ

  3537.   *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

  3538.   */

  3539. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)

  3540. {

  3541.   return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));

  3542. }

  3543. 

  3544. /**

  3545.   * @brief  Set ADC analog watchdog threshold value of threshold

  3546.   *         high or low.

  3547.   * @note   In case of ADC resolution different of 12 bits,

  3548.   *         analog watchdog thresholds data require a specific shift.

  3549.   *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

  3550.   * @note   On this STM32 serie, there is only 1 kind of analog watchdog

  3551.   *         instance:

  3552.   *         - AWD standard (instance AWD1):

  3553.   *           - channels monitored: can monitor 1 channel or all channels.

  3554.   *           - groups monitored: ADC groups regular and-or injected.

  3555.   *           - resolution: resolution is not limited (corresponds to

  3556.   *             ADC resolution configured).

  3557.   * @rmtoll HTR      HT             LL_ADC_SetAnalogWDThresholds\n

  3558.   *         LTR      LT             LL_ADC_SetAnalogWDThresholds

  3559.   * @param  ADCx ADC instance

  3560.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  3561.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  3562.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  3563.   * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF

  3564.   * @retval None

  3565.   */

  3566. __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)

  3567. {

  3568.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);

  3569. 

  3570.   MODIFY_REG(*preg,

  3571.              ADC_HTR_HT,

  3572.              AWDThresholdValue);

  3573. }

  3574. 

  3575. /**

  3576.   * @brief  Get ADC analog watchdog threshold value of threshold high or

  3577.   *         threshold low.

  3578.   * @note   In case of ADC resolution different of 12 bits,

  3579.   *         analog watchdog thresholds data require a specific shift.

  3580.   *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().

  3581.   * @rmtoll HTR      HT             LL_ADC_GetAnalogWDThresholds\n

  3582.   *         LTR      LT             LL_ADC_GetAnalogWDThresholds

  3583.   * @param  ADCx ADC instance

  3584.   * @param  AWDThresholdsHighLow This parameter can be one of the following values:

  3585.   *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

  3586.   *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

  3587.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  3588. */

  3589. __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)

  3590. {

  3591.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);

  3592. 

  3593.   return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));

  3594. }

  3595. 

  3596. /**

  3597.   * @}

  3598.   */

  3599. 

  3600. /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode

  3601.   * @{

  3602.   */

  3603. 

  3604. /**

  3605.   * @brief  Set ADC multimode configuration to operate in independent mode

  3606.   *         or multimode (for devices with several ADC instances).

  3607.   * @note   If multimode configuration: the selected ADC instance is

  3608.   *         either master or slave depending on hardware.

  3609.   *         Refer to reference manual.

  3610.   * @rmtoll CCR      MULTI          LL_ADC_SetMultimode

  3611.   * @param  ADCxy_COMMON ADC common instance

  3612.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  3613.   * @param  Multimode This parameter can be one of the following values:

  3614.   *         @arg @ref LL_ADC_MULTI_INDEPENDENT

  3615.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

  3616.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

  3617.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

  3618.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

  3619.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

  3620.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

  3621.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

  3622.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM

  3623.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT

  3624.   *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT

  3625.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT

  3626.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL

  3627.   *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN

  3628.   * @retval None

  3629.   */

  3630. __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)

  3631. {

  3632.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);

  3633. }

  3634. 

  3635. /**

  3636.   * @brief  Get ADC multimode configuration to operate in independent mode

  3637.   *         or multimode (for devices with several ADC instances).

  3638.   * @note   If multimode configuration: the selected ADC instance is

  3639.   *         either master or slave depending on hardware.

  3640.   *         Refer to reference manual.

  3641.   * @rmtoll CCR      MULTI          LL_ADC_GetMultimode

  3642.   * @param  ADCxy_COMMON ADC common instance

  3643.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  3644.   * @retval Returned value can be one of the following values:

  3645.   *         @arg @ref LL_ADC_MULTI_INDEPENDENT

  3646.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

  3647.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

  3648.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

  3649.   *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

  3650.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

  3651.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

  3652.   *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

  3653.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM

  3654.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT

  3655.   *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_SIMULT

  3656.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_SIMULT

  3657.   *         @arg @ref LL_ADC_MULTI_TRIPLE_REG_INTERL

  3658.   *         @arg @ref LL_ADC_MULTI_TRIPLE_INJ_ALTERN

  3659.   */

  3660. __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)

  3661. {

  3662.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));

  3663. }

  3664. 

  3665. /**

  3666.   * @brief  Set ADC multimode conversion data transfer: no transfer

  3667.   *         or transfer by DMA.

  3668.   * @note   If ADC multimode transfer by DMA is not selected:

  3669.   *         each ADC uses its own DMA channel, with its individual

  3670.   *         DMA transfer settings.

  3671.   *         If ADC multimode transfer by DMA is selected:

  3672.   *         One DMA channel is used for both ADC (DMA of ADC master)

  3673.   *         Specifies the DMA requests mode:

  3674.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  3675.   *           when number of DMA data transfers (number of

  3676.   *           ADC conversions) is reached.

  3677.   *           This ADC mode is intended to be used with DMA mode non-circular.

  3678.   *         - Unlimited mode: DMA transfer requests are unlimited,

  3679.   *           whatever number of DMA data transfers (number of

  3680.   *           ADC conversions).

  3681.   *           This ADC mode is intended to be used with DMA mode circular.

  3682.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  3683.   *         mode non-circular:

  3684.   *         when DMA transfers size will be reached, DMA will stop transfers of

  3685.   *         ADC conversions data ADC will raise an overrun error

  3686.   *         (overrun flag and interruption if enabled).

  3687.   * @note   How to retrieve multimode conversion data:

  3688.   *         Whatever multimode transfer by DMA setting: using function

  3689.   *         @ref LL_ADC_REG_ReadMultiConversionData32().

  3690.   *         If ADC multimode transfer by DMA is selected: conversion data

  3691.   *         is a raw data with ADC master and slave concatenated.

  3692.   *         A macro is available to get the conversion data of

  3693.   *         ADC master or ADC slave: see helper macro

  3694.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  3695.   * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n

  3696.   *         CCR      DDS            LL_ADC_SetMultiDMATransfer

  3697.   * @param  ADCxy_COMMON ADC common instance

  3698.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  3699.   * @param  MultiDMATransfer This parameter can be one of the following values:

  3700.   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

  3701.   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1

  3702.   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2

  3703.   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3

  3704.   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1

  3705.   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2

  3706.   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3

  3707.   * @retval None

  3708.   */

  3709. __STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)

  3710. {

  3711.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);

  3712. }

  3713. 

  3714. /**

  3715.   * @brief  Get ADC multimode conversion data transfer: no transfer

  3716.   *         or transfer by DMA.

  3717.   * @note   If ADC multimode transfer by DMA is not selected:

  3718.   *         each ADC uses its own DMA channel, with its individual

  3719.   *         DMA transfer settings.

  3720.   *         If ADC multimode transfer by DMA is selected:

  3721.   *         One DMA channel is used for both ADC (DMA of ADC master)

  3722.   *         Specifies the DMA requests mode:

  3723.   *         - Limited mode (One shot mode): DMA transfer requests are stopped

  3724.   *           when number of DMA data transfers (number of

  3725.   *           ADC conversions) is reached.

  3726.   *           This ADC mode is intended to be used with DMA mode non-circular.

  3727.   *         - Unlimited mode: DMA transfer requests are unlimited,

  3728.   *           whatever number of DMA data transfers (number of

  3729.   *           ADC conversions).

  3730.   *           This ADC mode is intended to be used with DMA mode circular.

  3731.   * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

  3732.   *         mode non-circular:

  3733.   *         when DMA transfers size will be reached, DMA will stop transfers of

  3734.   *         ADC conversions data ADC will raise an overrun error

  3735.   *         (overrun flag and interruption if enabled).

  3736.   * @note   How to retrieve multimode conversion data:

  3737.   *         Whatever multimode transfer by DMA setting: using function

  3738.   *         @ref LL_ADC_REG_ReadMultiConversionData32().

  3739.   *         If ADC multimode transfer by DMA is selected: conversion data

  3740.   *         is a raw data with ADC master and slave concatenated.

  3741.   *         A macro is available to get the conversion data of

  3742.   *         ADC master or ADC slave: see helper macro

  3743.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  3744.   * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n

  3745.   *         CCR      DDS            LL_ADC_GetMultiDMATransfer

  3746.   * @param  ADCxy_COMMON ADC common instance

  3747.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  3748.   * @retval Returned value can be one of the following values:

  3749.   *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

  3750.   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_1

  3751.   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_2

  3752.   *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_3

  3753.   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_1

  3754.   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_2

  3755.   *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_3

  3756.   */

  3757. __STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)

  3758. {

  3759.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));

  3760. }

  3761. 

  3762. /**

  3763.   * @brief  Set ADC multimode delay between 2 sampling phases.

  3764.   * @note   The sampling delay range depends on ADC resolution:

  3765.   *         - ADC resolution 12 bits can have maximum delay of 12 cycles.

  3766.   *         - ADC resolution 10 bits can have maximum delay of 10 cycles.

  3767.   *         - ADC resolution  8 bits can have maximum delay of  8 cycles.

  3768.   *         - ADC resolution  6 bits can have maximum delay of  6 cycles.

  3769.   * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay

  3770.   * @param  ADCxy_COMMON ADC common instance

  3771.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  3772.   * @param  MultiTwoSamplingDelay This parameter can be one of the following values:

  3773.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES

  3774.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES

  3775.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES

  3776.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES

  3777.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES

  3778.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES

  3779.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES

  3780.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES

  3781.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES

  3782.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES

  3783.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES

  3784.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES

  3785.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES

  3786.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES

  3787.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES

  3788.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES

  3789.   * @retval None

  3790.   */

  3791. __STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)

  3792. {

  3793.   MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);

  3794. }

  3795. 

  3796. /**

  3797.   * @brief  Get ADC multimode delay between 2 sampling phases.

  3798.   * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay

  3799.   * @param  ADCxy_COMMON ADC common instance

  3800.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  3801.   * @retval Returned value can be one of the following values:

  3802.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES

  3803.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES

  3804.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES

  3805.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES

  3806.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES

  3807.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES

  3808.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES

  3809.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES

  3810.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES

  3811.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES

  3812.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES

  3813.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES

  3814.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES

  3815.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES

  3816.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES

  3817.   *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES

  3818.   */

  3819. __STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)

  3820. {

  3821.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));

  3822. }

  3823. 

  3824. /**

  3825.   * @}

  3826.   */

  3827. /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance

  3828.   * @{

  3829.   */

  3830. 

  3831. /**

  3832.   * @brief  Enable the selected ADC instance.

  3833.   * @note   On this STM32 serie, after ADC enable, a delay for

  3834.   *         ADC internal analog stabilization is required before performing a

  3835.   *         ADC conversion start.

  3836.   *         Refer to device datasheet, parameter tSTAB.

  3837.   * @rmtoll CR2      ADON           LL_ADC_Enable

  3838.   * @param  ADCx ADC instance

  3839.   * @retval None

  3840.   */

  3841. __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)

  3842. {

  3843.   SET_BIT(ADCx->CR2, ADC_CR2_ADON);

  3844. }

  3845. 

  3846. /**

  3847.   * @brief  Disable the selected ADC instance.

  3848.   * @rmtoll CR2      ADON           LL_ADC_Disable

  3849.   * @param  ADCx ADC instance

  3850.   * @retval None

  3851.   */

  3852. __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)

  3853. {

  3854.   CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);

  3855. }

  3856. 

  3857. /**

  3858.   * @brief  Get the selected ADC instance enable state.

  3859.   * @rmtoll CR2      ADON           LL_ADC_IsEnabled

  3860.   * @param  ADCx ADC instance

  3861.   * @retval 0: ADC is disabled, 1: ADC is enabled.

  3862.   */

  3863. __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)

  3864. {

  3865.   return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));

  3866. }

  3867. 

  3868. /**

  3869.   * @}

  3870.   */

  3871. 

  3872. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular

  3873.   * @{

  3874.   */

  3875. 

  3876. /**

  3877.   * @brief  Start ADC group regular conversion.

  3878.   * @note   On this STM32 serie, this function is relevant only for

  3879.   *         internal trigger (SW start), not for external trigger:

  3880.   *         - If ADC trigger has been set to software start, ADC conversion

  3881.   *           starts immediately.

  3882.   *         - If ADC trigger has been set to external trigger, ADC conversion

  3883.   *           start must be performed using function

  3884.   *           @ref LL_ADC_REG_StartConversionExtTrig().

  3885.   *           (if external trigger edge would have been set during ADC other

  3886.   *           settings, ADC conversion would start at trigger event

  3887.   *           as soon as ADC is enabled).

  3888.   * @rmtoll CR2      SWSTART        LL_ADC_REG_StartConversionSWStart

  3889.   * @param  ADCx ADC instance

  3890.   * @retval None

  3891.   */

  3892. __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)

  3893. {

  3894.   SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);

  3895. }

  3896. 

  3897. /**

  3898.   * @brief  Start ADC group regular conversion from external trigger.

  3899.   * @note   ADC conversion will start at next trigger event (on the selected

  3900.   *         trigger edge) following the ADC start conversion command.

  3901.   * @note   On this STM32 serie, this function is relevant for

  3902.   *         ADC conversion start from external trigger.

  3903.   *         If internal trigger (SW start) is needed, perform ADC conversion

  3904.   *         start using function @ref LL_ADC_REG_StartConversionSWStart().

  3905.   * @rmtoll CR2      EXTEN          LL_ADC_REG_StartConversionExtTrig

  3906.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  3907.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

  3908.   *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

  3909.   *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

  3910.   * @param  ADCx ADC instance

  3911.   * @retval None

  3912.   */

  3913. __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  3914. {

  3915.   SET_BIT(ADCx->CR2, ExternalTriggerEdge);

  3916. }

  3917. 

  3918. /**

  3919.   * @brief  Stop ADC group regular conversion from external trigger.

  3920.   * @note   No more ADC conversion will start at next trigger event

  3921.   *         following the ADC stop conversion command.

  3922.   *         If a conversion is on-going, it will be completed.

  3923.   * @note   On this STM32 serie, there is no specific command

  3924.   *         to stop a conversion on-going or to stop ADC converting

  3925.   *         in continuous mode. These actions can be performed

  3926.   *         using function @ref LL_ADC_Disable().

  3927.   * @rmtoll CR2      EXTEN          LL_ADC_REG_StopConversionExtTrig

  3928.   * @param  ADCx ADC instance

  3929.   * @retval None

  3930.   */

  3931. __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)

  3932. {

  3933.   CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);

  3934. }

  3935. 

  3936. /**

  3937.   * @brief  Get ADC group regular conversion data, range fit for

  3938.   *         all ADC configurations: all ADC resolutions and

  3939.   *         all oversampling increased data width (for devices

  3940.   *         with feature oversampling).

  3941.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32

  3942.   * @param  ADCx ADC instance

  3943.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  3944.   */

  3945. __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)

  3946. {

  3947.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  3948. }

  3949. 

  3950. /**

  3951.   * @brief  Get ADC group regular conversion data, range fit for

  3952.   *         ADC resolution 12 bits.

  3953.   * @note   For devices with feature oversampling: Oversampling

  3954.   *         can increase data width, function for extended range

  3955.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  3956.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12

  3957.   * @param  ADCx ADC instance

  3958.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  3959.   */

  3960. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)

  3961. {

  3962.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  3963. }

  3964. 

  3965. /**

  3966.   * @brief  Get ADC group regular conversion data, range fit for

  3967.   *         ADC resolution 10 bits.

  3968.   * @note   For devices with feature oversampling: Oversampling

  3969.   *         can increase data width, function for extended range

  3970.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  3971.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10

  3972.   * @param  ADCx ADC instance

  3973.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  3974.   */

  3975. __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)

  3976. {

  3977.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  3978. }

  3979. 

  3980. /**

  3981.   * @brief  Get ADC group regular conversion data, range fit for

  3982.   *         ADC resolution 8 bits.

  3983.   * @note   For devices with feature oversampling: Oversampling

  3984.   *         can increase data width, function for extended range

  3985.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  3986.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8

  3987.   * @param  ADCx ADC instance

  3988.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  3989.   */

  3990. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)

  3991. {

  3992.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  3993. }

  3994. 

  3995. /**

  3996.   * @brief  Get ADC group regular conversion data, range fit for

  3997.   *         ADC resolution 6 bits.

  3998.   * @note   For devices with feature oversampling: Oversampling

  3999.   *         can increase data width, function for extended range

  4000.   *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

  4001.   * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6

  4002.   * @param  ADCx ADC instance

  4003.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F

  4004.   */

  4005. __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx)

  4006. {

  4007.   return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));

  4008. }

  4009. 

  4010. /**

  4011.   * @brief  Get ADC multimode conversion data of ADC master, ADC slave

  4012.   *         or raw data with ADC master and slave concatenated.

  4013.   * @note   If raw data with ADC master and slave concatenated is retrieved,

  4014.   *         a macro is available to get the conversion data of

  4015.   *         ADC master or ADC slave: see helper macro

  4016.   *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

  4017.   *         (however this macro is mainly intended for multimode

  4018.   *         transfer by DMA, because this function can do the same

  4019.   *         by getting multimode conversion data of ADC master or ADC slave

  4020.   *         separately).

  4021.   * @rmtoll CDR      DATA1          LL_ADC_REG_ReadMultiConversionData32\n

  4022.   *         CDR      DATA2          LL_ADC_REG_ReadMultiConversionData32

  4023.   * @param  ADCxy_COMMON ADC common instance

  4024.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4025.   * @param  ConversionData This parameter can be one of the following values:

  4026.   *         @arg @ref LL_ADC_MULTI_MASTER

  4027.   *         @arg @ref LL_ADC_MULTI_SLAVE

  4028.   *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE

  4029.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  4030.   */

  4031. __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)

  4032. {

  4033.   return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,

  4034.                              ADC_DR_ADC2DATA)

  4035.                     >> POSITION_VAL(ConversionData)

  4036.                    );

  4037. }

  4038. 

  4039. /**

  4040.   * @}

  4041.   */

  4042. 

  4043. /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected

  4044.   * @{

  4045.   */

  4046. 

  4047. /**

  4048.   * @brief  Start ADC group injected conversion.

  4049.   * @note   On this STM32 serie, this function is relevant only for

  4050.   *         internal trigger (SW start), not for external trigger:

  4051.   *         - If ADC trigger has been set to software start, ADC conversion

  4052.   *           starts immediately.

  4053.   *         - If ADC trigger has been set to external trigger, ADC conversion

  4054.   *           start must be performed using function

  4055.   *           @ref LL_ADC_INJ_StartConversionExtTrig().

  4056.   *           (if external trigger edge would have been set during ADC other

  4057.   *           settings, ADC conversion would start at trigger event

  4058.   *           as soon as ADC is enabled).

  4059.   * @rmtoll CR2      JSWSTART       LL_ADC_INJ_StartConversionSWStart

  4060.   * @param  ADCx ADC instance

  4061.   * @retval None

  4062.   */

  4063. __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)

  4064. {

  4065.   SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);

  4066. }

  4067. 

  4068. /**

  4069.   * @brief  Start ADC group injected conversion from external trigger.

  4070.   * @note   ADC conversion will start at next trigger event (on the selected

  4071.   *         trigger edge) following the ADC start conversion command.

  4072.   * @note   On this STM32 serie, this function is relevant for

  4073.   *         ADC conversion start from external trigger.

  4074.   *         If internal trigger (SW start) is needed, perform ADC conversion

  4075.   *         start using function @ref LL_ADC_INJ_StartConversionSWStart().

  4076.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StartConversionExtTrig

  4077.   * @param  ExternalTriggerEdge This parameter can be one of the following values:

  4078.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

  4079.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

  4080.   *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

  4081.   * @param  ADCx ADC instance

  4082.   * @retval None

  4083.   */

  4084. __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

  4085. {

  4086.   SET_BIT(ADCx->CR2, ExternalTriggerEdge);

  4087. }

  4088. 

  4089. /**

  4090.   * @brief  Stop ADC group injected conversion from external trigger.

  4091.   * @note   No more ADC conversion will start at next trigger event

  4092.   *         following the ADC stop conversion command.

  4093.   *         If a conversion is on-going, it will be completed.

  4094.   * @note   On this STM32 serie, there is no specific command

  4095.   *         to stop a conversion on-going or to stop ADC converting

  4096.   *         in continuous mode. These actions can be performed

  4097.   *         using function @ref LL_ADC_Disable().

  4098.   * @rmtoll CR2      JEXTEN         LL_ADC_INJ_StopConversionExtTrig

  4099.   * @param  ADCx ADC instance

  4100.   * @retval None

  4101.   */

  4102. __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)

  4103. {

  4104.   CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);

  4105. }

  4106. 

  4107. /**

  4108.   * @brief  Get ADC group regular conversion data, range fit for

  4109.   *         all ADC configurations: all ADC resolutions and

  4110.   *         all oversampling increased data width (for devices

  4111.   *         with feature oversampling).

  4112.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n

  4113.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n

  4114.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n

  4115.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32

  4116.   * @param  ADCx ADC instance

  4117.   * @param  Rank This parameter can be one of the following values:

  4118.   *         @arg @ref LL_ADC_INJ_RANK_1

  4119.   *         @arg @ref LL_ADC_INJ_RANK_2

  4120.   *         @arg @ref LL_ADC_INJ_RANK_3

  4121.   *         @arg @ref LL_ADC_INJ_RANK_4

  4122.   * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

  4123.   */

  4124. __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)

  4125. {

  4126.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4127. 

  4128.   return (uint32_t)(READ_BIT(*preg,

  4129.                              ADC_JDR1_JDATA)

  4130.                    );

  4131. }

  4132. 

  4133. /**

  4134.   * @brief  Get ADC group injected conversion data, range fit for

  4135.   *         ADC resolution 12 bits.

  4136.   * @note   For devices with feature oversampling: Oversampling

  4137.   *         can increase data width, function for extended range

  4138.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4139.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n

  4140.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n

  4141.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n

  4142.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12

  4143.   * @param  ADCx ADC instance

  4144.   * @param  Rank This parameter can be one of the following values:

  4145.   *         @arg @ref LL_ADC_INJ_RANK_1

  4146.   *         @arg @ref LL_ADC_INJ_RANK_2

  4147.   *         @arg @ref LL_ADC_INJ_RANK_3

  4148.   *         @arg @ref LL_ADC_INJ_RANK_4

  4149.   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

  4150.   */

  4151. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)

  4152. {

  4153.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4154. 

  4155.   return (uint16_t)(READ_BIT(*preg,

  4156.                              ADC_JDR1_JDATA)

  4157.                    );

  4158. }

  4159. 

  4160. /**

  4161.   * @brief  Get ADC group injected conversion data, range fit for

  4162.   *         ADC resolution 10 bits.

  4163.   * @note   For devices with feature oversampling: Oversampling

  4164.   *         can increase data width, function for extended range

  4165.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4166.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n

  4167.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n

  4168.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n

  4169.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10

  4170.   * @param  ADCx ADC instance

  4171.   * @param  Rank This parameter can be one of the following values:

  4172.   *         @arg @ref LL_ADC_INJ_RANK_1

  4173.   *         @arg @ref LL_ADC_INJ_RANK_2

  4174.   *         @arg @ref LL_ADC_INJ_RANK_3

  4175.   *         @arg @ref LL_ADC_INJ_RANK_4

  4176.   * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

  4177.   */

  4178. __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)

  4179. {

  4180.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4181. 

  4182.   return (uint16_t)(READ_BIT(*preg,

  4183.                              ADC_JDR1_JDATA)

  4184.                    );

  4185. }

  4186. 

  4187. /**

  4188.   * @brief  Get ADC group injected conversion data, range fit for

  4189.   *         ADC resolution 8 bits.

  4190.   * @note   For devices with feature oversampling: Oversampling

  4191.   *         can increase data width, function for extended range

  4192.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4193.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n

  4194.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n

  4195.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n

  4196.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8

  4197.   * @param  ADCx ADC instance

  4198.   * @param  Rank This parameter can be one of the following values:

  4199.   *         @arg @ref LL_ADC_INJ_RANK_1

  4200.   *         @arg @ref LL_ADC_INJ_RANK_2

  4201.   *         @arg @ref LL_ADC_INJ_RANK_3

  4202.   *         @arg @ref LL_ADC_INJ_RANK_4

  4203.   * @retval Value between Min_Data=0x00 and Max_Data=0xFF

  4204.   */

  4205. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)

  4206. {

  4207.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4208. 

  4209.   return (uint8_t)(READ_BIT(*preg,

  4210.                             ADC_JDR1_JDATA)

  4211.                   );

  4212. }

  4213. 

  4214. /**

  4215.   * @brief  Get ADC group injected conversion data, range fit for

  4216.   *         ADC resolution 6 bits.

  4217.   * @note   For devices with feature oversampling: Oversampling

  4218.   *         can increase data width, function for extended range

  4219.   *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

  4220.   * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n

  4221.   *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n

  4222.   *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n

  4223.   *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6

  4224.   * @param  ADCx ADC instance

  4225.   * @param  Rank This parameter can be one of the following values:

  4226.   *         @arg @ref LL_ADC_INJ_RANK_1

  4227.   *         @arg @ref LL_ADC_INJ_RANK_2

  4228.   *         @arg @ref LL_ADC_INJ_RANK_3

  4229.   *         @arg @ref LL_ADC_INJ_RANK_4

  4230.   * @retval Value between Min_Data=0x00 and Max_Data=0x3F

  4231.   */

  4232. __STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(ADC_TypeDef *ADCx, uint32_t Rank)

  4233. {

  4234.   register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));

  4235. 

  4236.   return (uint8_t)(READ_BIT(*preg,

  4237.                             ADC_JDR1_JDATA)

  4238.                   );

  4239. }

  4240. 

  4241. /**

  4242.   * @}

  4243.   */

  4244. 

  4245. /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management

  4246.   * @{

  4247.   */

  4248. 

  4249. /**

  4250.   * @brief  Get flag ADC group regular end of unitary conversion

  4251.   *         or end of sequence conversions, depending on

  4252.   *         ADC configuration.

  4253.   * @note   To configure flag of end of conversion,

  4254.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4255.   * @rmtoll SR       EOC            LL_ADC_IsActiveFlag_EOCS

  4256.   * @param  ADCx ADC instance

  4257.   * @retval State of bit (1 or 0).

  4258.   */

  4259. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(ADC_TypeDef *ADCx)

  4260. {

  4261.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));

  4262. }

  4263. 

  4264. /**

  4265.   * @brief  Get flag ADC group regular overrun.

  4266.   * @rmtoll SR       OVR            LL_ADC_IsActiveFlag_OVR

  4267.   * @param  ADCx ADC instance

  4268.   * @retval State of bit (1 or 0).

  4269.   */

  4270. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)

  4271. {

  4272.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));

  4273. }

  4274. 

  4275. 

  4276. /**

  4277.   * @brief  Get flag ADC group injected end of sequence conversions.

  4278.   * @rmtoll SR       JEOC           LL_ADC_IsActiveFlag_JEOS

  4279.   * @param  ADCx ADC instance

  4280.   * @retval State of bit (1 or 0).

  4281.   */

  4282. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)

  4283. {

  4284.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4285.   /*       end of unitary conversion.                                         */

  4286.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4287.   /*       in other STM32 families).                                          */

  4288.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));

  4289. }

  4290. 

  4291. /**

  4292.   * @brief  Get flag ADC analog watchdog 1 flag

  4293.   * @rmtoll SR       AWD            LL_ADC_IsActiveFlag_AWD1

  4294.   * @param  ADCx ADC instance

  4295.   * @retval State of bit (1 or 0).

  4296.   */

  4297. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)

  4298. {

  4299.   return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));

  4300. }

  4301. 

  4302. /**

  4303.   * @brief  Clear flag ADC group regular end of unitary conversion

  4304.   *         or end of sequence conversions, depending on

  4305.   *         ADC configuration.

  4306.   * @note   To configure flag of end of conversion,

  4307.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4308.   * @rmtoll SR       EOC            LL_ADC_ClearFlag_EOCS

  4309.   * @param  ADCx ADC instance

  4310.   * @retval None

  4311.   */

  4312. __STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)

  4313. {

  4314.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);

  4315. }

  4316. 

  4317. /**

  4318.   * @brief  Clear flag ADC group regular overrun.

  4319.   * @rmtoll SR       OVR            LL_ADC_ClearFlag_OVR

  4320.   * @param  ADCx ADC instance

  4321.   * @retval None

  4322.   */

  4323. __STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)

  4324. {

  4325.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);

  4326. }

  4327. 

  4328. 

  4329. /**

  4330.   * @brief  Clear flag ADC group injected end of sequence conversions.

  4331.   * @rmtoll SR       JEOC           LL_ADC_ClearFlag_JEOS

  4332.   * @param  ADCx ADC instance

  4333.   * @retval None

  4334.   */

  4335. __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)

  4336. {

  4337.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4338.   /*       end of unitary conversion.                                         */

  4339.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4340.   /*       in other STM32 families).                                          */

  4341.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);

  4342. }

  4343. 

  4344. /**

  4345.   * @brief  Clear flag ADC analog watchdog 1.

  4346.   * @rmtoll SR       AWD            LL_ADC_ClearFlag_AWD1

  4347.   * @param  ADCx ADC instance

  4348.   * @retval None

  4349.   */

  4350. __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)

  4351. {

  4352.   WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);

  4353. }

  4354. 

  4355. /**

  4356.   * @brief  Get flag multimode ADC group regular end of unitary conversion

  4357.   *         or end of sequence conversions, depending on

  4358.   *         ADC configuration, of the ADC master.

  4359.   * @note   To configure flag of end of conversion,

  4360.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4361.   * @rmtoll CSR      EOC1           LL_ADC_IsActiveFlag_MST_EOCS

  4362.   * @param  ADCxy_COMMON ADC common instance

  4363.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4364.   * @retval State of bit (1 or 0).

  4365.   */

  4366. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)

  4367. {

  4368.   return (READ_BIT(ADC1->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));

  4369. }

  4370. 

  4371. /**

  4372.   * @brief  Get flag multimode ADC group regular end of unitary conversion

  4373.   *         or end of sequence conversions, depending on

  4374.   *         ADC configuration, of the ADC slave 1.

  4375.   * @note   To configure flag of end of conversion,

  4376.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4377.   * @rmtoll CSR      EOC2           LL_ADC_IsActiveFlag_SLV1_EOCS

  4378.   * @param  ADCxy_COMMON ADC common instance

  4379.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4380.   * @retval State of bit (1 or 0).

  4381.   */

  4382. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)

  4383. {

  4384.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));

  4385. }

  4386. 

  4387. /**

  4388.   * @brief  Get flag multimode ADC group regular end of unitary conversion

  4389.   *         or end of sequence conversions, depending on

  4390.   *         ADC configuration, of the ADC slave 2.

  4391.   * @note   To configure flag of end of conversion,

  4392.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4393.   * @rmtoll CSR      EOC3           LL_ADC_IsActiveFlag_SLV2_EOCS

  4394.   * @param  ADCxy_COMMON ADC common instance

  4395.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4396.   * @retval State of bit (1 or 0).

  4397.   */

  4398. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(ADC_Common_TypeDef *ADCxy_COMMON)

  4399. {

  4400.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));

  4401. }

  4402. /**

  4403.   * @brief  Get flag multimode ADC group regular overrun of the ADC master.

  4404.   * @rmtoll CSR      OVR1           LL_ADC_IsActiveFlag_MST_OVR

  4405.   * @param  ADCxy_COMMON ADC common instance

  4406.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4407.   * @retval State of bit (1 or 0).

  4408.   */

  4409. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  4410. {

  4411.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));

  4412. }

  4413. 

  4414. /**

  4415.   * @brief  Get flag multimode ADC group regular overrun of the ADC slave 1.

  4416.   * @rmtoll CSR      OVR2           LL_ADC_IsActiveFlag_SLV1_OVR

  4417.   * @param  ADCxy_COMMON ADC common instance

  4418.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4419.   * @retval State of bit (1 or 0).

  4420.   */

  4421. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  4422. {

  4423.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));

  4424. }

  4425. 

  4426. /**

  4427.   * @brief  Get flag multimode ADC group regular overrun of the ADC slave 2.

  4428.   * @rmtoll CSR      OVR3           LL_ADC_IsActiveFlag_SLV2_OVR

  4429.   * @param  ADCxy_COMMON ADC common instance

  4430.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4431.   * @retval State of bit (1 or 0).

  4432.   */

  4433. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

  4434. {

  4435.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));

  4436. }

  4437. 

  4438. 

  4439. /**

  4440.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.

  4441.   * @rmtoll CSR      JEOC           LL_ADC_IsActiveFlag_MST_EOCS

  4442.   * @param  ADCxy_COMMON ADC common instance

  4443.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4444.   * @retval State of bit (1 or 0).

  4445.   */

  4446. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  4447. {

  4448.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4449.   /*       end of unitary conversion.                                         */

  4450.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4451.   /*       in other STM32 families).                                          */

  4452.   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));

  4453. }

  4454. 

  4455. /**

  4456.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave 1.

  4457.   * @rmtoll CSR      JEOC2          LL_ADC_IsActiveFlag_SLV1_JEOS

  4458.   * @param  ADCxy_COMMON ADC common instance

  4459.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4460.   * @retval State of bit (1 or 0).

  4461.   */

  4462. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  4463. {

  4464.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4465.   /*       end of unitary conversion.                                         */

  4466.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4467.   /*       in other STM32 families).                                          */

  4468.   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));

  4469. }

  4470. 

  4471. /**

  4472.   * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave 2.

  4473.   * @rmtoll CSR      JEOC3          LL_ADC_IsActiveFlag_SLV2_JEOS

  4474.   * @param  ADCxy_COMMON ADC common instance

  4475.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4476.   * @retval State of bit (1 or 0).

  4477.   */

  4478. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

  4479. {

  4480.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4481.   /*       end of unitary conversion.                                         */

  4482.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4483.   /*       in other STM32 families).                                          */

  4484.   return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));

  4485. }

  4486. 

  4487. /**

  4488.   * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.

  4489.   * @rmtoll CSR      AWD1           LL_ADC_IsActiveFlag_MST_AWD1

  4490.   * @param  ADCxy_COMMON ADC common instance

  4491.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4492.   * @retval State of bit (1 or 0).

  4493.   */

  4494. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  4495. {

  4496.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));

  4497. }

  4498. 

  4499. /**

  4500.   * @brief  Get flag multimode analog watchdog 1 of the ADC slave 1.

  4501.   * @rmtoll CSR      AWD2           LL_ADC_IsActiveFlag_SLV1_AWD1

  4502.   * @param  ADCxy_COMMON ADC common instance

  4503.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4504.   * @retval State of bit (1 or 0).

  4505.   */

  4506. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  4507. {

  4508.   return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));

  4509. }

  4510. 

  4511. /**

  4512.   * @brief  Get flag multimode analog watchdog 1 of the ADC slave 2.

  4513.   * @rmtoll CSR      AWD3           LL_ADC_IsActiveFlag_SLV2_AWD1

  4514.   * @param  ADCxy_COMMON ADC common instance

  4515.   *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

  4516.   * @retval State of bit (1 or 0).

  4517.   */

  4518. __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

  4519. {

  4520.     return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));

  4521. }

  4522. 

  4523. 

  4524. /**

  4525.   * @}

  4526.   */

  4527. 

  4528. /** @defgroup ADC_LL_EF_IT_Management ADC IT management

  4529.   * @{

  4530.   */

  4531. 

  4532. /**

  4533.   * @brief  Enable interruption ADC group regular end of unitary conversion

  4534.   *         or end of sequence conversions, depending on

  4535.   *         ADC configuration.

  4536.   * @note   To configure flag of end of conversion,

  4537.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4538.   * @rmtoll CR1      EOCIE          LL_ADC_EnableIT_EOCS

  4539.   * @param  ADCx ADC instance

  4540.   * @retval None

  4541.   */

  4542. __STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)

  4543. {

  4544.   SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);

  4545. }

  4546. 

  4547. /**

  4548.   * @brief  Enable ADC group regular interruption overrun.

  4549.   * @rmtoll CR1      OVRIE          LL_ADC_EnableIT_OVR

  4550.   * @param  ADCx ADC instance

  4551.   * @retval None

  4552.   */

  4553. __STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)

  4554. {

  4555.   SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);

  4556. }

  4557. 

  4558. 

  4559. /**

  4560.   * @brief  Enable interruption ADC group injected end of sequence conversions.

  4561.   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS

  4562.   * @param  ADCx ADC instance

  4563.   * @retval None

  4564.   */

  4565. __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)

  4566. {

  4567.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4568.   /*       end of unitary conversion.                                         */

  4569.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4570.   /*       in other STM32 families).                                          */

  4571.   SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);

  4572. }

  4573. 

  4574. /**

  4575.   * @brief  Enable interruption ADC analog watchdog 1.

  4576.   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1

  4577.   * @param  ADCx ADC instance

  4578.   * @retval None

  4579.   */

  4580. __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)

  4581. {

  4582.   SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);

  4583. }

  4584. 

  4585. /**

  4586.   * @brief  Disable interruption ADC group regular end of unitary conversion

  4587.   *         or end of sequence conversions, depending on

  4588.   *         ADC configuration.

  4589.   * @note   To configure flag of end of conversion,

  4590.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4591.   * @rmtoll CR1      EOCIE          LL_ADC_DisableIT_EOCS

  4592.   * @param  ADCx ADC instance

  4593.   * @retval None

  4594.   */

  4595. __STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)

  4596. {

  4597.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);

  4598. }

  4599. 

  4600. /**

  4601.   * @brief  Disable interruption ADC group regular overrun.

  4602.   * @rmtoll CR1      OVRIE          LL_ADC_DisableIT_OVR

  4603.   * @param  ADCx ADC instance

  4604.   * @retval None

  4605.   */

  4606. __STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)

  4607. {

  4608.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);

  4609. }

  4610. 

  4611. 

  4612. /**

  4613.   * @brief  Disable interruption ADC group injected end of sequence conversions.

  4614.   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS

  4615.   * @param  ADCx ADC instance

  4616.   * @retval None

  4617.   */

  4618. __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)

  4619. {

  4620.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4621.   /*       end of unitary conversion.                                         */

  4622.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4623.   /*       in other STM32 families).                                          */

  4624.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);

  4625. }

  4626. 

  4627. /**

  4628.   * @brief  Disable interruption ADC analog watchdog 1.

  4629.   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1

  4630.   * @param  ADCx ADC instance

  4631.   * @retval None

  4632.   */

  4633. __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)

  4634. {

  4635.   CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);

  4636. }

  4637. 

  4638. /**

  4639.   * @brief  Get state of interruption ADC group regular end of unitary conversion

  4640.   *         or end of sequence conversions, depending on

  4641.   *         ADC configuration.

  4642.   * @note   To configure flag of end of conversion,

  4643.   *         use function @ref LL_ADC_REG_SetFlagEndOfConversion().

  4644.   *         (0: interrupt disabled, 1: interrupt enabled)

  4645.   * @rmtoll CR1      EOCIE          LL_ADC_IsEnabledIT_EOCS

  4646.   * @param  ADCx ADC instance

  4647.   * @retval State of bit (1 or 0).

  4648.   */

  4649. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(ADC_TypeDef *ADCx)

  4650. {

  4651.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));

  4652. }

  4653. 

  4654. /**

  4655.   * @brief  Get state of interruption ADC group regular overrun

  4656.   *         (0: interrupt disabled, 1: interrupt enabled).

  4657.   * @rmtoll CR1      OVRIE          LL_ADC_IsEnabledIT_OVR

  4658.   * @param  ADCx ADC instance

  4659.   * @retval State of bit (1 or 0).

  4660.   */

  4661. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)

  4662. {

  4663.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));

  4664. }

  4665. 

  4666. 

  4667. /**

  4668.   * @brief  Get state of interruption ADC group injected end of sequence conversions

  4669.   *         (0: interrupt disabled, 1: interrupt enabled).

  4670.   * @rmtoll CR1      JEOCIE         LL_ADC_EnableIT_JEOS

  4671.   * @param  ADCx ADC instance

  4672.   * @retval State of bit (1 or 0).

  4673.   */

  4674. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)

  4675. {

  4676.   /* Note: on this STM32 serie, there is no flag ADC group injected          */

  4677.   /*       end of unitary conversion.                                         */

  4678.   /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */

  4679.   /*       in other STM32 families).                                          */

  4680.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));

  4681. }

  4682. 

  4683. /**

  4684.   * @brief  Get state of interruption ADC analog watchdog 1

  4685.   *         (0: interrupt disabled, 1: interrupt enabled).

  4686.   * @rmtoll CR1      AWDIE          LL_ADC_EnableIT_AWD1

  4687.   * @param  ADCx ADC instance

  4688.   * @retval State of bit (1 or 0).

  4689.   */

  4690. __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)

  4691. {

  4692.   return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));

  4693. }

  4694. 

  4695. /**

  4696.   * @}

  4697.   */

  4698. 

  4699. #if defined(USE_FULL_LL_DRIVER)

  4700. /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions

  4701.   * @{

  4702.   */

  4703. 

  4704. /* Initialization of some features of ADC common parameters and multimode */

  4705. ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);

  4706. ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  4707. void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

  4708. 

  4709. /* De-initialization of ADC instance, ADC group regular and ADC group injected */

  4710. /* (availability of ADC group injected depends on STM32 families) */

  4711. ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

  4712. 

  4713. /* Initialization of some features of ADC instance */

  4714. ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);

  4715. void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

  4716. 

  4717. /* Initialization of some features of ADC instance and ADC group regular */

  4718. ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  4719. void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

  4720. 

  4721. /* Initialization of some features of ADC instance and ADC group injected */

  4722. ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  4723. void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

  4724. 

  4725. /**

  4726.   * @}

  4727.   */

  4728. #endif /* USE_FULL_LL_DRIVER */

  4729. 

  4730. /**

  4731.   * @}

  4732.   */

  4733. 

  4734. /**

  4735.   * @}

  4736.   */

  4737. 

  4738. #endif /* ADC1 || ADC2 || ADC3 */

  4739. 

  4740. /**

  4741.   * @}

  4742.   */

  4743. 

  4744. #ifdef __cplusplus

  4745. }

  4746. #endif

  4747. 

  4748. #endif /* __STM32F7xx_LL_ADC_H */

  4749. 

  4750. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/