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  1. /**
  2. ******************************************************************************
  3. * @file stm32_hal_legacy.h
  4. * @author MCD Application Team
  5. * @version V1.2.2
  6. * @date 14-April-2017
  7. * @brief This file contains aliases definition for the STM32Cube HAL constants
  8. * macros and functions maintained for legacy purpose.
  9. ******************************************************************************
  10. * @attention
  11. *
  12. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  13. *
  14. * Redistribution and use in source and binary forms, with or without modification,
  15. * are permitted provided that the following conditions are met:
  16. * 1. Redistributions of source code must retain the above copyright notice,
  17. * this list of conditions and the following disclaimer.
  18. * 2. Redistributions in binary form must reproduce the above copyright notice,
  19. * this list of conditions and the following disclaimer in the documentation
  20. * and/or other materials provided with the distribution.
  21. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  22. * may be used to endorse or promote products derived from this software
  23. * without specific prior written permission.
  24. *
  25. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  26. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  28. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  29. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  31. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  32. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  33. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  34. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. *
  36. ******************************************************************************
  37. */
  38. /* Define to prevent recursive inclusion -------------------------------------*/
  39. #ifndef __STM32_HAL_LEGACY
  40. #define __STM32_HAL_LEGACY
  41. #ifdef __cplusplus
  42. extern "C" {
  43. #endif
  44. /* Includes ------------------------------------------------------------------*/
  45. /* Exported types ------------------------------------------------------------*/
  46. /* Exported constants --------------------------------------------------------*/
  47. /** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
  48. * @{
  49. */
  50. #define AES_FLAG_RDERR CRYP_FLAG_RDERR
  51. #define AES_FLAG_WRERR CRYP_FLAG_WRERR
  52. #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
  53. #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
  54. #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
  55. /**
  56. * @}
  57. */
  58. /** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
  59. * @{
  60. */
  61. #define ADC_RESOLUTION12b ADC_RESOLUTION_12B
  62. #define ADC_RESOLUTION10b ADC_RESOLUTION_10B
  63. #define ADC_RESOLUTION8b ADC_RESOLUTION_8B
  64. #define ADC_RESOLUTION6b ADC_RESOLUTION_6B
  65. #define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN
  66. #define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED
  67. #define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV
  68. #define EOC_SEQ_CONV ADC_EOC_SEQ_CONV
  69. #define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV
  70. #define REGULAR_GROUP ADC_REGULAR_GROUP
  71. #define INJECTED_GROUP ADC_INJECTED_GROUP
  72. #define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP
  73. #define AWD_EVENT ADC_AWD_EVENT
  74. #define AWD1_EVENT ADC_AWD1_EVENT
  75. #define AWD2_EVENT ADC_AWD2_EVENT
  76. #define AWD3_EVENT ADC_AWD3_EVENT
  77. #define OVR_EVENT ADC_OVR_EVENT
  78. #define JQOVF_EVENT ADC_JQOVF_EVENT
  79. #define ALL_CHANNELS ADC_ALL_CHANNELS
  80. #define REGULAR_CHANNELS ADC_REGULAR_CHANNELS
  81. #define INJECTED_CHANNELS ADC_INJECTED_CHANNELS
  82. #define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR
  83. #define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT
  84. #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1
  85. #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2
  86. #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
  87. #define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
  88. #define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
  89. #define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
  90. #define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
  91. #define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
  92. #define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
  93. #define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
  94. #define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
  95. #define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
  96. #define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE
  97. #define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
  98. #define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
  99. #define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
  100. #define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
  101. #define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
  102. #define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
  103. #define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC
  104. #define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
  105. #define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
  106. #define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
  107. #define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
  108. /**
  109. * @}
  110. */
  111. /** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
  112. * @{
  113. */
  114. #define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
  115. /**
  116. * @}
  117. */
  118. /** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
  119. * @{
  120. */
  121. #define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
  122. #define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
  123. #define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
  124. #define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2
  125. #define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3
  126. #define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4
  127. #define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
  128. #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
  129. #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
  130. #define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
  131. #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
  132. #if defined(STM32F373xC) || defined(STM32F378xx)
  133. #define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
  134. #define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
  135. #endif /* STM32F373xC || STM32F378xx */
  136. #if defined(STM32L0) || defined(STM32L4)
  137. #define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
  138. #define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
  139. #define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
  140. #define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
  141. #define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
  142. #define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
  143. #define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
  144. #define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
  145. #define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
  146. #define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
  147. #define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
  148. #define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
  149. #define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
  150. #define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
  151. #define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
  152. #define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
  153. #if defined(STM32L0)
  154. /* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */
  155. /* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */
  156. /* to the second dedicated IO (only for COMP2). */
  157. #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2
  158. #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2
  159. #else
  160. #define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
  161. #define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
  162. #endif
  163. #define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
  164. #define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
  165. #define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
  166. #define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
  167. /* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
  168. /* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
  169. #if defined(COMP_CSR_LOCK)
  170. #define COMP_FLAG_LOCK COMP_CSR_LOCK
  171. #elif defined(COMP_CSR_COMP1LOCK)
  172. #define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
  173. #elif defined(COMP_CSR_COMPxLOCK)
  174. #define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
  175. #endif
  176. #if defined(STM32L4)
  177. #define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
  178. #define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
  179. #define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
  180. #define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
  181. #define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
  182. #define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
  183. #define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
  184. #endif
  185. #if defined(STM32L0)
  186. #define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
  187. #define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
  188. #else
  189. #define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
  190. #define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
  191. #define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
  192. #define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
  193. #endif
  194. #endif
  195. /**
  196. * @}
  197. */
  198. /** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
  199. * @{
  200. */
  201. #define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
  202. /**
  203. * @}
  204. */
  205. /** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
  206. * @{
  207. */
  208. #define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
  209. #define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
  210. /**
  211. * @}
  212. */
  213. /** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
  214. * @{
  215. */
  216. #define DAC1_CHANNEL_1 DAC_CHANNEL_1
  217. #define DAC1_CHANNEL_2 DAC_CHANNEL_2
  218. #define DAC2_CHANNEL_1 DAC_CHANNEL_1
  219. #define DAC_WAVE_NONE 0x00000000U
  220. #define DAC_WAVE_NOISE DAC_CR_WAVE1_0
  221. #define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1
  222. #define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
  223. #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
  224. #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
  225. /**
  226. * @}
  227. */
  228. /** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
  229. * @{
  230. */
  231. #define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
  232. #define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
  233. #define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
  234. #define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
  235. #define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
  236. #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
  237. #define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
  238. #define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
  239. #define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
  240. #define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
  241. #define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
  242. #define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
  243. #define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
  244. #define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
  245. #define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
  246. #define IS_HAL_REMAPDMA IS_DMA_REMAP
  247. #define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
  248. #define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
  249. /**
  250. * @}
  251. */
  252. /** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
  253. * @{
  254. */
  255. #define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
  256. #define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
  257. #define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
  258. #define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD
  259. #define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS
  260. #define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES
  261. #define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES
  262. #define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE
  263. #define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE
  264. #define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE
  265. #define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE
  266. #define OBEX_PCROP OPTIONBYTE_PCROP
  267. #define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG
  268. #define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE
  269. #define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE
  270. #define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE
  271. #define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD
  272. #define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD
  273. #define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE
  274. #define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD
  275. #define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD
  276. #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE
  277. #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD
  278. #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD
  279. #define PAGESIZE FLASH_PAGE_SIZE
  280. #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE
  281. #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD
  282. #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD
  283. #define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1
  284. #define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2
  285. #define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3
  286. #define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4
  287. #define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST
  288. #define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST
  289. #define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA
  290. #define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB
  291. #define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA
  292. #define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB
  293. #define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE
  294. #define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN
  295. #define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE
  296. #define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN
  297. #define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE
  298. #define FLASH_ERROR_RD HAL_FLASH_ERROR_RD
  299. #define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG
  300. #define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS
  301. #define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP
  302. #define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV
  303. #define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR
  304. #define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG
  305. #define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION
  306. #define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA
  307. #define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE
  308. #define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE
  309. #define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS
  310. #define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS
  311. #define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST
  312. #define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR
  313. #define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO
  314. #define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION
  315. #define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS
  316. #define OB_WDG_SW OB_IWDG_SW
  317. #define OB_WDG_HW OB_IWDG_HW
  318. #define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET
  319. #define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET
  320. #define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET
  321. #define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET
  322. #define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR
  323. #define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
  324. #define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
  325. #define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
  326. /**
  327. * @}
  328. */
  329. /** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
  330. * @{
  331. */
  332. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
  333. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
  334. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
  335. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7
  336. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8
  337. #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9
  338. #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
  339. #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
  340. #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
  341. /**
  342. * @}
  343. */
  344. /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
  345. * @{
  346. */
  347. #if defined(STM32L4) || defined(STM32F7)
  348. #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
  349. #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
  350. #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
  351. #define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16
  352. #else
  353. #define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE
  354. #define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE
  355. #define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8
  356. #define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16
  357. #endif
  358. /**
  359. * @}
  360. */
  361. /** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
  362. * @{
  363. */
  364. #define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
  365. #define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
  366. /**
  367. * @}
  368. */
  369. /** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
  370. * @{
  371. */
  372. #define GET_GPIO_SOURCE GPIO_GET_INDEX
  373. #define GET_GPIO_INDEX GPIO_GET_INDEX
  374. #if defined(STM32F4)
  375. #define GPIO_AF12_SDMMC GPIO_AF12_SDIO
  376. #define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO
  377. #endif
  378. #if defined(STM32F7)
  379. #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
  380. #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
  381. #endif
  382. #if defined(STM32L4)
  383. #define GPIO_AF12_SDIO GPIO_AF12_SDMMC1
  384. #define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1
  385. #endif
  386. #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
  387. #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
  388. #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
  389. #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
  390. #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
  391. #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
  392. #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
  393. #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
  394. #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
  395. #if defined(STM32L1)
  396. #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
  397. #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
  398. #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
  399. #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
  400. #endif /* STM32L1 */
  401. #if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
  402. #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
  403. #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
  404. #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
  405. #endif /* STM32F0 || STM32F3 || STM32F1 */
  406. #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
  407. /**
  408. * @}
  409. */
  410. /** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
  411. * @{
  412. */
  413. #define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
  414. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
  415. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
  416. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
  417. #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
  418. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
  419. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
  420. #define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
  421. #define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
  422. #define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
  423. #define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
  424. #define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
  425. #define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD
  426. #define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
  427. #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
  428. #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
  429. #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
  430. /**
  431. * @}
  432. */
  433. /** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
  434. * @{
  435. */
  436. #define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE
  437. #define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE
  438. #define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE
  439. #define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE
  440. #define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE
  441. #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
  442. #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
  443. #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
  444. #if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
  445. #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
  446. #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
  447. #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
  448. #define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
  449. #define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
  450. #define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
  451. #endif
  452. /**
  453. * @}
  454. */
  455. /** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
  456. * @{
  457. */
  458. #define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE
  459. #define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE
  460. /**
  461. * @}
  462. */
  463. /** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
  464. * @{
  465. */
  466. #define KR_KEY_RELOAD IWDG_KEY_RELOAD
  467. #define KR_KEY_ENABLE IWDG_KEY_ENABLE
  468. #define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE
  469. #define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE
  470. /**
  471. * @}
  472. */
  473. /** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
  474. * @{
  475. */
  476. #define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
  477. #define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
  478. #define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
  479. #define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
  480. #define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING
  481. #define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING
  482. #define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING
  483. #define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
  484. #define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
  485. #define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
  486. #define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
  487. /* The following 3 definition have also been present in a temporary version of lptim.h */
  488. /* They need to be renamed also to the right name, just in case */
  489. #define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS
  490. #define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
  491. #define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
  492. /**
  493. * @}
  494. */
  495. /** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
  496. * @{
  497. */
  498. #define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
  499. #define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
  500. #define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
  501. #define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
  502. #define NAND_AddressTypedef NAND_AddressTypeDef
  503. #define __ARRAY_ADDRESS ARRAY_ADDRESS
  504. #define __ADDR_1st_CYCLE ADDR_1ST_CYCLE
  505. #define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE
  506. #define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE
  507. #define __ADDR_4th_CYCLE ADDR_4TH_CYCLE
  508. /**
  509. * @}
  510. */
  511. /** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
  512. * @{
  513. */
  514. #define NOR_StatusTypedef HAL_NOR_StatusTypeDef
  515. #define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS
  516. #define NOR_ONGOING HAL_NOR_STATUS_ONGOING
  517. #define NOR_ERROR HAL_NOR_STATUS_ERROR
  518. #define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT
  519. #define __NOR_WRITE NOR_WRITE
  520. #define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT
  521. /**
  522. * @}
  523. */
  524. /** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
  525. * @{
  526. */
  527. #define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0
  528. #define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
  529. #define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
  530. #define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
  531. #define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
  532. #define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
  533. #define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
  534. #define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
  535. #define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
  536. #define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
  537. #define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
  538. #define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
  539. #define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
  540. #define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
  541. #define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
  542. #define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
  543. #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
  544. #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
  545. /**
  546. * @}
  547. */
  548. /** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
  549. * @{
  550. */
  551. #define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
  552. #if defined(STM32F7)
  553. #define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
  554. #endif
  555. /**
  556. * @}
  557. */
  558. /** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
  559. * @{
  560. */
  561. /* Compact Flash-ATA registers description */
  562. #define CF_DATA ATA_DATA
  563. #define CF_SECTOR_COUNT ATA_SECTOR_COUNT
  564. #define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
  565. #define CF_CYLINDER_LOW ATA_CYLINDER_LOW
  566. #define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
  567. #define CF_CARD_HEAD ATA_CARD_HEAD
  568. #define CF_STATUS_CMD ATA_STATUS_CMD
  569. #define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
  570. #define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
  571. /* Compact Flash-ATA commands */
  572. #define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
  573. #define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
  574. #define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
  575. #define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
  576. #define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef
  577. #define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS
  578. #define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING
  579. #define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR
  580. #define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT
  581. /**
  582. * @}
  583. */
  584. /** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
  585. * @{
  586. */
  587. #define FORMAT_BIN RTC_FORMAT_BIN
  588. #define FORMAT_BCD RTC_FORMAT_BCD
  589. #define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
  590. #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
  591. #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
  592. #define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
  593. #define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
  594. #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
  595. #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
  596. #define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
  597. #define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
  598. #define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
  599. #define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
  600. #define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
  601. #define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
  602. #define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
  603. #define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
  604. #define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
  605. #define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
  606. #define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
  607. #define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
  608. #define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
  609. #define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
  610. #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
  611. #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
  612. /**
  613. * @}
  614. */
  615. /** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
  616. * @{
  617. */
  618. #define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE
  619. #define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE
  620. #define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE
  621. #define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE
  622. #define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE
  623. #define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE
  624. #define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE
  625. #define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE
  626. #define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE
  627. #define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE
  628. /**
  629. * @}
  630. */
  631. /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
  632. * @{
  633. */
  634. #define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
  635. #define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE
  636. #define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE
  637. #define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE
  638. #define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE
  639. #define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE
  640. #define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE
  641. #define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE
  642. #define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE
  643. #define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE
  644. #define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN
  645. /**
  646. * @}
  647. */
  648. /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
  649. * @{
  650. */
  651. #define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
  652. #define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE
  653. #define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE
  654. #define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE
  655. #define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE
  656. #define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE
  657. /**
  658. * @}
  659. */
  660. /** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
  661. * @{
  662. */
  663. #define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
  664. #define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
  665. #define TIM_DMABase_CR1 TIM_DMABASE_CR1
  666. #define TIM_DMABase_CR2 TIM_DMABASE_CR2
  667. #define TIM_DMABase_SMCR TIM_DMABASE_SMCR
  668. #define TIM_DMABase_DIER TIM_DMABASE_DIER
  669. #define TIM_DMABase_SR TIM_DMABASE_SR
  670. #define TIM_DMABase_EGR TIM_DMABASE_EGR
  671. #define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1
  672. #define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2
  673. #define TIM_DMABase_CCER TIM_DMABASE_CCER
  674. #define TIM_DMABase_CNT TIM_DMABASE_CNT
  675. #define TIM_DMABase_PSC TIM_DMABASE_PSC
  676. #define TIM_DMABase_ARR TIM_DMABASE_ARR
  677. #define TIM_DMABase_RCR TIM_DMABASE_RCR
  678. #define TIM_DMABase_CCR1 TIM_DMABASE_CCR1
  679. #define TIM_DMABase_CCR2 TIM_DMABASE_CCR2
  680. #define TIM_DMABase_CCR3 TIM_DMABASE_CCR3
  681. #define TIM_DMABase_CCR4 TIM_DMABASE_CCR4
  682. #define TIM_DMABase_BDTR TIM_DMABASE_BDTR
  683. #define TIM_DMABase_DCR TIM_DMABASE_DCR
  684. #define TIM_DMABase_DMAR TIM_DMABASE_DMAR
  685. #define TIM_DMABase_OR1 TIM_DMABASE_OR1
  686. #define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3
  687. #define TIM_DMABase_CCR5 TIM_DMABASE_CCR5
  688. #define TIM_DMABase_CCR6 TIM_DMABASE_CCR6
  689. #define TIM_DMABase_OR2 TIM_DMABASE_OR2
  690. #define TIM_DMABase_OR3 TIM_DMABASE_OR3
  691. #define TIM_DMABase_OR TIM_DMABASE_OR
  692. #define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE
  693. #define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1
  694. #define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2
  695. #define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3
  696. #define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4
  697. #define TIM_EventSource_COM TIM_EVENTSOURCE_COM
  698. #define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER
  699. #define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK
  700. #define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2
  701. #define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER
  702. #define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS
  703. #define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS
  704. #define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS
  705. #define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS
  706. #define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS
  707. #define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS
  708. #define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS
  709. #define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS
  710. #define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS
  711. #define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS
  712. #define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS
  713. #define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS
  714. #define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS
  715. #define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS
  716. #define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS
  717. #define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS
  718. #define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS
  719. /**
  720. * @}
  721. */
  722. /** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
  723. * @{
  724. */
  725. #define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING
  726. #define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING
  727. /**
  728. * @}
  729. */
  730. /** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
  731. * @{
  732. */
  733. #define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
  734. #define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
  735. #define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE
  736. #define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE
  737. #define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE
  738. #define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE
  739. #define __DIV_SAMPLING16 UART_DIV_SAMPLING16
  740. #define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16
  741. #define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16
  742. #define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16
  743. #define __DIV_SAMPLING8 UART_DIV_SAMPLING8
  744. #define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8
  745. #define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8
  746. #define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8
  747. #define __DIV_LPUART UART_DIV_LPUART
  748. #define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE
  749. #define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK
  750. /**
  751. * @}
  752. */
  753. /** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
  754. * @{
  755. */
  756. #define USART_CLOCK_DISABLED USART_CLOCK_DISABLE
  757. #define USART_CLOCK_ENABLED USART_CLOCK_ENABLE
  758. #define USARTNACK_ENABLED USART_NACK_ENABLE
  759. #define USARTNACK_DISABLED USART_NACK_DISABLE
  760. /**
  761. * @}
  762. */
  763. /** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
  764. * @{
  765. */
  766. #define CFR_BASE WWDG_CFR_BASE
  767. /**
  768. * @}
  769. */
  770. /** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
  771. * @{
  772. */
  773. #define CAN_FilterFIFO0 CAN_FILTER_FIFO0
  774. #define CAN_FilterFIFO1 CAN_FILTER_FIFO1
  775. #define CAN_IT_RQCP0 CAN_IT_TME
  776. #define CAN_IT_RQCP1 CAN_IT_TME
  777. #define CAN_IT_RQCP2 CAN_IT_TME
  778. #define INAK_TIMEOUT CAN_TIMEOUT_VALUE
  779. #define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
  780. #define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
  781. #define CAN_TXSTATUS_OK ((uint8_t)0x01U)
  782. #define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
  783. /**
  784. * @}
  785. */
  786. /** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
  787. * @{
  788. */
  789. #define VLAN_TAG ETH_VLAN_TAG
  790. #define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD
  791. #define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD
  792. #define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD
  793. #define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK
  794. #define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK
  795. #define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
  796. #define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
  797. #define ETH_MMCCR 0x00000100U
  798. #define ETH_MMCRIR 0x00000104U
  799. #define ETH_MMCTIR 0x00000108U
  800. #define ETH_MMCRIMR 0x0000010CU
  801. #define ETH_MMCTIMR 0x00000110U
  802. #define ETH_MMCTGFSCCR 0x0000014CU
  803. #define ETH_MMCTGFMSCCR 0x00000150U
  804. #define ETH_MMCTGFCR 0x00000168U
  805. #define ETH_MMCRFCECR 0x00000194U
  806. #define ETH_MMCRFAECR 0x00000198U
  807. #define ETH_MMCRGUFCR 0x000001C4U
  808. #define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
  809. #define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
  810. #define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
  811. #define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
  812. #define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
  813. #define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
  814. #define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
  815. #define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
  816. #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
  817. #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
  818. #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
  819. #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
  820. #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
  821. #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
  822. #define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
  823. #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
  824. #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
  825. #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
  826. #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
  827. #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
  828. #define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
  829. #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
  830. #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
  831. #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
  832. #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */
  833. #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
  834. #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
  835. /**
  836. * @}
  837. */
  838. /** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
  839. * @{
  840. */
  841. #define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
  842. #define DCMI_IT_OVF DCMI_IT_OVR
  843. #define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
  844. #define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
  845. #define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
  846. #define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
  847. #define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
  848. /**
  849. * @}
  850. */
  851. #if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
  852. defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
  853. /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
  854. * @{
  855. */
  856. #define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
  857. #define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
  858. #define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
  859. #define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
  860. #define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
  861. #define CM_ARGB8888 DMA2D_INPUT_ARGB8888
  862. #define CM_RGB888 DMA2D_INPUT_RGB888
  863. #define CM_RGB565 DMA2D_INPUT_RGB565
  864. #define CM_ARGB1555 DMA2D_INPUT_ARGB1555
  865. #define CM_ARGB4444 DMA2D_INPUT_ARGB4444
  866. #define CM_L8 DMA2D_INPUT_L8
  867. #define CM_AL44 DMA2D_INPUT_AL44
  868. #define CM_AL88 DMA2D_INPUT_AL88
  869. #define CM_L4 DMA2D_INPUT_L4
  870. #define CM_A8 DMA2D_INPUT_A8
  871. #define CM_A4 DMA2D_INPUT_A4
  872. /**
  873. * @}
  874. */
  875. #endif /* STM32L4xx || STM32F7*/
  876. /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
  877. * @{
  878. */
  879. /**
  880. * @}
  881. */
  882. /* Exported functions --------------------------------------------------------*/
  883. /** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
  884. * @{
  885. */
  886. #define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
  887. /**
  888. * @}
  889. */
  890. /** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
  891. * @{
  892. */
  893. #define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
  894. #define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
  895. #define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
  896. #define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish
  897. #define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish
  898. #define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish
  899. /*HASH Algorithm Selection*/
  900. #define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
  901. #define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
  902. #define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
  903. #define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
  904. #define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
  905. #define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
  906. #define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
  907. #define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY
  908. /**
  909. * @}
  910. */
  911. /** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
  912. * @{
  913. */
  914. #define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
  915. #define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
  916. #define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
  917. #define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
  918. #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
  919. #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
  920. #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
  921. #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
  922. #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
  923. #if defined(STM32L0)
  924. #else
  925. #define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
  926. #endif
  927. #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
  928. #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
  929. /**
  930. * @}
  931. */
  932. /** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
  933. * @{
  934. */
  935. #define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram
  936. #define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown
  937. #define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown
  938. #define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock
  939. #define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock
  940. #define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase
  941. #define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program
  942. /**
  943. * @}
  944. */
  945. /** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
  946. * @{
  947. */
  948. #define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
  949. #define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
  950. #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
  951. #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
  952. #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
  953. /**
  954. * @}
  955. */
  956. /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
  957. * @{
  958. */
  959. #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
  960. #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
  961. #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
  962. #define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor
  963. #define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg
  964. #define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown
  965. #define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor
  966. #define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler
  967. #define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD
  968. #define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler
  969. #define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback
  970. #define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive
  971. #define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive
  972. #define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC
  973. #define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC
  974. #define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM
  975. #define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL
  976. #define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING
  977. #define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING
  978. #define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING
  979. #define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING
  980. #define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING
  981. #define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING
  982. #define CR_OFFSET_BB PWR_CR_OFFSET_BB
  983. #define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
  984. #define DBP_BitNumber DBP_BIT_NUMBER
  985. #define PVDE_BitNumber PVDE_BIT_NUMBER
  986. #define PMODE_BitNumber PMODE_BIT_NUMBER
  987. #define EWUP_BitNumber EWUP_BIT_NUMBER
  988. #define FPDS_BitNumber FPDS_BIT_NUMBER
  989. #define ODEN_BitNumber ODEN_BIT_NUMBER
  990. #define ODSWEN_BitNumber ODSWEN_BIT_NUMBER
  991. #define MRLVDS_BitNumber MRLVDS_BIT_NUMBER
  992. #define LPLVDS_BitNumber LPLVDS_BIT_NUMBER
  993. #define BRE_BitNumber BRE_BIT_NUMBER
  994. #define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
  995. /**
  996. * @}
  997. */
  998. /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
  999. * @{
  1000. */
  1001. #define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
  1002. #define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
  1003. #define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
  1004. /**
  1005. * @}
  1006. */
  1007. /** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
  1008. * @{
  1009. */
  1010. #define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
  1011. /**
  1012. * @}
  1013. */
  1014. /** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
  1015. * @{
  1016. */
  1017. #define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt
  1018. #define HAL_TIM_DMAError TIM_DMAError
  1019. #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
  1020. #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
  1021. /**
  1022. * @}
  1023. */
  1024. /** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
  1025. * @{
  1026. */
  1027. #define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
  1028. /**
  1029. * @}
  1030. */
  1031. /** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
  1032. * @{
  1033. */
  1034. #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
  1035. /**
  1036. * @}
  1037. */
  1038. /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
  1039. * @{
  1040. */
  1041. /**
  1042. * @}
  1043. */
  1044. /* Exported macros ------------------------------------------------------------*/
  1045. /** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
  1046. * @{
  1047. */
  1048. #define AES_IT_CC CRYP_IT_CC
  1049. #define AES_IT_ERR CRYP_IT_ERR
  1050. #define AES_FLAG_CCF CRYP_FLAG_CCF
  1051. /**
  1052. * @}
  1053. */
  1054. /** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
  1055. * @{
  1056. */
  1057. #define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE
  1058. #define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH
  1059. #define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
  1060. #define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
  1061. #define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
  1062. #define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
  1063. #define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
  1064. #define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
  1065. #define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
  1066. #define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG
  1067. #define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
  1068. #define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
  1069. #define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
  1070. #define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
  1071. #define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
  1072. #define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS
  1073. #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER
  1074. #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER
  1075. /**
  1076. * @}
  1077. */
  1078. /** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
  1079. * @{
  1080. */
  1081. #define __ADC_ENABLE __HAL_ADC_ENABLE
  1082. #define __ADC_DISABLE __HAL_ADC_DISABLE
  1083. #define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS
  1084. #define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS
  1085. #define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE
  1086. #define __ADC_IS_ENABLED ADC_IS_ENABLE
  1087. #define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR
  1088. #define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED
  1089. #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
  1090. #define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR
  1091. #define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED
  1092. #define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING
  1093. #define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE
  1094. #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
  1095. #define __HAL_ADC_JSQR_RK ADC_JSQR_RK
  1096. #define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT
  1097. #define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR
  1098. #define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION
  1099. #define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE
  1100. #define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS
  1101. #define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS
  1102. #define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM
  1103. #define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT
  1104. #define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS
  1105. #define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN
  1106. #define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ
  1107. #define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET
  1108. #define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET
  1109. #define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL
  1110. #define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL
  1111. #define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET
  1112. #define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET
  1113. #define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD
  1114. #define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION
  1115. #define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
  1116. #define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
  1117. #define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER
  1118. #define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI
  1119. #define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
  1120. #define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE
  1121. #define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER
  1122. #define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER
  1123. #define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE
  1124. #define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT
  1125. #define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT
  1126. #define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL
  1127. #define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM
  1128. #define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET
  1129. #define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE
  1130. #define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE
  1131. #define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER
  1132. #define __HAL_ADC_SQR1 ADC_SQR1
  1133. #define __HAL_ADC_SMPR1 ADC_SMPR1
  1134. #define __HAL_ADC_SMPR2 ADC_SMPR2
  1135. #define __HAL_ADC_SQR3_RK ADC_SQR3_RK
  1136. #define __HAL_ADC_SQR2_RK ADC_SQR2_RK
  1137. #define __HAL_ADC_SQR1_RK ADC_SQR1_RK
  1138. #define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS
  1139. #define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS
  1140. #define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
  1141. #define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
  1142. #define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
  1143. #define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
  1144. #define __HAL_ADC_JSQR ADC_JSQR
  1145. #define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
  1146. #define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS
  1147. #define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF
  1148. #define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT
  1149. #define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS
  1150. #define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN
  1151. #define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR
  1152. #define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ
  1153. /**
  1154. * @}
  1155. */
  1156. /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
  1157. * @{
  1158. */
  1159. #define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT
  1160. #define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT
  1161. #define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT
  1162. #define IS_DAC_GENERATE_WAVE IS_DAC_WAVE
  1163. /**
  1164. * @}
  1165. */
  1166. /** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
  1167. * @{
  1168. */
  1169. #define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
  1170. #define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
  1171. #define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
  1172. #define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
  1173. #define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
  1174. #define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
  1175. #define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
  1176. #define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
  1177. #define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
  1178. #define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
  1179. #define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
  1180. #define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
  1181. #define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
  1182. #define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
  1183. #define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
  1184. #define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
  1185. #define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
  1186. #define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
  1187. #define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
  1188. #define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
  1189. #define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
  1190. #define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
  1191. #define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
  1192. #define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
  1193. #define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
  1194. #define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
  1195. #define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
  1196. #define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
  1197. #define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
  1198. #define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
  1199. #define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
  1200. #define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
  1201. #define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
  1202. #define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
  1203. #define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
  1204. #define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
  1205. #define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
  1206. #define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
  1207. #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
  1208. #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
  1209. #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
  1210. #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
  1211. #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
  1212. #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
  1213. #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
  1214. #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
  1215. #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
  1216. #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
  1217. #define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
  1218. #define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
  1219. #define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
  1220. #define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
  1221. #define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
  1222. #define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
  1223. /**
  1224. * @}
  1225. */
  1226. /** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
  1227. * @{
  1228. */
  1229. #if defined(STM32F3)
  1230. #define COMP_START __HAL_COMP_ENABLE
  1231. #define COMP_STOP __HAL_COMP_DISABLE
  1232. #define COMP_LOCK __HAL_COMP_LOCK
  1233. #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
  1234. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
  1235. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
  1236. __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
  1237. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
  1238. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
  1239. __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
  1240. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
  1241. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
  1242. __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
  1243. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
  1244. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
  1245. __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
  1246. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
  1247. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
  1248. __HAL_COMP_COMP6_EXTI_ENABLE_IT())
  1249. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
  1250. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
  1251. __HAL_COMP_COMP6_EXTI_DISABLE_IT())
  1252. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
  1253. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
  1254. __HAL_COMP_COMP6_EXTI_GET_FLAG())
  1255. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
  1256. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
  1257. __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
  1258. # endif
  1259. # if defined(STM32F302xE) || defined(STM32F302xC)
  1260. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  1261. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
  1262. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
  1263. __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
  1264. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  1265. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
  1266. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
  1267. __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
  1268. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  1269. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
  1270. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
  1271. __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
  1272. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  1273. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
  1274. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
  1275. __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
  1276. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  1277. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
  1278. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
  1279. __HAL_COMP_COMP6_EXTI_ENABLE_IT())
  1280. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  1281. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
  1282. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
  1283. __HAL_COMP_COMP6_EXTI_DISABLE_IT())
  1284. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  1285. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
  1286. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
  1287. __HAL_COMP_COMP6_EXTI_GET_FLAG())
  1288. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  1289. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
  1290. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
  1291. __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
  1292. # endif
  1293. # if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
  1294. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  1295. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
  1296. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
  1297. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
  1298. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
  1299. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
  1300. __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
  1301. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  1302. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
  1303. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
  1304. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
  1305. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
  1306. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
  1307. __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
  1308. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  1309. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
  1310. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
  1311. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
  1312. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
  1313. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
  1314. __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
  1315. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  1316. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
  1317. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
  1318. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
  1319. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
  1320. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
  1321. __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
  1322. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  1323. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
  1324. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
  1325. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
  1326. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
  1327. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
  1328. __HAL_COMP_COMP7_EXTI_ENABLE_IT())
  1329. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  1330. ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
  1331. ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
  1332. ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
  1333. ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
  1334. ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
  1335. __HAL_COMP_COMP7_EXTI_DISABLE_IT())
  1336. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  1337. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
  1338. ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
  1339. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
  1340. ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
  1341. ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
  1342. __HAL_COMP_COMP7_EXTI_GET_FLAG())
  1343. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  1344. ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
  1345. ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
  1346. ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
  1347. ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
  1348. ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
  1349. __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
  1350. # endif
  1351. # if defined(STM32F373xC) ||defined(STM32F378xx)
  1352. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  1353. __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
  1354. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  1355. __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
  1356. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  1357. __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
  1358. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  1359. __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
  1360. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  1361. __HAL_COMP_COMP2_EXTI_ENABLE_IT())
  1362. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  1363. __HAL_COMP_COMP2_EXTI_DISABLE_IT())
  1364. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  1365. __HAL_COMP_COMP2_EXTI_GET_FLAG())
  1366. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  1367. __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
  1368. # endif
  1369. #else
  1370. #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
  1371. __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
  1372. #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
  1373. __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
  1374. #define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
  1375. __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
  1376. #define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
  1377. __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
  1378. #define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
  1379. __HAL_COMP_COMP2_EXTI_ENABLE_IT())
  1380. #define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
  1381. __HAL_COMP_COMP2_EXTI_DISABLE_IT())
  1382. #define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
  1383. __HAL_COMP_COMP2_EXTI_GET_FLAG())
  1384. #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
  1385. __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
  1386. #endif
  1387. #define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
  1388. #if defined(STM32L0) || defined(STM32L4)
  1389. /* Note: On these STM32 families, the only argument of this macro */
  1390. /* is COMP_FLAG_LOCK. */
  1391. /* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
  1392. /* argument. */
  1393. #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
  1394. #endif
  1395. /**
  1396. * @}
  1397. */
  1398. #if defined(STM32L0) || defined(STM32L4)
  1399. /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
  1400. * @{
  1401. */
  1402. #define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
  1403. #define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
  1404. /**
  1405. * @}
  1406. */
  1407. #endif
  1408. /** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
  1409. * @{
  1410. */
  1411. #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
  1412. ((WAVE) == DAC_WAVE_NOISE)|| \
  1413. ((WAVE) == DAC_WAVE_TRIANGLE))
  1414. /**
  1415. * @}
  1416. */
  1417. /** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
  1418. * @{
  1419. */
  1420. #define IS_WRPAREA IS_OB_WRPAREA
  1421. #define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM
  1422. #define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
  1423. #define IS_TYPEERASE IS_FLASH_TYPEERASE
  1424. #define IS_NBSECTORS IS_FLASH_NBSECTORS
  1425. #define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE
  1426. /**
  1427. * @}
  1428. */
  1429. /** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
  1430. * @{
  1431. */
  1432. #define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
  1433. #define __HAL_I2C_GENERATE_START I2C_GENERATE_START
  1434. #define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
  1435. #define __HAL_I2C_RISE_TIME I2C_RISE_TIME
  1436. #define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
  1437. #define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
  1438. #define __HAL_I2C_SPEED I2C_SPEED
  1439. #define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE
  1440. #define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ
  1441. #define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS
  1442. #define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE
  1443. #define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ
  1444. #define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB
  1445. #define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB
  1446. #define __HAL_I2C_FREQRANGE I2C_FREQRANGE
  1447. /**
  1448. * @}
  1449. */
  1450. /** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
  1451. * @{
  1452. */
  1453. #define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
  1454. #define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
  1455. /**
  1456. * @}
  1457. */
  1458. /** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
  1459. * @{
  1460. */
  1461. #define __IRDA_DISABLE __HAL_IRDA_DISABLE
  1462. #define __IRDA_ENABLE __HAL_IRDA_ENABLE
  1463. #define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
  1464. #define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
  1465. #define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
  1466. #define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
  1467. #define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
  1468. /**
  1469. * @}
  1470. */
  1471. /** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
  1472. * @{
  1473. */
  1474. #define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS
  1475. #define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
  1476. /**
  1477. * @}
  1478. */
  1479. /** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
  1480. * @{
  1481. */
  1482. #define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT
  1483. #define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT
  1484. #define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE
  1485. /**
  1486. * @}
  1487. */
  1488. /** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
  1489. * @{
  1490. */
  1491. #define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD
  1492. #define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX
  1493. #define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX
  1494. #define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX
  1495. #define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX
  1496. #define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L
  1497. #define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H
  1498. #define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM
  1499. #define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES
  1500. #define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX
  1501. #define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT
  1502. #define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION
  1503. #define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET
  1504. /**
  1505. * @}
  1506. */
  1507. /** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
  1508. * @{
  1509. */
  1510. #define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
  1511. #define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
  1512. #define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
  1513. #define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
  1514. #define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
  1515. #define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
  1516. #define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE
  1517. #define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE
  1518. #define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
  1519. #define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
  1520. #define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
  1521. #define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
  1522. #define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine
  1523. #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
  1524. #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
  1525. #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
  1526. #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
  1527. #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
  1528. #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
  1529. #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
  1530. #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
  1531. #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
  1532. #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
  1533. #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
  1534. #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
  1535. #define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
  1536. #define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
  1537. #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
  1538. #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
  1539. #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
  1540. #define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2
  1541. #define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
  1542. #define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
  1543. #define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB
  1544. #define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB
  1545. #if defined (STM32F4)
  1546. #define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
  1547. #define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
  1548. #define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
  1549. #define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
  1550. #define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
  1551. #else
  1552. #define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG
  1553. #define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
  1554. #define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
  1555. #define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
  1556. #define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
  1557. #endif /* STM32F4 */
  1558. /**
  1559. * @}
  1560. */
  1561. /** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
  1562. * @{
  1563. */
  1564. #define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
  1565. #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
  1566. #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
  1567. #define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
  1568. #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
  1569. #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
  1570. #define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
  1571. #define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
  1572. #define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
  1573. #define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
  1574. #define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
  1575. #define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
  1576. #define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
  1577. #define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
  1578. #define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
  1579. #define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
  1580. #define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
  1581. #define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
  1582. #define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
  1583. #define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
  1584. #define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
  1585. #define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
  1586. #define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
  1587. #define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
  1588. #define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
  1589. #define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
  1590. #define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
  1591. #define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
  1592. #define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
  1593. #define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
  1594. #define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
  1595. #define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
  1596. #define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
  1597. #define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
  1598. #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
  1599. #define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
  1600. #define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
  1601. #define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
  1602. #define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
  1603. #define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
  1604. #define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
  1605. #define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
  1606. #define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
  1607. #define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
  1608. #define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
  1609. #define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
  1610. #define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
  1611. #define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
  1612. #define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
  1613. #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
  1614. #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
  1615. #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
  1616. #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
  1617. #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
  1618. #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
  1619. #define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
  1620. #define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
  1621. #define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
  1622. #define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
  1623. #define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
  1624. #define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
  1625. #define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
  1626. #define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
  1627. #define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
  1628. #define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
  1629. #define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
  1630. #define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
  1631. #define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
  1632. #define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
  1633. #define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
  1634. #define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
  1635. #define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
  1636. #define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE
  1637. #define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE
  1638. #define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET
  1639. #define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET
  1640. #define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE
  1641. #define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE
  1642. #define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
  1643. #define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
  1644. #define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
  1645. #define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
  1646. #define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
  1647. #define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
  1648. #define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
  1649. #define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
  1650. #define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
  1651. #define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
  1652. #define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
  1653. #define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
  1654. #define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
  1655. #define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
  1656. #define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
  1657. #define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
  1658. #define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
  1659. #define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
  1660. #define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE
  1661. #define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE
  1662. #define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET
  1663. #define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET
  1664. #define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
  1665. #define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
  1666. #define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
  1667. #define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
  1668. #define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
  1669. #define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
  1670. #define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
  1671. #define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
  1672. #define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
  1673. #define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
  1674. #define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
  1675. #define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
  1676. #define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
  1677. #define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
  1678. #define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
  1679. #define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
  1680. #define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
  1681. #define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
  1682. #define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
  1683. #define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
  1684. #define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
  1685. #define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
  1686. #define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
  1687. #define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
  1688. #define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
  1689. #define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
  1690. #define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
  1691. #define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
  1692. #define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
  1693. #define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
  1694. #define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
  1695. #define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
  1696. #define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
  1697. #define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
  1698. #define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE
  1699. #define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE
  1700. #define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET
  1701. #define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET
  1702. #define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
  1703. #define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
  1704. #define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
  1705. #define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
  1706. #define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
  1707. #define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
  1708. #define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
  1709. #define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
  1710. #define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
  1711. #define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
  1712. #define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
  1713. #define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
  1714. #define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
  1715. #define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
  1716. #define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
  1717. #define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
  1718. #define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
  1719. #define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
  1720. #define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
  1721. #define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
  1722. #define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
  1723. #define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
  1724. #define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
  1725. #define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
  1726. #define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
  1727. #define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
  1728. #define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
  1729. #define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
  1730. #define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
  1731. #define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
  1732. #define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
  1733. #define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
  1734. #define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
  1735. #define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
  1736. #define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
  1737. #define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
  1738. #define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
  1739. #define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
  1740. #define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
  1741. #define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
  1742. #define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
  1743. #define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
  1744. #define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
  1745. #define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
  1746. #define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
  1747. #define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
  1748. #define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
  1749. #define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
  1750. #define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
  1751. #define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
  1752. #define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
  1753. #define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
  1754. #define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
  1755. #define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
  1756. #define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
  1757. #define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
  1758. #define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
  1759. #define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
  1760. #define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
  1761. #define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
  1762. #define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
  1763. #define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
  1764. #define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
  1765. #define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
  1766. #define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
  1767. #define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
  1768. #define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
  1769. #define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
  1770. #define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
  1771. #define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
  1772. #define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
  1773. #define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
  1774. #define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
  1775. #define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
  1776. #define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
  1777. #define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
  1778. #define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
  1779. #define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
  1780. #define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
  1781. #define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
  1782. #define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
  1783. #define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
  1784. #define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
  1785. #define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
  1786. #define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
  1787. #define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
  1788. #define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
  1789. #define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
  1790. #define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
  1791. #define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
  1792. #define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
  1793. #define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
  1794. #define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
  1795. #define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
  1796. #define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
  1797. #define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
  1798. #define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
  1799. #define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
  1800. #define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
  1801. #define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
  1802. #define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
  1803. #define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
  1804. #define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
  1805. #define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
  1806. #define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
  1807. #define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
  1808. #define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
  1809. #define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
  1810. #define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
  1811. #define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
  1812. #define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
  1813. #define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
  1814. #define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
  1815. #define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
  1816. #define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
  1817. #define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
  1818. #define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
  1819. #define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
  1820. #define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
  1821. #define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
  1822. #define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
  1823. #define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
  1824. #define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
  1825. #define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
  1826. #define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
  1827. #define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
  1828. #define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
  1829. #define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
  1830. #define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
  1831. #define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
  1832. #define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
  1833. #define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
  1834. #define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
  1835. #define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
  1836. #define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
  1837. #define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
  1838. #define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
  1839. #define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
  1840. #define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
  1841. #define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
  1842. #define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
  1843. #define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
  1844. #define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
  1845. #define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
  1846. #define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
  1847. #define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
  1848. #define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
  1849. #define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
  1850. #define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
  1851. #define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
  1852. #define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
  1853. #define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
  1854. #define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
  1855. #define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
  1856. #define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
  1857. #define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
  1858. #define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
  1859. #define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
  1860. #define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
  1861. #define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
  1862. #define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
  1863. #define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
  1864. #define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
  1865. #define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
  1866. #define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
  1867. #define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
  1868. #define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
  1869. #define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
  1870. #define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
  1871. #define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
  1872. #define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
  1873. #define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
  1874. #define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
  1875. #define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
  1876. #define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
  1877. #define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
  1878. #define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
  1879. #define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
  1880. #define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
  1881. #define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
  1882. #define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
  1883. #define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
  1884. #define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
  1885. #define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
  1886. #define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
  1887. #define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
  1888. #define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
  1889. #define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
  1890. #define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
  1891. #define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
  1892. #define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
  1893. #define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
  1894. #define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
  1895. #define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
  1896. #define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
  1897. #define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
  1898. #define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
  1899. #define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
  1900. #define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
  1901. #define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
  1902. #define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
  1903. #define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
  1904. #define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
  1905. #define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
  1906. #define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
  1907. #define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
  1908. #define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
  1909. #define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
  1910. #define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
  1911. #define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
  1912. #define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
  1913. #define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
  1914. #define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
  1915. #define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
  1916. #define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
  1917. #define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
  1918. #define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
  1919. #define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
  1920. #define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
  1921. #define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
  1922. #define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
  1923. #define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
  1924. #define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
  1925. #define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
  1926. #define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
  1927. #define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
  1928. #define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
  1929. #define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
  1930. #define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
  1931. #define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
  1932. #define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
  1933. #define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
  1934. #define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
  1935. #define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
  1936. #define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
  1937. #define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
  1938. #define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
  1939. #define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
  1940. #define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
  1941. #define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
  1942. #define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
  1943. #define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
  1944. #define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
  1945. #define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
  1946. #define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
  1947. #define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
  1948. #define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
  1949. #define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
  1950. #define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
  1951. #define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
  1952. #define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
  1953. #define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
  1954. #define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
  1955. #define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
  1956. #define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
  1957. #define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
  1958. #define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
  1959. #define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
  1960. #define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
  1961. #define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
  1962. #define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
  1963. #define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
  1964. #define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
  1965. #define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
  1966. #define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
  1967. #define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
  1968. #define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
  1969. #define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
  1970. #define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
  1971. #define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
  1972. #define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
  1973. #define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
  1974. #define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
  1975. #define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
  1976. #define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
  1977. #define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
  1978. #define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
  1979. #define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
  1980. #define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
  1981. #define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
  1982. #define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
  1983. #define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
  1984. #define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
  1985. #define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
  1986. #define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
  1987. #define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
  1988. #define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
  1989. #define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
  1990. #define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
  1991. #define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
  1992. #define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
  1993. #define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
  1994. #define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
  1995. #define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
  1996. #define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
  1997. #define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
  1998. #define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
  1999. #define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
  2000. #define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
  2001. #define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
  2002. #define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
  2003. #define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
  2004. #define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
  2005. #define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
  2006. #define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
  2007. #define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
  2008. #define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
  2009. #define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
  2010. #define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
  2011. #define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
  2012. #define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
  2013. #define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
  2014. #define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
  2015. #define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
  2016. #define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
  2017. #define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
  2018. #define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
  2019. #define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
  2020. #define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
  2021. #define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
  2022. #define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
  2023. #define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
  2024. #define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
  2025. #define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
  2026. #define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
  2027. #define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
  2028. #define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
  2029. #define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
  2030. #define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
  2031. #define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
  2032. #define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
  2033. #define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
  2034. #define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE
  2035. #define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE
  2036. #define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET
  2037. #define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE
  2038. #define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE
  2039. #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
  2040. #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
  2041. #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
  2042. #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
  2043. #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
  2044. #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
  2045. #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
  2046. #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
  2047. #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
  2048. #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
  2049. #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
  2050. #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
  2051. #define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET
  2052. #define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
  2053. #define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
  2054. #define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE
  2055. #define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE
  2056. #define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET
  2057. #define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET
  2058. #define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
  2059. #define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
  2060. #define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
  2061. #define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
  2062. #define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
  2063. #define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
  2064. #define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
  2065. #define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
  2066. #define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
  2067. #define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
  2068. #define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
  2069. #define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
  2070. #define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
  2071. #define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
  2072. #define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
  2073. #define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
  2074. #define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
  2075. #define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
  2076. #define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
  2077. #define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
  2078. #define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
  2079. #define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
  2080. #define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
  2081. #define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
  2082. #define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
  2083. #define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
  2084. #define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
  2085. #define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
  2086. #define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
  2087. #define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
  2088. #define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
  2089. #define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
  2090. #define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
  2091. #define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
  2092. #define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
  2093. #define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
  2094. #define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
  2095. #define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
  2096. #define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
  2097. #define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
  2098. #define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
  2099. #define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
  2100. #define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
  2101. #define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
  2102. #define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
  2103. #define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
  2104. #define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
  2105. #define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
  2106. #define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
  2107. #define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
  2108. #define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
  2109. #define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
  2110. #define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
  2111. #define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
  2112. #define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
  2113. #define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
  2114. #define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
  2115. #define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
  2116. #define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
  2117. #define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
  2118. #define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
  2119. #define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
  2120. #define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
  2121. #define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
  2122. #define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
  2123. #define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
  2124. #define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
  2125. #define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
  2126. #define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
  2127. #define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
  2128. #define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
  2129. #define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
  2130. #define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
  2131. #define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
  2132. #define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
  2133. #define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
  2134. #define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
  2135. #define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
  2136. #define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
  2137. #define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
  2138. #define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
  2139. #define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
  2140. #define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
  2141. #define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
  2142. #define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
  2143. #define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
  2144. #define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
  2145. #define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
  2146. #define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
  2147. #define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
  2148. #define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
  2149. #define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
  2150. #define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
  2151. #define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
  2152. #define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
  2153. #define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
  2154. #define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
  2155. #define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
  2156. #define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
  2157. #define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
  2158. #define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
  2159. #define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
  2160. #define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
  2161. #define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
  2162. #define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
  2163. #define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
  2164. #define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
  2165. #define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
  2166. #define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
  2167. #define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
  2168. #define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
  2169. #define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
  2170. #define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
  2171. #define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
  2172. #define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
  2173. #define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
  2174. #define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
  2175. #define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
  2176. #define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
  2177. #define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
  2178. #define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
  2179. #define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
  2180. #define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
  2181. #define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
  2182. #define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
  2183. #define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
  2184. #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
  2185. #define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
  2186. #define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
  2187. #define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
  2188. #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
  2189. #define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
  2190. #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
  2191. #define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
  2192. #define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
  2193. #define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
  2194. #define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
  2195. #define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
  2196. #define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
  2197. #define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
  2198. #define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
  2199. #define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
  2200. #define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
  2201. #define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
  2202. #define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
  2203. #define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
  2204. #define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
  2205. #define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
  2206. #define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
  2207. #define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
  2208. #define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
  2209. #define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
  2210. #define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
  2211. #define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
  2212. #define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
  2213. #define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET
  2214. #define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
  2215. #define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
  2216. /* alias define maintained for legacy */
  2217. #define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET
  2218. #define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET
  2219. #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
  2220. #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
  2221. #define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
  2222. #define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
  2223. #define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
  2224. #define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
  2225. #define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
  2226. #define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
  2227. #define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
  2228. #define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE
  2229. #define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE
  2230. #define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE
  2231. #define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE
  2232. #define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE
  2233. #define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE
  2234. #define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE
  2235. #define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE
  2236. #define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE
  2237. #define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE
  2238. #define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE
  2239. #define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE
  2240. #define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE
  2241. #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
  2242. #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
  2243. #define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
  2244. #define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
  2245. #define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
  2246. #define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
  2247. #define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
  2248. #define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
  2249. #define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
  2250. #define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET
  2251. #define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET
  2252. #define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET
  2253. #define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET
  2254. #define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET
  2255. #define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET
  2256. #define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET
  2257. #define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET
  2258. #define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET
  2259. #define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET
  2260. #define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET
  2261. #define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET
  2262. #define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET
  2263. #define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED
  2264. #define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED
  2265. #define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
  2266. #define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
  2267. #define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED
  2268. #define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED
  2269. #define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED
  2270. #define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED
  2271. #define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED
  2272. #define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED
  2273. #define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED
  2274. #define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED
  2275. #define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED
  2276. #define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED
  2277. #define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED
  2278. #define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED
  2279. #define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED
  2280. #define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED
  2281. #define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED
  2282. #define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED
  2283. #define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED
  2284. #define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED
  2285. #define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED
  2286. #define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED
  2287. #define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED
  2288. #define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED
  2289. #define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED
  2290. #define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED
  2291. #define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED
  2292. #define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED
  2293. #define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED
  2294. #define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED
  2295. #define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED
  2296. #define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED
  2297. #define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED
  2298. #define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED
  2299. #define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED
  2300. #define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED
  2301. #define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED
  2302. #define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED
  2303. #define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED
  2304. #define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED
  2305. #define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED
  2306. #define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED
  2307. #define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED
  2308. #define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED
  2309. #define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED
  2310. #define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED
  2311. #define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED
  2312. #define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED
  2313. #define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED
  2314. #define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED
  2315. #define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED
  2316. #define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED
  2317. #define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED
  2318. #define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED
  2319. #define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED
  2320. #define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED
  2321. #define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED
  2322. #define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED
  2323. #define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED
  2324. #define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED
  2325. #define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED
  2326. #define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED
  2327. #define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED
  2328. #define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED
  2329. #define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED
  2330. #define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED
  2331. #define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED
  2332. #define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED
  2333. #define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED
  2334. #define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED
  2335. #define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED
  2336. #define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED
  2337. #define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED
  2338. #define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED
  2339. #define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED
  2340. #define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED
  2341. #define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED
  2342. #define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED
  2343. #define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED
  2344. #define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED
  2345. #define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED
  2346. #define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED
  2347. #define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED
  2348. #define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED
  2349. #define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED
  2350. #define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED
  2351. #define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED
  2352. #define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED
  2353. #define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED
  2354. #define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED
  2355. #define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED
  2356. #define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED
  2357. #define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED
  2358. #define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED
  2359. #define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED
  2360. #define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED
  2361. #define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED
  2362. #define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED
  2363. #define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED
  2364. #define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED
  2365. #define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED
  2366. #define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED
  2367. #define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED
  2368. #define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED
  2369. #define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED
  2370. #define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED
  2371. #define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED
  2372. #define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED
  2373. #define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED
  2374. #define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED
  2375. #define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED
  2376. #define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED
  2377. #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
  2378. #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
  2379. #if defined(STM32F4)
  2380. #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
  2381. #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
  2382. #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
  2383. #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
  2384. #define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
  2385. #define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
  2386. #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED
  2387. #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED
  2388. #define Sdmmc1ClockSelection SdioClockSelection
  2389. #define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO
  2390. #define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48
  2391. #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK
  2392. #define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG
  2393. #define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE
  2394. #endif
  2395. #if defined(STM32F7) || defined(STM32L4)
  2396. #define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET
  2397. #define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET
  2398. #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
  2399. #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
  2400. #define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE
  2401. #define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE
  2402. #define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED
  2403. #define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED
  2404. #define SdioClockSelection Sdmmc1ClockSelection
  2405. #define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
  2406. #define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
  2407. #define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
  2408. #endif
  2409. #if defined(STM32F7)
  2410. #define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
  2411. #define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
  2412. #endif
  2413. #define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
  2414. #define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
  2415. #define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE
  2416. #define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE
  2417. #define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE
  2418. #define IS_RCC_SYSCLK_DIV IS_RCC_HCLK
  2419. #define IS_RCC_HCLK_DIV IS_RCC_PCLK
  2420. #define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK
  2421. #define RCC_IT_HSI14 RCC_IT_HSI14RDY
  2422. #define RCC_IT_CSSLSE RCC_IT_LSECSS
  2423. #define RCC_IT_CSSHSE RCC_IT_CSS
  2424. #define RCC_PLLMUL_3 RCC_PLL_MUL3
  2425. #define RCC_PLLMUL_4 RCC_PLL_MUL4
  2426. #define RCC_PLLMUL_6 RCC_PLL_MUL6
  2427. #define RCC_PLLMUL_8 RCC_PLL_MUL8
  2428. #define RCC_PLLMUL_12 RCC_PLL_MUL12
  2429. #define RCC_PLLMUL_16 RCC_PLL_MUL16
  2430. #define RCC_PLLMUL_24 RCC_PLL_MUL24
  2431. #define RCC_PLLMUL_32 RCC_PLL_MUL32
  2432. #define RCC_PLLMUL_48 RCC_PLL_MUL48
  2433. #define RCC_PLLDIV_2 RCC_PLL_DIV2
  2434. #define RCC_PLLDIV_3 RCC_PLL_DIV3
  2435. #define RCC_PLLDIV_4 RCC_PLL_DIV4
  2436. #define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE
  2437. #define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG
  2438. #define RCC_MCO_NODIV RCC_MCODIV_1
  2439. #define RCC_MCO_DIV1 RCC_MCODIV_1
  2440. #define RCC_MCO_DIV2 RCC_MCODIV_2
  2441. #define RCC_MCO_DIV4 RCC_MCODIV_4
  2442. #define RCC_MCO_DIV8 RCC_MCODIV_8
  2443. #define RCC_MCO_DIV16 RCC_MCODIV_16
  2444. #define RCC_MCO_DIV32 RCC_MCODIV_32
  2445. #define RCC_MCO_DIV64 RCC_MCODIV_64
  2446. #define RCC_MCO_DIV128 RCC_MCODIV_128
  2447. #define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK
  2448. #define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI
  2449. #define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE
  2450. #define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK
  2451. #define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI
  2452. #define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14
  2453. #define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48
  2454. #define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE
  2455. #define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK
  2456. #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
  2457. #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
  2458. #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
  2459. #define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
  2460. #define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
  2461. #define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI
  2462. #define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL
  2463. #define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL
  2464. #define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5
  2465. #define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2
  2466. #define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3
  2467. #define HSION_BitNumber RCC_HSION_BIT_NUMBER
  2468. #define HSION_BITNUMBER RCC_HSION_BIT_NUMBER
  2469. #define HSEON_BitNumber RCC_HSEON_BIT_NUMBER
  2470. #define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER
  2471. #define MSION_BITNUMBER RCC_MSION_BIT_NUMBER
  2472. #define CSSON_BitNumber RCC_CSSON_BIT_NUMBER
  2473. #define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER
  2474. #define PLLON_BitNumber RCC_PLLON_BIT_NUMBER
  2475. #define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER
  2476. #define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER
  2477. #define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER
  2478. #define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER
  2479. #define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER
  2480. #define BDRST_BitNumber RCC_BDRST_BIT_NUMBER
  2481. #define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER
  2482. #define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER
  2483. #define LSION_BitNumber RCC_LSION_BIT_NUMBER
  2484. #define LSION_BITNUMBER RCC_LSION_BIT_NUMBER
  2485. #define LSEON_BitNumber RCC_LSEON_BIT_NUMBER
  2486. #define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER
  2487. #define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER
  2488. #define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER
  2489. #define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER
  2490. #define RMVF_BitNumber RCC_RMVF_BIT_NUMBER
  2491. #define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER
  2492. #define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
  2493. #define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS
  2494. #define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS
  2495. #define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS
  2496. #define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS
  2497. #define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE
  2498. #define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE
  2499. #define CR_HSION_BB RCC_CR_HSION_BB
  2500. #define CR_CSSON_BB RCC_CR_CSSON_BB
  2501. #define CR_PLLON_BB RCC_CR_PLLON_BB
  2502. #define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB
  2503. #define CR_MSION_BB RCC_CR_MSION_BB
  2504. #define CSR_LSION_BB RCC_CSR_LSION_BB
  2505. #define CSR_LSEON_BB RCC_CSR_LSEON_BB
  2506. #define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB
  2507. #define CSR_RTCEN_BB RCC_CSR_RTCEN_BB
  2508. #define CSR_RTCRST_BB RCC_CSR_RTCRST_BB
  2509. #define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB
  2510. #define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB
  2511. #define BDCR_BDRST_BB RCC_BDCR_BDRST_BB
  2512. #define CR_HSEON_BB RCC_CR_HSEON_BB
  2513. #define CSR_RMVF_BB RCC_CSR_RMVF_BB
  2514. #define CR_PLLSAION_BB RCC_CR_PLLSAION_BB
  2515. #define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB
  2516. #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
  2517. #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
  2518. #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
  2519. #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
  2520. #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
  2521. #define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
  2522. #define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
  2523. #define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
  2524. #define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
  2525. #define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
  2526. #define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
  2527. #define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
  2528. #define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
  2529. #define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
  2530. #define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
  2531. #define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
  2532. #define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
  2533. #define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
  2534. #define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
  2535. #define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
  2536. #define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
  2537. #define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
  2538. #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
  2539. #define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
  2540. #define DfsdmClockSelection Dfsdm1ClockSelection
  2541. #define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
  2542. #define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
  2543. #define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
  2544. #define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
  2545. #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
  2546. #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
  2547. #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
  2548. #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
  2549. #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
  2550. /**
  2551. * @}
  2552. */
  2553. /** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
  2554. * @{
  2555. */
  2556. #define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
  2557. /**
  2558. * @}
  2559. */
  2560. /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
  2561. * @{
  2562. */
  2563. #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
  2564. #define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
  2565. #define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
  2566. #if defined (STM32F1)
  2567. #define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
  2568. #define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT()
  2569. #define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT()
  2570. #define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG()
  2571. #define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
  2572. #else
  2573. #define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
  2574. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
  2575. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
  2576. #define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
  2577. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
  2578. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
  2579. #define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
  2580. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
  2581. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
  2582. #define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
  2583. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
  2584. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
  2585. #define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
  2586. (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \
  2587. __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
  2588. #endif /* STM32F1 */
  2589. #define IS_ALARM IS_RTC_ALARM
  2590. #define IS_ALARM_MASK IS_RTC_ALARM_MASK
  2591. #define IS_TAMPER IS_RTC_TAMPER
  2592. #define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
  2593. #define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
  2594. #define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
  2595. #define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
  2596. #define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
  2597. #define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE
  2598. #define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ
  2599. #define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
  2600. #define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER
  2601. #define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK
  2602. #define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER
  2603. #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
  2604. #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
  2605. /**
  2606. * @}
  2607. */
  2608. /** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
  2609. * @{
  2610. */
  2611. #define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
  2612. #define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
  2613. #if defined(STM32F4)
  2614. #define SD_SDMMC_DISABLED SD_SDIO_DISABLED
  2615. #define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
  2616. #define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
  2617. #define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
  2618. #define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
  2619. #define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
  2620. #define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
  2621. #define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
  2622. #define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
  2623. #define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
  2624. #define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
  2625. #define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
  2626. #define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
  2627. #define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
  2628. #define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
  2629. #define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
  2630. #define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
  2631. #define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
  2632. #define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
  2633. #define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
  2634. /* alias CMSIS */
  2635. #define SDMMC1_IRQn SDIO_IRQn
  2636. #define SDMMC1_IRQHandler SDIO_IRQHandler
  2637. #endif
  2638. #if defined(STM32F7) || defined(STM32L4)
  2639. #define SD_SDIO_DISABLED SD_SDMMC_DISABLED
  2640. #define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
  2641. #define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
  2642. #define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
  2643. #define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
  2644. #define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
  2645. #define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED
  2646. #define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE
  2647. #define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE
  2648. #define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE
  2649. #define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE
  2650. #define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT
  2651. #define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT
  2652. #define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG
  2653. #define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG
  2654. #define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT
  2655. #define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT
  2656. #define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS
  2657. #define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT
  2658. #define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND
  2659. /* alias CMSIS for compatibilities */
  2660. #define SDIO_IRQn SDMMC1_IRQn
  2661. #define SDIO_IRQHandler SDMMC1_IRQHandler
  2662. #endif
  2663. #if defined(STM32F7) || defined(STM32F4)
  2664. #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
  2665. #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
  2666. #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
  2667. #define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
  2668. #endif
  2669. /**
  2670. * @}
  2671. */
  2672. /** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
  2673. * @{
  2674. */
  2675. #define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT
  2676. #define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT
  2677. #define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE
  2678. #define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE
  2679. #define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE
  2680. #define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
  2681. #define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
  2682. #define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
  2683. #define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
  2684. /**
  2685. * @}
  2686. */
  2687. /** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
  2688. * @{
  2689. */
  2690. #define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1
  2691. #define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2
  2692. #define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START
  2693. #define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH
  2694. #define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR
  2695. #define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE
  2696. #define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE
  2697. #define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED
  2698. /**
  2699. * @}
  2700. */
  2701. /** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
  2702. * @{
  2703. */
  2704. #define __HAL_SPI_1LINE_TX SPI_1LINE_TX
  2705. #define __HAL_SPI_1LINE_RX SPI_1LINE_RX
  2706. #define __HAL_SPI_RESET_CRC SPI_RESET_CRC
  2707. /**
  2708. * @}
  2709. */
  2710. /** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
  2711. * @{
  2712. */
  2713. #define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
  2714. #define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION
  2715. #define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE
  2716. #define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION
  2717. #define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
  2718. #define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
  2719. #define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
  2720. /**
  2721. * @}
  2722. */
  2723. /** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
  2724. * @{
  2725. */
  2726. #define __USART_ENABLE_IT __HAL_USART_ENABLE_IT
  2727. #define __USART_DISABLE_IT __HAL_USART_DISABLE_IT
  2728. #define __USART_ENABLE __HAL_USART_ENABLE
  2729. #define __USART_DISABLE __HAL_USART_DISABLE
  2730. #define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
  2731. #define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE
  2732. /**
  2733. * @}
  2734. */
  2735. /** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
  2736. * @{
  2737. */
  2738. #define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE
  2739. #define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
  2740. #define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
  2741. #define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
  2742. #define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE
  2743. #define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
  2744. #define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
  2745. #define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
  2746. #define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE
  2747. #define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT
  2748. #define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT
  2749. #define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG
  2750. #define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
  2751. #define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
  2752. #define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
  2753. #define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
  2754. #define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
  2755. #define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
  2756. #define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
  2757. #define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
  2758. #define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
  2759. #define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
  2760. #define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
  2761. #define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
  2762. #define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
  2763. #define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
  2764. #define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
  2765. #define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
  2766. #define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
  2767. #define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
  2768. #define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
  2769. #define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
  2770. #define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup
  2771. #define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup
  2772. #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo
  2773. #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo
  2774. /**
  2775. * @}
  2776. */
  2777. /** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
  2778. * @{
  2779. */
  2780. #define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE
  2781. #define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
  2782. #define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
  2783. #define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT
  2784. #define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE
  2785. #define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN
  2786. #define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER
  2787. #define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER
  2788. #define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER
  2789. #define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD
  2790. #define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD
  2791. #define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION
  2792. #define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION
  2793. #define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER
  2794. #define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER
  2795. #define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
  2796. #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
  2797. #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
  2798. /**
  2799. * @}
  2800. */
  2801. /** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
  2802. * @{
  2803. */
  2804. #define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
  2805. #define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
  2806. #define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
  2807. #define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
  2808. #define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
  2809. #define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
  2810. #define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
  2811. #define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
  2812. #define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
  2813. #define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
  2814. /**
  2815. * @}
  2816. */
  2817. /** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
  2818. * @{
  2819. */
  2820. #define __HAL_LTDC_LAYER LTDC_LAYER
  2821. /**
  2822. * @}
  2823. */
  2824. /** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
  2825. * @{
  2826. */
  2827. #define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE
  2828. #define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE
  2829. #define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
  2830. #define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
  2831. #define SAI_STREOMODE SAI_STEREOMODE
  2832. #define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
  2833. #define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
  2834. #define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
  2835. #define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
  2836. #define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
  2837. #define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
  2838. #define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
  2839. #define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
  2840. #define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
  2841. /**
  2842. * @}
  2843. */
  2844. /** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
  2845. * @{
  2846. */
  2847. /**
  2848. * @}
  2849. */
  2850. #ifdef __cplusplus
  2851. }
  2852. #endif
  2853. #endif /* ___STM32_HAL_LEGACY */
  2854. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/