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stm32lib/CMSIS/STM32F0xx/Source/Templates/gcc/startup_stm32f070x6.s

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  1. /**

  2.   ******************************************************************************

  3.   * @file      startup_stm32f070x6.s

  4.   * @author    MCD Application Team

  5.   * @brief     STM32F070x4/STM32F070x6 devices vector table for GCC toolchain.

  6.   *            This module performs:

  7.   *                - Set the initial SP

  8.   *                - Set the initial PC == Reset_Handler,

  9.   *                - Set the vector table entries with the exceptions ISR address

  10.   *                - Branches to main in the C library (which eventually

  11.   *                  calls main()).

  12.   *            After Reset the Cortex-M0 processor is in Thread mode,

  13.   *            priority is Privileged, and the Stack is set to Main.

  14.   ******************************************************************************

  15.   *

  16.   * Redistribution and use in source and binary forms, with or without modification,

  17.   * are permitted provided that the following conditions are met:

  18.   *   1. Redistributions of source code must retain the above copyright notice,

  19.   *      this list of conditions and the following disclaimer.

  20.   *   2. Redistributions in binary form must reproduce the above copyright notice,

  21.   *      this list of conditions and the following disclaimer in the documentation

  22.   *      and/or other materials provided with the distribution.

  23.   *   3. Neither the name of STMicroelectronics nor the names of its contributors

  24.   *      may be used to endorse or promote products derived from this software

  25.   *      without specific prior written permission.

  26.   *

  27.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  28.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  29.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  30.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  31.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  32.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  33.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  34.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  35.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  36.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  37.   *

  38.   ******************************************************************************

  39.   */

  40. 

  41.   .syntax unified

  42.   .cpu cortex-m0

  43.   .fpu softvfp

  44.   .thumb

  45. 

  46. .global g_pfnVectors

  47. .global Default_Handler

  48. 

  49. /* start address for the initialization values of the .data section.

  50. defined in linker script */

  51. .word _sidata

  52. /* start address for the .data section. defined in linker script */

  53. .word _sdata

  54. /* end address for the .data section. defined in linker script */

  55. .word _edata

  56. /* start address for the .bss section. defined in linker script */

  57. .word _sbss

  58. /* end address for the .bss section. defined in linker script */

  59. .word _ebss

  60. 

  61. /**

  62.  * @brief  This is the code that gets called when the processor first

  63.  *          starts execution following a reset event. Only the absolutely

  64.  *          necessary set is performed, after which the application

  65.  *          supplied main() routine is called.

  66.  * @param  None

  67.  * @retval : None

  68. */

  69. 

  70.   .section .text.Reset_Handler

  71.   .weak Reset_Handler

  72.   .type Reset_Handler, %function

  73. Reset_Handler:

  74.   ldr   r0, =_estack

  75.   mov   sp, r0          /* set stack pointer */

  76. 

  77. /*Check if boot space corresponds to test memory*/

  78. 

  79.     LDR R0,=0x00000004

  80.     LDR R1, [R0]

  81.     LSRS R1, R1, #24

  82.     LDR R2,=0x1F

  83.     CMP R1, R2

  84.     BNE ApplicationStart

  85. 

  86.  /*SYSCFG clock enable*/

  87. 

  88.     LDR R0,=0x40021018

  89.     LDR R1,=0x00000001

  90.     STR R1, [R0]

  91. 

  92. /*Set CFGR1 register with flash memory remap at address 0*/

  93.     LDR R0,=0x40010000

  94.     LDR R1,=0x00000000

  95.     STR R1, [R0]

  96. 

  97. ApplicationStart:

  98. /* Copy the data segment initializers from flash to SRAM */

  99.   ldr r0, =_sdata

  100.   ldr r1, =_edata

  101.   ldr r2, =_sidata

  102.   movs r3, #0

  103.   b LoopCopyDataInit

  104. 

  105. CopyDataInit:

  106.   ldr r4, [r2, r3]

  107.   str r4, [r0, r3]

  108.   adds r3, r3, #4

  109. 

  110. LoopCopyDataInit:

  111.   adds r4, r0, r3

  112.   cmp r4, r1

  113.   bcc CopyDataInit

  114. 

  115. /* Zero fill the bss segment. */

  116.   ldr r2, =_sbss

  117.   ldr r4, =_ebss

  118.   movs r3, #0

  119.   b LoopFillZerobss

  120. 

  121. FillZerobss:

  122.   str  r3, [r2]

  123.   adds r2, r2, #4

  124. 

  125. LoopFillZerobss:

  126.   cmp r2, r4

  127.   bcc FillZerobss

  128. 

  129. /* Call the clock system intitialization function.*/

  130.   bl  SystemInit

  131. /* Call static constructors */

  132.   bl __libc_init_array

  133. /* Call the application's entry point.*/

  134.   bl main

  135. 

  136. LoopForever:

  137.     b LoopForever

  138. 

  139. 

  140. .size Reset_Handler, .-Reset_Handler

  141. 

  142. /**

  143.  * @brief  This is the code that gets called when the processor receives an

  144.  *         unexpected interrupt.  This simply enters an infinite loop, preserving

  145.  *         the system state for examination by a debugger.

  146.  *

  147.  * @param  None

  148.  * @retval : None

  149. */

  150.     .section .text.Default_Handler,"ax",%progbits

  151. Default_Handler:

  152. Infinite_Loop:

  153.   b Infinite_Loop

  154.   .size Default_Handler, .-Default_Handler

  155. /******************************************************************************

  156. *

  157. * The minimal vector table for a Cortex M0.  Note that the proper constructs

  158. * must be placed on this to ensure that it ends up at physical address

  159. * 0x0000.0000.

  160. *

  161. ******************************************************************************/

  162.    .section .isr_vector,"a",%progbits

  163.   .type g_pfnVectors, %object

  164.   .size g_pfnVectors, .-g_pfnVectors

  165. 

  166. 

  167. g_pfnVectors:

  168.   .word  _estack

  169.   .word  Reset_Handler

  170.   .word  NMI_Handler

  171.   .word  HardFault_Handler

  172.   .word  0

  173.   .word  0

  174.   .word  0

  175.   .word  0

  176.   .word  0

  177.   .word  0

  178.   .word  0

  179.   .word  SVC_Handler

  180.   .word  0

  181.   .word  0

  182.   .word  PendSV_Handler

  183.   .word  SysTick_Handler

  184.   .word  WWDG_IRQHandler                   /* Window WatchDog              */

  185.   .word  0                                 /* Reserved                     */

  186.   .word  RTC_IRQHandler                    /* RTC through the EXTI line    */

  187.   .word  FLASH_IRQHandler                  /* FLASH                        */

  188.   .word  RCC_IRQHandler                    /* RCC                          */

  189.   .word  EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */

  190.   .word  EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */

  191.   .word  EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */

  192.   .word  0                                 /* Reserved                     */

  193.   .word  DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */

  194.   .word  DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */

  195.   .word  DMA1_Channel4_5_IRQHandler        /* DMA1 Channel 4 and Channel 5 */

  196.   .word  ADC1_IRQHandler                   /* ADC1                         */

  197.   .word  TIM1_BRK_UP_TRG_COM_IRQHandler    /* TIM1 Break, Update, Trigger and Commutation */

  198.   .word  TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */

  199.   .word  0                                 /* Reserved                     */

  200.   .word  TIM3_IRQHandler                   /* TIM3                         */

  201.   .word  0                                 /* Reserved                     */

  202.   .word  0                                 /* Reserved                     */

  203.   .word  TIM14_IRQHandler                  /* TIM14                        */

  204.   .word  0                                 /* Reserved                     */

  205.   .word  TIM16_IRQHandler                  /* TIM16                        */

  206.   .word  TIM17_IRQHandler                  /* TIM17                        */

  207.   .word  I2C1_IRQHandler                   /* I2C1                         */

  208.   .word  0                                 /* Reserved                     */

  209.   .word  SPI1_IRQHandler                   /* SPI1                         */

  210.   .word  0                                 /* Reserved                     */

  211.   .word  USART1_IRQHandler                 /* USART1                       */

  212.   .word  USART2_IRQHandler                 /* USART2                       */

  213.   .word  0                                 /* Reserved                     */

  214.   .word  0                                 /* Reserved                     */

  215.   .word  USB_IRQHandler                    /* USB                          */

  216. 

  217. /*******************************************************************************

  218. *

  219. * Provide weak aliases for each Exception handler to the Default_Handler.

  220. * As they are weak aliases, any function with the same name will override

  221. * this definition.

  222. *

  223. *******************************************************************************/

  224. 

  225.   .weak      NMI_Handler

  226.   .thumb_set NMI_Handler,Default_Handler

  227. 

  228.   .weak      HardFault_Handler

  229.   .thumb_set HardFault_Handler,Default_Handler

  230. 

  231.   .weak      SVC_Handler

  232.   .thumb_set SVC_Handler,Default_Handler

  233. 

  234.   .weak      PendSV_Handler

  235.   .thumb_set PendSV_Handler,Default_Handler

  236. 

  237.   .weak      SysTick_Handler

  238.   .thumb_set SysTick_Handler,Default_Handler

  239. 

  240.   .weak      WWDG_IRQHandler

  241.   .thumb_set WWDG_IRQHandler,Default_Handler

  242. 

  243.   .weak      RTC_IRQHandler

  244.   .thumb_set RTC_IRQHandler,Default_Handler

  245. 

  246.   .weak      FLASH_IRQHandler

  247.   .thumb_set FLASH_IRQHandler,Default_Handler

  248. 

  249.   .weak      RCC_IRQHandler

  250.   .thumb_set RCC_IRQHandler,Default_Handler

  251. 

  252.   .weak      EXTI0_1_IRQHandler

  253.   .thumb_set EXTI0_1_IRQHandler,Default_Handler

  254. 

  255.   .weak      EXTI2_3_IRQHandler

  256.   .thumb_set EXTI2_3_IRQHandler,Default_Handler

  257. 

  258.   .weak      EXTI4_15_IRQHandler

  259.   .thumb_set EXTI4_15_IRQHandler,Default_Handler

  260. 

  261.   .weak      DMA1_Channel1_IRQHandler

  262.   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler

  263. 

  264.   .weak      DMA1_Channel2_3_IRQHandler

  265.   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler

  266. 

  267.   .weak      DMA1_Channel4_5_IRQHandler

  268.   .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler

  269. 

  270.   .weak      ADC1_IRQHandler

  271.   .thumb_set ADC1_IRQHandler,Default_Handler

  272. 

  273.   .weak      TIM1_BRK_UP_TRG_COM_IRQHandler

  274.   .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler

  275. 

  276.   .weak      TIM1_CC_IRQHandler

  277.   .thumb_set TIM1_CC_IRQHandler,Default_Handler

  278. 

  279.   .weak      TIM3_IRQHandler

  280.   .thumb_set TIM3_IRQHandler,Default_Handler

  281. 

  282.   .weak      TIM14_IRQHandler

  283.   .thumb_set TIM14_IRQHandler,Default_Handler

  284. 

  285.   .weak      TIM16_IRQHandler

  286.   .thumb_set TIM16_IRQHandler,Default_Handler

  287. 

  288.   .weak      TIM17_IRQHandler

  289.   .thumb_set TIM17_IRQHandler,Default_Handler

  290. 

  291.   .weak      I2C1_IRQHandler

  292.   .thumb_set I2C1_IRQHandler,Default_Handler

  293. 

  294.   .weak      SPI1_IRQHandler

  295.   .thumb_set SPI1_IRQHandler,Default_Handler

  296. 

  297.   .weak      USART1_IRQHandler

  298.   .thumb_set USART1_IRQHandler,Default_Handler

  299. 

  300.   .weak      USART2_IRQHandler

  301.   .thumb_set USART2_IRQHandler,Default_Handler

  302. 

  303.   .weak      USB_IRQHandler

  304.   .thumb_set USB_IRQHandler,Default_Handler

  305. 

  306. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/