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  1. /**
  2. ******************************************************************************
  3. * @file stm32f7xx_hal_eth.c
  4. * @author MCD Application Team
  5. * @version V1.2.2
  6. * @date 14-April-2017
  7. * @brief ETH HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the Ethernet (ETH) peripheral:
  10. * + Initialization and de-initialization functions
  11. * + IO operation functions
  12. * + Peripheral Control functions
  13. * + Peripheral State and Errors functions
  14. *
  15. @verbatim
  16. ==============================================================================
  17. ##### How to use this driver #####
  18. ==============================================================================
  19. [..]
  20. (#)Declare a ETH_HandleTypeDef handle structure, for example:
  21. ETH_HandleTypeDef heth;
  22. (#)Fill parameters of Init structure in heth handle
  23. (#)Call HAL_ETH_Init() API to initialize the Ethernet peripheral (MAC, DMA, ...)
  24. (#)Initialize the ETH low level resources through the HAL_ETH_MspInit() API:
  25. (##) Enable the Ethernet interface clock using
  26. (+++) __HAL_RCC_ETHMAC_CLK_ENABLE();
  27. (+++) __HAL_RCC_ETHMACTX_CLK_ENABLE();
  28. (+++) __HAL_RCC_ETHMACRX_CLK_ENABLE();
  29. (##) Initialize the related GPIO clocks
  30. (##) Configure Ethernet pin-out
  31. (##) Configure Ethernet NVIC interrupt (IT mode)
  32. (#)Initialize Ethernet DMA Descriptors in chain mode and point to allocated buffers:
  33. (##) HAL_ETH_DMATxDescListInit(); for Transmission process
  34. (##) HAL_ETH_DMARxDescListInit(); for Reception process
  35. (#)Enable MAC and DMA transmission and reception:
  36. (##) HAL_ETH_Start();
  37. (#)Prepare ETH DMA TX Descriptors and give the hand to ETH DMA to transfer
  38. the frame to MAC TX FIFO:
  39. (##) HAL_ETH_TransmitFrame();
  40. (#)Poll for a received frame in ETH RX DMA Descriptors and get received
  41. frame parameters
  42. (##) HAL_ETH_GetReceivedFrame(); (should be called into an infinite loop)
  43. (#) Get a received frame when an ETH RX interrupt occurs:
  44. (##) HAL_ETH_GetReceivedFrame_IT(); (called in IT mode only)
  45. (#) Communicate with external PHY device:
  46. (##) Read a specific register from the PHY
  47. HAL_ETH_ReadPHYRegister();
  48. (##) Write data to a specific RHY register:
  49. HAL_ETH_WritePHYRegister();
  50. (#) Configure the Ethernet MAC after ETH peripheral initialization
  51. HAL_ETH_ConfigMAC(); all MAC parameters should be filled.
  52. (#) Configure the Ethernet DMA after ETH peripheral initialization
  53. HAL_ETH_ConfigDMA(); all DMA parameters should be filled.
  54. @endverbatim
  55. ******************************************************************************
  56. * @attention
  57. *
  58. * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  59. *
  60. * Redistribution and use in source and binary forms, with or without modification,
  61. * are permitted provided that the following conditions are met:
  62. * 1. Redistributions of source code must retain the above copyright notice,
  63. * this list of conditions and the following disclaimer.
  64. * 2. Redistributions in binary form must reproduce the above copyright notice,
  65. * this list of conditions and the following disclaimer in the documentation
  66. * and/or other materials provided with the distribution.
  67. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  68. * may be used to endorse or promote products derived from this software
  69. * without specific prior written permission.
  70. *
  71. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  72. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  73. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  74. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  75. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  76. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  77. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  78. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  79. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  80. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  81. *
  82. ******************************************************************************
  83. */
  84. /* Includes ------------------------------------------------------------------*/
  85. #include "stm32f7xx_hal.h"
  86. /** @addtogroup STM32F7xx_HAL_Driver
  87. * @{
  88. */
  89. /** @defgroup ETH ETH
  90. * @brief ETH HAL module driver
  91. * @{
  92. */
  93. #ifdef HAL_ETH_MODULE_ENABLED
  94. #if defined (ETH)
  95. /* Private typedef -----------------------------------------------------------*/
  96. /* Private define ------------------------------------------------------------*/
  97. /** @defgroup ETH_Private_Constants ETH Private Constants
  98. * @{
  99. */
  100. #define ETH_TIMEOUT_SWRESET ((uint32_t)500)
  101. #define ETH_TIMEOUT_LINKED_STATE ((uint32_t)5000)
  102. #define ETH_TIMEOUT_AUTONEGO_COMPLETED ((uint32_t)5000)
  103. /**
  104. * @}
  105. */
  106. /* Private macro -------------------------------------------------------------*/
  107. /* Private variables ---------------------------------------------------------*/
  108. /* Private function prototypes -----------------------------------------------*/
  109. /** @defgroup ETH_Private_Functions ETH Private Functions
  110. * @{
  111. */
  112. static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err);
  113. static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr);
  114. static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth);
  115. static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth);
  116. static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth);
  117. static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth);
  118. static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth);
  119. static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth);
  120. static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth);
  121. static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth);
  122. static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth);
  123. /**
  124. * @}
  125. */
  126. /* Private functions ---------------------------------------------------------*/
  127. /** @defgroup ETH_Exported_Functions ETH Exported Functions
  128. * @{
  129. */
  130. /** @defgroup ETH_Exported_Functions_Group1 Initialization and de-initialization functions
  131. * @brief Initialization and Configuration functions
  132. *
  133. @verbatim
  134. ===============================================================================
  135. ##### Initialization and de-initialization functions #####
  136. ===============================================================================
  137. [..] This section provides functions allowing to:
  138. (+) Initialize and configure the Ethernet peripheral
  139. (+) De-initialize the Ethernet peripheral
  140. @endverbatim
  141. * @{
  142. */
  143. /**
  144. * @brief Initializes the Ethernet MAC and DMA according to default
  145. * parameters.
  146. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  147. * the configuration information for ETHERNET module
  148. * @retval HAL status
  149. */
  150. HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth)
  151. {
  152. uint32_t tempreg = 0, phyreg = 0;
  153. uint32_t hclk = 60000000;
  154. uint32_t tickstart = 0;
  155. uint32_t err = ETH_SUCCESS;
  156. /* Check the ETH peripheral state */
  157. if(heth == NULL)
  158. {
  159. return HAL_ERROR;
  160. }
  161. /* Check parameters */
  162. assert_param(IS_ETH_AUTONEGOTIATION(heth->Init.AutoNegotiation));
  163. assert_param(IS_ETH_RX_MODE(heth->Init.RxMode));
  164. assert_param(IS_ETH_CHECKSUM_MODE(heth->Init.ChecksumMode));
  165. assert_param(IS_ETH_MEDIA_INTERFACE(heth->Init.MediaInterface));
  166. if(heth->State == HAL_ETH_STATE_RESET)
  167. {
  168. /* Allocate lock resource and initialize it */
  169. heth->Lock = HAL_UNLOCKED;
  170. /* Init the low level hardware : GPIO, CLOCK, NVIC. */
  171. HAL_ETH_MspInit(heth);
  172. }
  173. /* Enable SYSCFG Clock */
  174. __HAL_RCC_SYSCFG_CLK_ENABLE();
  175. /* Select MII or RMII Mode*/
  176. SYSCFG->PMC &= ~(SYSCFG_PMC_MII_RMII_SEL);
  177. SYSCFG->PMC |= (uint32_t)heth->Init.MediaInterface;
  178. /* Ethernet Software reset */
  179. /* Set the SWR bit: resets all MAC subsystem internal registers and logic */
  180. /* After reset all the registers holds their respective reset values */
  181. (heth->Instance)->DMABMR |= ETH_DMABMR_SR;
  182. /* Get tick */
  183. tickstart = HAL_GetTick();
  184. /* Wait for software reset */
  185. while (((heth->Instance)->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET)
  186. {
  187. /* Check for the Timeout */
  188. if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_SWRESET)
  189. {
  190. heth->State= HAL_ETH_STATE_TIMEOUT;
  191. /* Process Unlocked */
  192. __HAL_UNLOCK(heth);
  193. /* Note: The SWR is not performed if the ETH_RX_CLK or the ETH_TX_CLK are
  194. not available, please check your external PHY or the IO configuration */
  195. return HAL_TIMEOUT;
  196. }
  197. }
  198. /*-------------------------------- MAC Initialization ----------------------*/
  199. /* Get the ETHERNET MACMIIAR value */
  200. tempreg = (heth->Instance)->MACMIIAR;
  201. /* Clear CSR Clock Range CR[2:0] bits */
  202. tempreg &= ETH_MACMIIAR_CR_MASK;
  203. /* Get hclk frequency value */
  204. hclk = HAL_RCC_GetHCLKFreq();
  205. /* Set CR bits depending on hclk value */
  206. if((hclk >= 20000000)&&(hclk < 35000000))
  207. {
  208. /* CSR Clock Range between 20-35 MHz */
  209. tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div16;
  210. }
  211. else if((hclk >= 35000000)&&(hclk < 60000000))
  212. {
  213. /* CSR Clock Range between 35-60 MHz */
  214. tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div26;
  215. }
  216. else if((hclk >= 60000000)&&(hclk < 100000000))
  217. {
  218. /* CSR Clock Range between 60-100 MHz */
  219. tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div42;
  220. }
  221. else if((hclk >= 100000000)&&(hclk < 150000000))
  222. {
  223. /* CSR Clock Range between 100-150 MHz */
  224. tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div62;
  225. }
  226. else /* ((hclk >= 150000000)&&(hclk <= 216000000)) */
  227. {
  228. /* CSR Clock Range between 150-216 MHz */
  229. tempreg |= (uint32_t)ETH_MACMIIAR_CR_Div102;
  230. }
  231. /* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
  232. (heth->Instance)->MACMIIAR = (uint32_t)tempreg;
  233. /*-------------------- PHY initialization and configuration ----------------*/
  234. /* Put the PHY in reset mode */
  235. if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_RESET)) != HAL_OK)
  236. {
  237. /* In case of write timeout */
  238. err = ETH_ERROR;
  239. /* Config MAC and DMA */
  240. ETH_MACDMAConfig(heth, err);
  241. /* Set the ETH peripheral state to READY */
  242. heth->State = HAL_ETH_STATE_READY;
  243. /* Return HAL_ERROR */
  244. return HAL_ERROR;
  245. }
  246. /* Delay to assure PHY reset */
  247. HAL_Delay(PHY_RESET_DELAY);
  248. if((heth->Init).AutoNegotiation != ETH_AUTONEGOTIATION_DISABLE)
  249. {
  250. /* Get tick */
  251. tickstart = HAL_GetTick();
  252. /* We wait for linked status */
  253. do
  254. {
  255. HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
  256. /* Check for the Timeout */
  257. if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_LINKED_STATE)
  258. {
  259. /* In case of write timeout */
  260. err = ETH_ERROR;
  261. /* Config MAC and DMA */
  262. ETH_MACDMAConfig(heth, err);
  263. heth->State= HAL_ETH_STATE_READY;
  264. /* Process Unlocked */
  265. __HAL_UNLOCK(heth);
  266. return HAL_TIMEOUT;
  267. }
  268. } while (((phyreg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS));
  269. /* Enable Auto-Negotiation */
  270. if((HAL_ETH_WritePHYRegister(heth, PHY_BCR, PHY_AUTONEGOTIATION)) != HAL_OK)
  271. {
  272. /* In case of write timeout */
  273. err = ETH_ERROR;
  274. /* Config MAC and DMA */
  275. ETH_MACDMAConfig(heth, err);
  276. /* Set the ETH peripheral state to READY */
  277. heth->State = HAL_ETH_STATE_READY;
  278. /* Return HAL_ERROR */
  279. return HAL_ERROR;
  280. }
  281. /* Get tick */
  282. tickstart = HAL_GetTick();
  283. /* Wait until the auto-negotiation will be completed */
  284. do
  285. {
  286. HAL_ETH_ReadPHYRegister(heth, PHY_BSR, &phyreg);
  287. /* Check for the Timeout */
  288. if((HAL_GetTick() - tickstart ) > ETH_TIMEOUT_AUTONEGO_COMPLETED)
  289. {
  290. /* In case of write timeout */
  291. err = ETH_ERROR;
  292. /* Config MAC and DMA */
  293. ETH_MACDMAConfig(heth, err);
  294. heth->State= HAL_ETH_STATE_READY;
  295. /* Process Unlocked */
  296. __HAL_UNLOCK(heth);
  297. return HAL_TIMEOUT;
  298. }
  299. } while (((phyreg & PHY_AUTONEGO_COMPLETE) != PHY_AUTONEGO_COMPLETE));
  300. /* Read the result of the auto-negotiation */
  301. if((HAL_ETH_ReadPHYRegister(heth, PHY_SR, &phyreg)) != HAL_OK)
  302. {
  303. /* In case of write timeout */
  304. err = ETH_ERROR;
  305. /* Config MAC and DMA */
  306. ETH_MACDMAConfig(heth, err);
  307. /* Set the ETH peripheral state to READY */
  308. heth->State = HAL_ETH_STATE_READY;
  309. /* Return HAL_ERROR */
  310. return HAL_ERROR;
  311. }
  312. /* Configure the MAC with the Duplex Mode fixed by the auto-negotiation process */
  313. if((phyreg & PHY_DUPLEX_STATUS) != (uint32_t)RESET)
  314. {
  315. /* Set Ethernet duplex mode to Full-duplex following the auto-negotiation */
  316. (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
  317. }
  318. else
  319. {
  320. /* Set Ethernet duplex mode to Half-duplex following the auto-negotiation */
  321. (heth->Init).DuplexMode = ETH_MODE_HALFDUPLEX;
  322. }
  323. /* Configure the MAC with the speed fixed by the auto-negotiation process */
  324. if((phyreg & PHY_SPEED_STATUS) == PHY_SPEED_STATUS)
  325. {
  326. /* Set Ethernet speed to 10M following the auto-negotiation */
  327. (heth->Init).Speed = ETH_SPEED_10M;
  328. }
  329. else
  330. {
  331. /* Set Ethernet speed to 100M following the auto-negotiation */
  332. (heth->Init).Speed = ETH_SPEED_100M;
  333. }
  334. }
  335. else /* AutoNegotiation Disable */
  336. {
  337. /* Check parameters */
  338. assert_param(IS_ETH_SPEED(heth->Init.Speed));
  339. assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
  340. /* Set MAC Speed and Duplex Mode */
  341. if(HAL_ETH_WritePHYRegister(heth, PHY_BCR, ((uint16_t)((heth->Init).DuplexMode >> 3) |
  342. (uint16_t)((heth->Init).Speed >> 1))) != HAL_OK)
  343. {
  344. /* In case of write timeout */
  345. err = ETH_ERROR;
  346. /* Config MAC and DMA */
  347. ETH_MACDMAConfig(heth, err);
  348. /* Set the ETH peripheral state to READY */
  349. heth->State = HAL_ETH_STATE_READY;
  350. /* Return HAL_ERROR */
  351. return HAL_ERROR;
  352. }
  353. /* Delay to assure PHY configuration */
  354. HAL_Delay(PHY_CONFIG_DELAY);
  355. }
  356. /* Config MAC and DMA */
  357. ETH_MACDMAConfig(heth, err);
  358. /* Set ETH HAL State to Ready */
  359. heth->State= HAL_ETH_STATE_READY;
  360. /* Return function status */
  361. return HAL_OK;
  362. }
  363. /**
  364. * @brief De-Initializes the ETH peripheral.
  365. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  366. * the configuration information for ETHERNET module
  367. * @retval HAL status
  368. */
  369. HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth)
  370. {
  371. /* Set the ETH peripheral state to BUSY */
  372. heth->State = HAL_ETH_STATE_BUSY;
  373. /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */
  374. HAL_ETH_MspDeInit(heth);
  375. /* Set ETH HAL state to Disabled */
  376. heth->State= HAL_ETH_STATE_RESET;
  377. /* Release Lock */
  378. __HAL_UNLOCK(heth);
  379. /* Return function status */
  380. return HAL_OK;
  381. }
  382. /**
  383. * @brief Initializes the DMA Tx descriptors in chain mode.
  384. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  385. * the configuration information for ETHERNET module
  386. * @param DMATxDescTab: Pointer to the first Tx desc list
  387. * @param TxBuff: Pointer to the first TxBuffer list
  388. * @param TxBuffCount: Number of the used Tx desc in the list
  389. * @retval HAL status
  390. */
  391. HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
  392. {
  393. uint32_t i = 0;
  394. ETH_DMADescTypeDef *dmatxdesc;
  395. /* Process Locked */
  396. __HAL_LOCK(heth);
  397. /* Set the ETH peripheral state to BUSY */
  398. heth->State = HAL_ETH_STATE_BUSY;
  399. /* Set the DMATxDescToSet pointer with the first one of the DMATxDescTab list */
  400. heth->TxDesc = DMATxDescTab;
  401. /* Fill each DMATxDesc descriptor with the right values */
  402. for(i=0; i < TxBuffCount; i++)
  403. {
  404. /* Get the pointer on the ith member of the Tx Desc list */
  405. dmatxdesc = DMATxDescTab + i;
  406. /* Set Second Address Chained bit */
  407. dmatxdesc->Status = ETH_DMATXDESC_TCH;
  408. /* Set Buffer1 address pointer */
  409. dmatxdesc->Buffer1Addr = (uint32_t)(&TxBuff[i*ETH_TX_BUF_SIZE]);
  410. if ((heth->Init).ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
  411. {
  412. /* Set the DMA Tx descriptors checksum insertion */
  413. dmatxdesc->Status |= ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL;
  414. }
  415. /* Initialize the next descriptor with the Next Descriptor Polling Enable */
  416. if(i < (TxBuffCount-1))
  417. {
  418. /* Set next descriptor address register with next descriptor base address */
  419. dmatxdesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab+i+1);
  420. }
  421. else
  422. {
  423. /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
  424. dmatxdesc->Buffer2NextDescAddr = (uint32_t) DMATxDescTab;
  425. }
  426. }
  427. /* Set Transmit Descriptor List Address Register */
  428. (heth->Instance)->DMATDLAR = (uint32_t) DMATxDescTab;
  429. /* Set ETH HAL State to Ready */
  430. heth->State= HAL_ETH_STATE_READY;
  431. /* Process Unlocked */
  432. __HAL_UNLOCK(heth);
  433. /* Return function status */
  434. return HAL_OK;
  435. }
  436. /**
  437. * @brief Initializes the DMA Rx descriptors in chain mode.
  438. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  439. * the configuration information for ETHERNET module
  440. * @param DMARxDescTab: Pointer to the first Rx desc list
  441. * @param RxBuff: Pointer to the first RxBuffer list
  442. * @param RxBuffCount: Number of the used Rx desc in the list
  443. * @retval HAL status
  444. */
  445. HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
  446. {
  447. uint32_t i = 0;
  448. ETH_DMADescTypeDef *DMARxDesc;
  449. /* Process Locked */
  450. __HAL_LOCK(heth);
  451. /* Set the ETH peripheral state to BUSY */
  452. heth->State = HAL_ETH_STATE_BUSY;
  453. /* Set the Ethernet RxDesc pointer with the first one of the DMARxDescTab list */
  454. heth->RxDesc = DMARxDescTab;
  455. /* Fill each DMARxDesc descriptor with the right values */
  456. for(i=0; i < RxBuffCount; i++)
  457. {
  458. /* Get the pointer on the ith member of the Rx Desc list */
  459. DMARxDesc = DMARxDescTab+i;
  460. /* Set Own bit of the Rx descriptor Status */
  461. DMARxDesc->Status = ETH_DMARXDESC_OWN;
  462. /* Set Buffer1 size and Second Address Chained bit */
  463. DMARxDesc->ControlBufferSize = ETH_DMARXDESC_RCH | ETH_RX_BUF_SIZE;
  464. /* Set Buffer1 address pointer */
  465. DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i*ETH_RX_BUF_SIZE]);
  466. if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
  467. {
  468. /* Enable Ethernet DMA Rx Descriptor interrupt */
  469. DMARxDesc->ControlBufferSize &= ~ETH_DMARXDESC_DIC;
  470. }
  471. /* Initialize the next descriptor with the Next Descriptor Polling Enable */
  472. if(i < (RxBuffCount-1))
  473. {
  474. /* Set next descriptor address register with next descriptor base address */
  475. DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab+i+1);
  476. }
  477. else
  478. {
  479. /* For last descriptor, set next descriptor address register equal to the first descriptor base address */
  480. DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab);
  481. }
  482. }
  483. /* Set Receive Descriptor List Address Register */
  484. (heth->Instance)->DMARDLAR = (uint32_t) DMARxDescTab;
  485. /* Set ETH HAL State to Ready */
  486. heth->State= HAL_ETH_STATE_READY;
  487. /* Process Unlocked */
  488. __HAL_UNLOCK(heth);
  489. /* Return function status */
  490. return HAL_OK;
  491. }
  492. /**
  493. * @brief Initializes the ETH MSP.
  494. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  495. * the configuration information for ETHERNET module
  496. * @retval None
  497. */
  498. __weak void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
  499. {
  500. /* Prevent unused argument(s) compilation warning */
  501. UNUSED(heth);
  502. /* NOTE : This function Should not be modified, when the callback is needed,
  503. the HAL_ETH_MspInit could be implemented in the user file
  504. */
  505. }
  506. /**
  507. * @brief DeInitializes ETH MSP.
  508. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  509. * the configuration information for ETHERNET module
  510. * @retval None
  511. */
  512. __weak void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
  513. {
  514. /* Prevent unused argument(s) compilation warning */
  515. UNUSED(heth);
  516. /* NOTE : This function Should not be modified, when the callback is needed,
  517. the HAL_ETH_MspDeInit could be implemented in the user file
  518. */
  519. }
  520. /**
  521. * @}
  522. */
  523. /** @defgroup ETH_Exported_Functions_Group2 IO operation functions
  524. * @brief Data transfers functions
  525. *
  526. @verbatim
  527. ==============================================================================
  528. ##### IO operation functions #####
  529. ==============================================================================
  530. [..] This section provides functions allowing to:
  531. (+) Transmit a frame
  532. HAL_ETH_TransmitFrame();
  533. (+) Receive a frame
  534. HAL_ETH_GetReceivedFrame();
  535. HAL_ETH_GetReceivedFrame_IT();
  536. (+) Read from an External PHY register
  537. HAL_ETH_ReadPHYRegister();
  538. (+) Write to an External PHY register
  539. HAL_ETH_WritePHYRegister();
  540. @endverbatim
  541. * @{
  542. */
  543. /**
  544. * @brief Sends an Ethernet frame.
  545. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  546. * the configuration information for ETHERNET module
  547. * @param FrameLength: Amount of data to be sent
  548. * @retval HAL status
  549. */
  550. HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
  551. {
  552. uint32_t bufcount = 0, size = 0, i = 0;
  553. /* Process Locked */
  554. __HAL_LOCK(heth);
  555. /* Set the ETH peripheral state to BUSY */
  556. heth->State = HAL_ETH_STATE_BUSY;
  557. if (FrameLength == 0)
  558. {
  559. /* Set ETH HAL state to READY */
  560. heth->State = HAL_ETH_STATE_READY;
  561. /* Process Unlocked */
  562. __HAL_UNLOCK(heth);
  563. return HAL_ERROR;
  564. }
  565. /* Check if the descriptor is owned by the ETHERNET DMA (when set) or CPU (when reset) */
  566. if(((heth->TxDesc)->Status & ETH_DMATXDESC_OWN) != (uint32_t)RESET)
  567. {
  568. /* OWN bit set */
  569. heth->State = HAL_ETH_STATE_BUSY_TX;
  570. /* Process Unlocked */
  571. __HAL_UNLOCK(heth);
  572. return HAL_ERROR;
  573. }
  574. /* Get the number of needed Tx buffers for the current frame */
  575. if (FrameLength > ETH_TX_BUF_SIZE)
  576. {
  577. bufcount = FrameLength/ETH_TX_BUF_SIZE;
  578. if (FrameLength % ETH_TX_BUF_SIZE)
  579. {
  580. bufcount++;
  581. }
  582. }
  583. else
  584. {
  585. bufcount = 1;
  586. }
  587. if (bufcount == 1)
  588. {
  589. /* Set LAST and FIRST segment */
  590. heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
  591. /* Set frame size */
  592. heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
  593. /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
  594. heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
  595. /* Point to next descriptor */
  596. heth->TxDesc= (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
  597. }
  598. else
  599. {
  600. for (i=0; i< bufcount; i++)
  601. {
  602. /* Clear FIRST and LAST segment bits */
  603. heth->TxDesc->Status &= ~(ETH_DMATXDESC_FS | ETH_DMATXDESC_LS);
  604. if (i == 0)
  605. {
  606. /* Setting the first segment bit */
  607. heth->TxDesc->Status |= ETH_DMATXDESC_FS;
  608. }
  609. /* Program size */
  610. heth->TxDesc->ControlBufferSize = (ETH_TX_BUF_SIZE & ETH_DMATXDESC_TBS1);
  611. if (i == (bufcount-1))
  612. {
  613. /* Setting the last segment bit */
  614. heth->TxDesc->Status |= ETH_DMATXDESC_LS;
  615. size = FrameLength - (bufcount-1)*ETH_TX_BUF_SIZE;
  616. heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
  617. }
  618. /* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
  619. heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
  620. /* point to next descriptor */
  621. heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
  622. }
  623. }
  624. /* When Tx Buffer unavailable flag is set: clear it and resume transmission */
  625. if (((heth->Instance)->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET)
  626. {
  627. /* Clear TBUS ETHERNET DMA flag */
  628. (heth->Instance)->DMASR = ETH_DMASR_TBUS;
  629. /* Resume DMA transmission*/
  630. (heth->Instance)->DMATPDR = 0;
  631. }
  632. /* Set ETH HAL State to Ready */
  633. heth->State = HAL_ETH_STATE_READY;
  634. /* Process Unlocked */
  635. __HAL_UNLOCK(heth);
  636. /* Return function status */
  637. return HAL_OK;
  638. }
  639. /**
  640. * @brief Checks for received frames.
  641. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  642. * the configuration information for ETHERNET module
  643. * @retval HAL status
  644. */
  645. HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth)
  646. {
  647. uint32_t framelength = 0;
  648. /* Process Locked */
  649. __HAL_LOCK(heth);
  650. /* Check the ETH state to BUSY */
  651. heth->State = HAL_ETH_STATE_BUSY;
  652. /* Check if segment is not owned by DMA */
  653. /* (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET)) */
  654. if(((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET))
  655. {
  656. /* Check if last segment */
  657. if(((heth->RxDesc->Status & ETH_DMARXDESC_LS) != (uint32_t)RESET))
  658. {
  659. /* increment segment count */
  660. (heth->RxFrameInfos).SegCount++;
  661. /* Check if last segment is first segment: one segment contains the frame */
  662. if ((heth->RxFrameInfos).SegCount == 1)
  663. {
  664. (heth->RxFrameInfos).FSRxDesc =heth->RxDesc;
  665. }
  666. heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
  667. /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
  668. framelength = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
  669. heth->RxFrameInfos.length = framelength;
  670. /* Get the address of the buffer start address */
  671. heth->RxFrameInfos.buffer = ((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
  672. /* point to next descriptor */
  673. heth->RxDesc = (ETH_DMADescTypeDef*) ((heth->RxDesc)->Buffer2NextDescAddr);
  674. /* Set HAL State to Ready */
  675. heth->State = HAL_ETH_STATE_READY;
  676. /* Process Unlocked */
  677. __HAL_UNLOCK(heth);
  678. /* Return function status */
  679. return HAL_OK;
  680. }
  681. /* Check if first segment */
  682. else if((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET)
  683. {
  684. (heth->RxFrameInfos).FSRxDesc = heth->RxDesc;
  685. (heth->RxFrameInfos).LSRxDesc = NULL;
  686. (heth->RxFrameInfos).SegCount = 1;
  687. /* Point to next descriptor */
  688. heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
  689. }
  690. /* Check if intermediate segment */
  691. else
  692. {
  693. (heth->RxFrameInfos).SegCount++;
  694. /* Point to next descriptor */
  695. heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
  696. }
  697. }
  698. /* Set ETH HAL State to Ready */
  699. heth->State = HAL_ETH_STATE_READY;
  700. /* Process Unlocked */
  701. __HAL_UNLOCK(heth);
  702. /* Return function status */
  703. return HAL_ERROR;
  704. }
  705. /**
  706. * @brief Gets the Received frame in interrupt mode.
  707. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  708. * the configuration information for ETHERNET module
  709. * @retval HAL status
  710. */
  711. HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth)
  712. {
  713. uint32_t descriptorscancounter = 0;
  714. /* Process Locked */
  715. __HAL_LOCK(heth);
  716. /* Set ETH HAL State to BUSY */
  717. heth->State = HAL_ETH_STATE_BUSY;
  718. /* Scan descriptors owned by CPU */
  719. while (((heth->RxDesc->Status & ETH_DMARXDESC_OWN) == (uint32_t)RESET) && (descriptorscancounter < ETH_RXBUFNB))
  720. {
  721. /* Just for security */
  722. descriptorscancounter++;
  723. /* Check if first segment in frame */
  724. /* ((heth->RxDesc->Status & ETH_DMARXDESC_FS) != (uint32_t)RESET) && ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)) */
  725. if((heth->RxDesc->Status & (ETH_DMARXDESC_FS | ETH_DMARXDESC_LS)) == (uint32_t)ETH_DMARXDESC_FS)
  726. {
  727. heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
  728. heth->RxFrameInfos.SegCount = 1;
  729. /* Point to next descriptor */
  730. heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
  731. }
  732. /* Check if intermediate segment */
  733. /* ((heth->RxDesc->Status & ETH_DMARXDESC_LS) == (uint32_t)RESET)&& ((heth->RxDesc->Status & ETH_DMARXDESC_FS) == (uint32_t)RESET)) */
  734. else if ((heth->RxDesc->Status & (ETH_DMARXDESC_LS | ETH_DMARXDESC_FS)) == (uint32_t)RESET)
  735. {
  736. /* Increment segment count */
  737. (heth->RxFrameInfos.SegCount)++;
  738. /* Point to next descriptor */
  739. heth->RxDesc = (ETH_DMADescTypeDef*)(heth->RxDesc->Buffer2NextDescAddr);
  740. }
  741. /* Should be last segment */
  742. else
  743. {
  744. /* Last segment */
  745. heth->RxFrameInfos.LSRxDesc = heth->RxDesc;
  746. /* Increment segment count */
  747. (heth->RxFrameInfos.SegCount)++;
  748. /* Check if last segment is first segment: one segment contains the frame */
  749. if ((heth->RxFrameInfos.SegCount) == 1)
  750. {
  751. heth->RxFrameInfos.FSRxDesc = heth->RxDesc;
  752. }
  753. /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */
  754. heth->RxFrameInfos.length = (((heth->RxDesc)->Status & ETH_DMARXDESC_FL) >> ETH_DMARXDESC_FRAMELENGTHSHIFT) - 4;
  755. /* Get the address of the buffer start address */
  756. heth->RxFrameInfos.buffer =((heth->RxFrameInfos).FSRxDesc)->Buffer1Addr;
  757. /* Point to next descriptor */
  758. heth->RxDesc = (ETH_DMADescTypeDef*) (heth->RxDesc->Buffer2NextDescAddr);
  759. /* Set HAL State to Ready */
  760. heth->State = HAL_ETH_STATE_READY;
  761. /* Process Unlocked */
  762. __HAL_UNLOCK(heth);
  763. /* Return function status */
  764. return HAL_OK;
  765. }
  766. }
  767. /* Set HAL State to Ready */
  768. heth->State = HAL_ETH_STATE_READY;
  769. /* Process Unlocked */
  770. __HAL_UNLOCK(heth);
  771. /* Return function status */
  772. return HAL_ERROR;
  773. }
  774. /**
  775. * @brief This function handles ETH interrupt request.
  776. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  777. * the configuration information for ETHERNET module
  778. * @retval HAL status
  779. */
  780. void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth)
  781. {
  782. /* Frame received */
  783. if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_R))
  784. {
  785. /* Receive complete callback */
  786. HAL_ETH_RxCpltCallback(heth);
  787. /* Clear the Eth DMA Rx IT pending bits */
  788. __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_R);
  789. /* Set HAL State to Ready */
  790. heth->State = HAL_ETH_STATE_READY;
  791. /* Process Unlocked */
  792. __HAL_UNLOCK(heth);
  793. }
  794. /* Frame transmitted */
  795. else if (__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_T))
  796. {
  797. /* Transfer complete callback */
  798. HAL_ETH_TxCpltCallback(heth);
  799. /* Clear the Eth DMA Tx IT pending bits */
  800. __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_T);
  801. /* Set HAL State to Ready */
  802. heth->State = HAL_ETH_STATE_READY;
  803. /* Process Unlocked */
  804. __HAL_UNLOCK(heth);
  805. }
  806. /* Clear the interrupt flags */
  807. __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_IT_NIS);
  808. /* ETH DMA Error */
  809. if(__HAL_ETH_DMA_GET_FLAG(heth, ETH_DMA_FLAG_AIS))
  810. {
  811. /* Ethernet Error callback */
  812. HAL_ETH_ErrorCallback(heth);
  813. /* Clear the interrupt flags */
  814. __HAL_ETH_DMA_CLEAR_IT(heth, ETH_DMA_FLAG_AIS);
  815. /* Set HAL State to Ready */
  816. heth->State = HAL_ETH_STATE_READY;
  817. /* Process Unlocked */
  818. __HAL_UNLOCK(heth);
  819. }
  820. }
  821. /**
  822. * @brief Tx Transfer completed callbacks.
  823. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  824. * the configuration information for ETHERNET module
  825. * @retval None
  826. */
  827. __weak void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth)
  828. {
  829. /* Prevent unused argument(s) compilation warning */
  830. UNUSED(heth);
  831. /* NOTE : This function Should not be modified, when the callback is needed,
  832. the HAL_ETH_TxCpltCallback could be implemented in the user file
  833. */
  834. }
  835. /**
  836. * @brief Rx Transfer completed callbacks.
  837. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  838. * the configuration information for ETHERNET module
  839. * @retval None
  840. */
  841. __weak void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
  842. {
  843. /* Prevent unused argument(s) compilation warning */
  844. UNUSED(heth);
  845. /* NOTE : This function Should not be modified, when the callback is needed,
  846. the HAL_ETH_TxCpltCallback could be implemented in the user file
  847. */
  848. }
  849. /**
  850. * @brief Ethernet transfer error callbacks
  851. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  852. * the configuration information for ETHERNET module
  853. * @retval None
  854. */
  855. __weak void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
  856. {
  857. /* Prevent unused argument(s) compilation warning */
  858. UNUSED(heth);
  859. /* NOTE : This function Should not be modified, when the callback is needed,
  860. the HAL_ETH_TxCpltCallback could be implemented in the user file
  861. */
  862. }
  863. /**
  864. * @brief Reads a PHY register
  865. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  866. * the configuration information for ETHERNET module
  867. * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
  868. * This parameter can be one of the following values:
  869. * PHY_BCR: Transceiver Basic Control Register,
  870. * PHY_BSR: Transceiver Basic Status Register.
  871. * More PHY register could be read depending on the used PHY
  872. * @param RegValue: PHY register value
  873. * @retval HAL status
  874. */
  875. HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
  876. {
  877. uint32_t tmpreg = 0;
  878. uint32_t tickstart = 0;
  879. /* Check parameters */
  880. assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
  881. /* Check the ETH peripheral state */
  882. if(heth->State == HAL_ETH_STATE_BUSY_RD)
  883. {
  884. return HAL_BUSY;
  885. }
  886. /* Set ETH HAL State to BUSY_RD */
  887. heth->State = HAL_ETH_STATE_BUSY_RD;
  888. /* Get the ETHERNET MACMIIAR value */
  889. tmpreg = heth->Instance->MACMIIAR;
  890. /* Keep only the CSR Clock Range CR[2:0] bits value */
  891. tmpreg &= ~ETH_MACMIIAR_CR_MASK;
  892. /* Prepare the MII address register value */
  893. tmpreg |=(((uint32_t)heth->Init.PhyAddress << 11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
  894. tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
  895. tmpreg &= ~ETH_MACMIIAR_MW; /* Set the read mode */
  896. tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
  897. /* Write the result value into the MII Address register */
  898. heth->Instance->MACMIIAR = tmpreg;
  899. /* Get tick */
  900. tickstart = HAL_GetTick();
  901. /* Check for the Busy flag */
  902. while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
  903. {
  904. /* Check for the Timeout */
  905. if((HAL_GetTick() - tickstart ) > PHY_READ_TO)
  906. {
  907. heth->State= HAL_ETH_STATE_READY;
  908. /* Process Unlocked */
  909. __HAL_UNLOCK(heth);
  910. return HAL_TIMEOUT;
  911. }
  912. tmpreg = heth->Instance->MACMIIAR;
  913. }
  914. /* Get MACMIIDR value */
  915. *RegValue = (uint16_t)(heth->Instance->MACMIIDR);
  916. /* Set ETH HAL State to READY */
  917. heth->State = HAL_ETH_STATE_READY;
  918. /* Return function status */
  919. return HAL_OK;
  920. }
  921. /**
  922. * @brief Writes to a PHY register.
  923. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  924. * the configuration information for ETHERNET module
  925. * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
  926. * This parameter can be one of the following values:
  927. * PHY_BCR: Transceiver Control Register.
  928. * More PHY register could be written depending on the used PHY
  929. * @param RegValue: the value to write
  930. * @retval HAL status
  931. */
  932. HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
  933. {
  934. uint32_t tmpreg = 0;
  935. uint32_t tickstart = 0;
  936. /* Check parameters */
  937. assert_param(IS_ETH_PHY_ADDRESS(heth->Init.PhyAddress));
  938. /* Check the ETH peripheral state */
  939. if(heth->State == HAL_ETH_STATE_BUSY_WR)
  940. {
  941. return HAL_BUSY;
  942. }
  943. /* Set ETH HAL State to BUSY_WR */
  944. heth->State = HAL_ETH_STATE_BUSY_WR;
  945. /* Get the ETHERNET MACMIIAR value */
  946. tmpreg = heth->Instance->MACMIIAR;
  947. /* Keep only the CSR Clock Range CR[2:0] bits value */
  948. tmpreg &= ~ETH_MACMIIAR_CR_MASK;
  949. /* Prepare the MII register address value */
  950. tmpreg |=(((uint32_t)heth->Init.PhyAddress<<11) & ETH_MACMIIAR_PA); /* Set the PHY device address */
  951. tmpreg |=(((uint32_t)PHYReg<<6) & ETH_MACMIIAR_MR); /* Set the PHY register address */
  952. tmpreg |= ETH_MACMIIAR_MW; /* Set the write mode */
  953. tmpreg |= ETH_MACMIIAR_MB; /* Set the MII Busy bit */
  954. /* Give the value to the MII data register */
  955. heth->Instance->MACMIIDR = (uint16_t)RegValue;
  956. /* Write the result value into the MII Address register */
  957. heth->Instance->MACMIIAR = tmpreg;
  958. /* Get tick */
  959. tickstart = HAL_GetTick();
  960. /* Check for the Busy flag */
  961. while((tmpreg & ETH_MACMIIAR_MB) == ETH_MACMIIAR_MB)
  962. {
  963. /* Check for the Timeout */
  964. if((HAL_GetTick() - tickstart ) > PHY_WRITE_TO)
  965. {
  966. heth->State= HAL_ETH_STATE_READY;
  967. /* Process Unlocked */
  968. __HAL_UNLOCK(heth);
  969. return HAL_TIMEOUT;
  970. }
  971. tmpreg = heth->Instance->MACMIIAR;
  972. }
  973. /* Set ETH HAL State to READY */
  974. heth->State = HAL_ETH_STATE_READY;
  975. /* Return function status */
  976. return HAL_OK;
  977. }
  978. /**
  979. * @}
  980. */
  981. /** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions
  982. * @brief Peripheral Control functions
  983. *
  984. @verbatim
  985. ===============================================================================
  986. ##### Peripheral Control functions #####
  987. ===============================================================================
  988. [..] This section provides functions allowing to:
  989. (+) Enable MAC and DMA transmission and reception.
  990. HAL_ETH_Start();
  991. (+) Disable MAC and DMA transmission and reception.
  992. HAL_ETH_Stop();
  993. (+) Set the MAC configuration in runtime mode
  994. HAL_ETH_ConfigMAC();
  995. (+) Set the DMA configuration in runtime mode
  996. HAL_ETH_ConfigDMA();
  997. @endverbatim
  998. * @{
  999. */
  1000. /**
  1001. * @brief Enables Ethernet MAC and DMA reception/transmission
  1002. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1003. * the configuration information for ETHERNET module
  1004. * @retval HAL status
  1005. */
  1006. HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth)
  1007. {
  1008. /* Process Locked */
  1009. __HAL_LOCK(heth);
  1010. /* Set the ETH peripheral state to BUSY */
  1011. heth->State = HAL_ETH_STATE_BUSY;
  1012. /* Enable transmit state machine of the MAC for transmission on the MII */
  1013. ETH_MACTransmissionEnable(heth);
  1014. /* Enable receive state machine of the MAC for reception from the MII */
  1015. ETH_MACReceptionEnable(heth);
  1016. /* Flush Transmit FIFO */
  1017. ETH_FlushTransmitFIFO(heth);
  1018. /* Start DMA transmission */
  1019. ETH_DMATransmissionEnable(heth);
  1020. /* Start DMA reception */
  1021. ETH_DMAReceptionEnable(heth);
  1022. /* Set the ETH state to READY*/
  1023. heth->State= HAL_ETH_STATE_READY;
  1024. /* Process Unlocked */
  1025. __HAL_UNLOCK(heth);
  1026. /* Return function status */
  1027. return HAL_OK;
  1028. }
  1029. /**
  1030. * @brief Stop Ethernet MAC and DMA reception/transmission
  1031. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1032. * the configuration information for ETHERNET module
  1033. * @retval HAL status
  1034. */
  1035. HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth)
  1036. {
  1037. /* Process Locked */
  1038. __HAL_LOCK(heth);
  1039. /* Set the ETH peripheral state to BUSY */
  1040. heth->State = HAL_ETH_STATE_BUSY;
  1041. /* Stop DMA transmission */
  1042. ETH_DMATransmissionDisable(heth);
  1043. /* Stop DMA reception */
  1044. ETH_DMAReceptionDisable(heth);
  1045. /* Disable receive state machine of the MAC for reception from the MII */
  1046. ETH_MACReceptionDisable(heth);
  1047. /* Flush Transmit FIFO */
  1048. ETH_FlushTransmitFIFO(heth);
  1049. /* Disable transmit state machine of the MAC for transmission on the MII */
  1050. ETH_MACTransmissionDisable(heth);
  1051. /* Set the ETH state*/
  1052. heth->State = HAL_ETH_STATE_READY;
  1053. /* Process Unlocked */
  1054. __HAL_UNLOCK(heth);
  1055. /* Return function status */
  1056. return HAL_OK;
  1057. }
  1058. /**
  1059. * @brief Set ETH MAC Configuration.
  1060. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1061. * the configuration information for ETHERNET module
  1062. * @param macconf: MAC Configuration structure
  1063. * @retval HAL status
  1064. */
  1065. HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
  1066. {
  1067. uint32_t tmpreg = 0;
  1068. /* Process Locked */
  1069. __HAL_LOCK(heth);
  1070. /* Set the ETH peripheral state to BUSY */
  1071. heth->State= HAL_ETH_STATE_BUSY;
  1072. assert_param(IS_ETH_SPEED(heth->Init.Speed));
  1073. assert_param(IS_ETH_DUPLEX_MODE(heth->Init.DuplexMode));
  1074. if (macconf != NULL)
  1075. {
  1076. /* Check the parameters */
  1077. assert_param(IS_ETH_WATCHDOG(macconf->Watchdog));
  1078. assert_param(IS_ETH_JABBER(macconf->Jabber));
  1079. assert_param(IS_ETH_INTER_FRAME_GAP(macconf->InterFrameGap));
  1080. assert_param(IS_ETH_CARRIER_SENSE(macconf->CarrierSense));
  1081. assert_param(IS_ETH_RECEIVE_OWN(macconf->ReceiveOwn));
  1082. assert_param(IS_ETH_LOOPBACK_MODE(macconf->LoopbackMode));
  1083. assert_param(IS_ETH_CHECKSUM_OFFLOAD(macconf->ChecksumOffload));
  1084. assert_param(IS_ETH_RETRY_TRANSMISSION(macconf->RetryTransmission));
  1085. assert_param(IS_ETH_AUTOMATIC_PADCRC_STRIP(macconf->AutomaticPadCRCStrip));
  1086. assert_param(IS_ETH_BACKOFF_LIMIT(macconf->BackOffLimit));
  1087. assert_param(IS_ETH_DEFERRAL_CHECK(macconf->DeferralCheck));
  1088. assert_param(IS_ETH_RECEIVE_ALL(macconf->ReceiveAll));
  1089. assert_param(IS_ETH_SOURCE_ADDR_FILTER(macconf->SourceAddrFilter));
  1090. assert_param(IS_ETH_CONTROL_FRAMES(macconf->PassControlFrames));
  1091. assert_param(IS_ETH_BROADCAST_FRAMES_RECEPTION(macconf->BroadcastFramesReception));
  1092. assert_param(IS_ETH_DESTINATION_ADDR_FILTER(macconf->DestinationAddrFilter));
  1093. assert_param(IS_ETH_PROMISCUOUS_MODE(macconf->PromiscuousMode));
  1094. assert_param(IS_ETH_MULTICAST_FRAMES_FILTER(macconf->MulticastFramesFilter));
  1095. assert_param(IS_ETH_UNICAST_FRAMES_FILTER(macconf->UnicastFramesFilter));
  1096. assert_param(IS_ETH_PAUSE_TIME(macconf->PauseTime));
  1097. assert_param(IS_ETH_ZEROQUANTA_PAUSE(macconf->ZeroQuantaPause));
  1098. assert_param(IS_ETH_PAUSE_LOW_THRESHOLD(macconf->PauseLowThreshold));
  1099. assert_param(IS_ETH_UNICAST_PAUSE_FRAME_DETECT(macconf->UnicastPauseFrameDetect));
  1100. assert_param(IS_ETH_RECEIVE_FLOWCONTROL(macconf->ReceiveFlowControl));
  1101. assert_param(IS_ETH_TRANSMIT_FLOWCONTROL(macconf->TransmitFlowControl));
  1102. assert_param(IS_ETH_VLAN_TAG_COMPARISON(macconf->VLANTagComparison));
  1103. assert_param(IS_ETH_VLAN_TAG_IDENTIFIER(macconf->VLANTagIdentifier));
  1104. /*------------------------ ETHERNET MACCR Configuration --------------------*/
  1105. /* Get the ETHERNET MACCR value */
  1106. tmpreg = (heth->Instance)->MACCR;
  1107. /* Clear WD, PCE, PS, TE and RE bits */
  1108. tmpreg &= ETH_MACCR_CLEAR_MASK;
  1109. tmpreg |= (uint32_t)(macconf->Watchdog |
  1110. macconf->Jabber |
  1111. macconf->InterFrameGap |
  1112. macconf->CarrierSense |
  1113. (heth->Init).Speed |
  1114. macconf->ReceiveOwn |
  1115. macconf->LoopbackMode |
  1116. (heth->Init).DuplexMode |
  1117. macconf->ChecksumOffload |
  1118. macconf->RetryTransmission |
  1119. macconf->AutomaticPadCRCStrip |
  1120. macconf->BackOffLimit |
  1121. macconf->DeferralCheck);
  1122. /* Write to ETHERNET MACCR */
  1123. (heth->Instance)->MACCR = (uint32_t)tmpreg;
  1124. /* Wait until the write operation will be taken into account :
  1125. at least four TX_CLK/RX_CLK clock cycles */
  1126. tmpreg = (heth->Instance)->MACCR;
  1127. HAL_Delay(ETH_REG_WRITE_DELAY);
  1128. (heth->Instance)->MACCR = tmpreg;
  1129. /*----------------------- ETHERNET MACFFR Configuration --------------------*/
  1130. /* Write to ETHERNET MACFFR */
  1131. (heth->Instance)->MACFFR = (uint32_t)(macconf->ReceiveAll |
  1132. macconf->SourceAddrFilter |
  1133. macconf->PassControlFrames |
  1134. macconf->BroadcastFramesReception |
  1135. macconf->DestinationAddrFilter |
  1136. macconf->PromiscuousMode |
  1137. macconf->MulticastFramesFilter |
  1138. macconf->UnicastFramesFilter);
  1139. /* Wait until the write operation will be taken into account :
  1140. at least four TX_CLK/RX_CLK clock cycles */
  1141. tmpreg = (heth->Instance)->MACFFR;
  1142. HAL_Delay(ETH_REG_WRITE_DELAY);
  1143. (heth->Instance)->MACFFR = tmpreg;
  1144. /*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
  1145. /* Write to ETHERNET MACHTHR */
  1146. (heth->Instance)->MACHTHR = (uint32_t)macconf->HashTableHigh;
  1147. /* Write to ETHERNET MACHTLR */
  1148. (heth->Instance)->MACHTLR = (uint32_t)macconf->HashTableLow;
  1149. /*----------------------- ETHERNET MACFCR Configuration --------------------*/
  1150. /* Get the ETHERNET MACFCR value */
  1151. tmpreg = (heth->Instance)->MACFCR;
  1152. /* Clear xx bits */
  1153. tmpreg &= ETH_MACFCR_CLEAR_MASK;
  1154. tmpreg |= (uint32_t)((macconf->PauseTime << 16) |
  1155. macconf->ZeroQuantaPause |
  1156. macconf->PauseLowThreshold |
  1157. macconf->UnicastPauseFrameDetect |
  1158. macconf->ReceiveFlowControl |
  1159. macconf->TransmitFlowControl);
  1160. /* Write to ETHERNET MACFCR */
  1161. (heth->Instance)->MACFCR = (uint32_t)tmpreg;
  1162. /* Wait until the write operation will be taken into account :
  1163. at least four TX_CLK/RX_CLK clock cycles */
  1164. tmpreg = (heth->Instance)->MACFCR;
  1165. HAL_Delay(ETH_REG_WRITE_DELAY);
  1166. (heth->Instance)->MACFCR = tmpreg;
  1167. /*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
  1168. (heth->Instance)->MACVLANTR = (uint32_t)(macconf->VLANTagComparison |
  1169. macconf->VLANTagIdentifier);
  1170. /* Wait until the write operation will be taken into account :
  1171. at least four TX_CLK/RX_CLK clock cycles */
  1172. tmpreg = (heth->Instance)->MACVLANTR;
  1173. HAL_Delay(ETH_REG_WRITE_DELAY);
  1174. (heth->Instance)->MACVLANTR = tmpreg;
  1175. }
  1176. else /* macconf == NULL : here we just configure Speed and Duplex mode */
  1177. {
  1178. /*------------------------ ETHERNET MACCR Configuration --------------------*/
  1179. /* Get the ETHERNET MACCR value */
  1180. tmpreg = (heth->Instance)->MACCR;
  1181. /* Clear FES and DM bits */
  1182. tmpreg &= ~((uint32_t)0x00004800);
  1183. tmpreg |= (uint32_t)(heth->Init.Speed | heth->Init.DuplexMode);
  1184. /* Write to ETHERNET MACCR */
  1185. (heth->Instance)->MACCR = (uint32_t)tmpreg;
  1186. /* Wait until the write operation will be taken into account:
  1187. at least four TX_CLK/RX_CLK clock cycles */
  1188. tmpreg = (heth->Instance)->MACCR;
  1189. HAL_Delay(ETH_REG_WRITE_DELAY);
  1190. (heth->Instance)->MACCR = tmpreg;
  1191. }
  1192. /* Set the ETH state to Ready */
  1193. heth->State= HAL_ETH_STATE_READY;
  1194. /* Process Unlocked */
  1195. __HAL_UNLOCK(heth);
  1196. /* Return function status */
  1197. return HAL_OK;
  1198. }
  1199. /**
  1200. * @brief Sets ETH DMA Configuration.
  1201. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1202. * the configuration information for ETHERNET module
  1203. * @param dmaconf: DMA Configuration structure
  1204. * @retval HAL status
  1205. */
  1206. HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
  1207. {
  1208. uint32_t tmpreg = 0;
  1209. /* Process Locked */
  1210. __HAL_LOCK(heth);
  1211. /* Set the ETH peripheral state to BUSY */
  1212. heth->State= HAL_ETH_STATE_BUSY;
  1213. /* Check parameters */
  1214. assert_param(IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(dmaconf->DropTCPIPChecksumErrorFrame));
  1215. assert_param(IS_ETH_RECEIVE_STORE_FORWARD(dmaconf->ReceiveStoreForward));
  1216. assert_param(IS_ETH_FLUSH_RECEIVE_FRAME(dmaconf->FlushReceivedFrame));
  1217. assert_param(IS_ETH_TRANSMIT_STORE_FORWARD(dmaconf->TransmitStoreForward));
  1218. assert_param(IS_ETH_TRANSMIT_THRESHOLD_CONTROL(dmaconf->TransmitThresholdControl));
  1219. assert_param(IS_ETH_FORWARD_ERROR_FRAMES(dmaconf->ForwardErrorFrames));
  1220. assert_param(IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(dmaconf->ForwardUndersizedGoodFrames));
  1221. assert_param(IS_ETH_RECEIVE_THRESHOLD_CONTROL(dmaconf->ReceiveThresholdControl));
  1222. assert_param(IS_ETH_SECOND_FRAME_OPERATE(dmaconf->SecondFrameOperate));
  1223. assert_param(IS_ETH_ADDRESS_ALIGNED_BEATS(dmaconf->AddressAlignedBeats));
  1224. assert_param(IS_ETH_FIXED_BURST(dmaconf->FixedBurst));
  1225. assert_param(IS_ETH_RXDMA_BURST_LENGTH(dmaconf->RxDMABurstLength));
  1226. assert_param(IS_ETH_TXDMA_BURST_LENGTH(dmaconf->TxDMABurstLength));
  1227. assert_param(IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(dmaconf->EnhancedDescriptorFormat));
  1228. assert_param(IS_ETH_DMA_DESC_SKIP_LENGTH(dmaconf->DescriptorSkipLength));
  1229. assert_param(IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(dmaconf->DMAArbitration));
  1230. /*----------------------- ETHERNET DMAOMR Configuration --------------------*/
  1231. /* Get the ETHERNET DMAOMR value */
  1232. tmpreg = (heth->Instance)->DMAOMR;
  1233. /* Clear xx bits */
  1234. tmpreg &= ETH_DMAOMR_CLEAR_MASK;
  1235. tmpreg |= (uint32_t)(dmaconf->DropTCPIPChecksumErrorFrame |
  1236. dmaconf->ReceiveStoreForward |
  1237. dmaconf->FlushReceivedFrame |
  1238. dmaconf->TransmitStoreForward |
  1239. dmaconf->TransmitThresholdControl |
  1240. dmaconf->ForwardErrorFrames |
  1241. dmaconf->ForwardUndersizedGoodFrames |
  1242. dmaconf->ReceiveThresholdControl |
  1243. dmaconf->SecondFrameOperate);
  1244. /* Write to ETHERNET DMAOMR */
  1245. (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
  1246. /* Wait until the write operation will be taken into account:
  1247. at least four TX_CLK/RX_CLK clock cycles */
  1248. tmpreg = (heth->Instance)->DMAOMR;
  1249. HAL_Delay(ETH_REG_WRITE_DELAY);
  1250. (heth->Instance)->DMAOMR = tmpreg;
  1251. /*----------------------- ETHERNET DMABMR Configuration --------------------*/
  1252. (heth->Instance)->DMABMR = (uint32_t)(dmaconf->AddressAlignedBeats |
  1253. dmaconf->FixedBurst |
  1254. dmaconf->RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
  1255. dmaconf->TxDMABurstLength |
  1256. dmaconf->EnhancedDescriptorFormat |
  1257. (dmaconf->DescriptorSkipLength << 2) |
  1258. dmaconf->DMAArbitration |
  1259. ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
  1260. /* Wait until the write operation will be taken into account:
  1261. at least four TX_CLK/RX_CLK clock cycles */
  1262. tmpreg = (heth->Instance)->DMABMR;
  1263. HAL_Delay(ETH_REG_WRITE_DELAY);
  1264. (heth->Instance)->DMABMR = tmpreg;
  1265. /* Set the ETH state to Ready */
  1266. heth->State= HAL_ETH_STATE_READY;
  1267. /* Process Unlocked */
  1268. __HAL_UNLOCK(heth);
  1269. /* Return function status */
  1270. return HAL_OK;
  1271. }
  1272. /**
  1273. * @}
  1274. */
  1275. /** @defgroup ETH_Exported_Functions_Group4 Peripheral State functions
  1276. * @brief Peripheral State functions
  1277. *
  1278. @verbatim
  1279. ===============================================================================
  1280. ##### Peripheral State functions #####
  1281. ===============================================================================
  1282. [..]
  1283. This subsection permits to get in run-time the status of the peripheral
  1284. and the data flow.
  1285. (+) Get the ETH handle state:
  1286. HAL_ETH_GetState();
  1287. @endverbatim
  1288. * @{
  1289. */
  1290. /**
  1291. * @brief Return the ETH HAL state
  1292. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1293. * the configuration information for ETHERNET module
  1294. * @retval HAL state
  1295. */
  1296. HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth)
  1297. {
  1298. /* Return ETH state */
  1299. return heth->State;
  1300. }
  1301. /**
  1302. * @}
  1303. */
  1304. /**
  1305. * @}
  1306. */
  1307. /** @addtogroup ETH_Private_Functions
  1308. * @{
  1309. */
  1310. /**
  1311. * @brief Configures Ethernet MAC and DMA with default parameters.
  1312. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1313. * the configuration information for ETHERNET module
  1314. * @param err: Ethernet Init error
  1315. * @retval HAL status
  1316. */
  1317. static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
  1318. {
  1319. ETH_MACInitTypeDef macinit;
  1320. ETH_DMAInitTypeDef dmainit;
  1321. uint32_t tmpreg = 0;
  1322. if (err != ETH_SUCCESS) /* Auto-negotiation failed */
  1323. {
  1324. /* Set Ethernet duplex mode to Full-duplex */
  1325. (heth->Init).DuplexMode = ETH_MODE_FULLDUPLEX;
  1326. /* Set Ethernet speed to 100M */
  1327. (heth->Init).Speed = ETH_SPEED_100M;
  1328. }
  1329. /* Ethernet MAC default initialization **************************************/
  1330. macinit.Watchdog = ETH_WATCHDOG_ENABLE;
  1331. macinit.Jabber = ETH_JABBER_ENABLE;
  1332. macinit.InterFrameGap = ETH_INTERFRAMEGAP_96BIT;
  1333. macinit.CarrierSense = ETH_CARRIERSENCE_ENABLE;
  1334. macinit.ReceiveOwn = ETH_RECEIVEOWN_ENABLE;
  1335. macinit.LoopbackMode = ETH_LOOPBACKMODE_DISABLE;
  1336. if(heth->Init.ChecksumMode == ETH_CHECKSUM_BY_HARDWARE)
  1337. {
  1338. macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_ENABLE;
  1339. }
  1340. else
  1341. {
  1342. macinit.ChecksumOffload = ETH_CHECKSUMOFFLAOD_DISABLE;
  1343. }
  1344. macinit.RetryTransmission = ETH_RETRYTRANSMISSION_DISABLE;
  1345. macinit.AutomaticPadCRCStrip = ETH_AUTOMATICPADCRCSTRIP_DISABLE;
  1346. macinit.BackOffLimit = ETH_BACKOFFLIMIT_10;
  1347. macinit.DeferralCheck = ETH_DEFFERRALCHECK_DISABLE;
  1348. macinit.ReceiveAll = ETH_RECEIVEAll_DISABLE;
  1349. macinit.SourceAddrFilter = ETH_SOURCEADDRFILTER_DISABLE;
  1350. macinit.PassControlFrames = ETH_PASSCONTROLFRAMES_BLOCKALL;
  1351. macinit.BroadcastFramesReception = ETH_BROADCASTFRAMESRECEPTION_ENABLE;
  1352. macinit.DestinationAddrFilter = ETH_DESTINATIONADDRFILTER_NORMAL;
  1353. macinit.PromiscuousMode = ETH_PROMISCUOUS_MODE_DISABLE;
  1354. macinit.MulticastFramesFilter = ETH_MULTICASTFRAMESFILTER_PERFECT;
  1355. macinit.UnicastFramesFilter = ETH_UNICASTFRAMESFILTER_PERFECT;
  1356. macinit.HashTableHigh = 0x0;
  1357. macinit.HashTableLow = 0x0;
  1358. macinit.PauseTime = 0x0;
  1359. macinit.ZeroQuantaPause = ETH_ZEROQUANTAPAUSE_DISABLE;
  1360. macinit.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS4;
  1361. macinit.UnicastPauseFrameDetect = ETH_UNICASTPAUSEFRAMEDETECT_DISABLE;
  1362. macinit.ReceiveFlowControl = ETH_RECEIVEFLOWCONTROL_DISABLE;
  1363. macinit.TransmitFlowControl = ETH_TRANSMITFLOWCONTROL_DISABLE;
  1364. macinit.VLANTagComparison = ETH_VLANTAGCOMPARISON_16BIT;
  1365. macinit.VLANTagIdentifier = 0x0;
  1366. /*------------------------ ETHERNET MACCR Configuration --------------------*/
  1367. /* Get the ETHERNET MACCR value */
  1368. tmpreg = (heth->Instance)->MACCR;
  1369. /* Clear WD, PCE, PS, TE and RE bits */
  1370. tmpreg &= ETH_MACCR_CLEAR_MASK;
  1371. /* Set the WD bit according to ETH Watchdog value */
  1372. /* Set the JD: bit according to ETH Jabber value */
  1373. /* Set the IFG bit according to ETH InterFrameGap value */
  1374. /* Set the DCRS bit according to ETH CarrierSense value */
  1375. /* Set the FES bit according to ETH Speed value */
  1376. /* Set the DO bit according to ETH ReceiveOwn value */
  1377. /* Set the LM bit according to ETH LoopbackMode value */
  1378. /* Set the DM bit according to ETH Mode value */
  1379. /* Set the IPCO bit according to ETH ChecksumOffload value */
  1380. /* Set the DR bit according to ETH RetryTransmission value */
  1381. /* Set the ACS bit according to ETH AutomaticPadCRCStrip value */
  1382. /* Set the BL bit according to ETH BackOffLimit value */
  1383. /* Set the DC bit according to ETH DeferralCheck value */
  1384. tmpreg |= (uint32_t)(macinit.Watchdog |
  1385. macinit.Jabber |
  1386. macinit.InterFrameGap |
  1387. macinit.CarrierSense |
  1388. (heth->Init).Speed |
  1389. macinit.ReceiveOwn |
  1390. macinit.LoopbackMode |
  1391. (heth->Init).DuplexMode |
  1392. macinit.ChecksumOffload |
  1393. macinit.RetryTransmission |
  1394. macinit.AutomaticPadCRCStrip |
  1395. macinit.BackOffLimit |
  1396. macinit.DeferralCheck);
  1397. /* Write to ETHERNET MACCR */
  1398. (heth->Instance)->MACCR = (uint32_t)tmpreg;
  1399. /* Wait until the write operation will be taken into account:
  1400. at least four TX_CLK/RX_CLK clock cycles */
  1401. tmpreg = (heth->Instance)->MACCR;
  1402. HAL_Delay(ETH_REG_WRITE_DELAY);
  1403. (heth->Instance)->MACCR = tmpreg;
  1404. /*----------------------- ETHERNET MACFFR Configuration --------------------*/
  1405. /* Set the RA bit according to ETH ReceiveAll value */
  1406. /* Set the SAF and SAIF bits according to ETH SourceAddrFilter value */
  1407. /* Set the PCF bit according to ETH PassControlFrames value */
  1408. /* Set the DBF bit according to ETH BroadcastFramesReception value */
  1409. /* Set the DAIF bit according to ETH DestinationAddrFilter value */
  1410. /* Set the PR bit according to ETH PromiscuousMode value */
  1411. /* Set the PM, HMC and HPF bits according to ETH MulticastFramesFilter value */
  1412. /* Set the HUC and HPF bits according to ETH UnicastFramesFilter value */
  1413. /* Write to ETHERNET MACFFR */
  1414. (heth->Instance)->MACFFR = (uint32_t)(macinit.ReceiveAll |
  1415. macinit.SourceAddrFilter |
  1416. macinit.PassControlFrames |
  1417. macinit.BroadcastFramesReception |
  1418. macinit.DestinationAddrFilter |
  1419. macinit.PromiscuousMode |
  1420. macinit.MulticastFramesFilter |
  1421. macinit.UnicastFramesFilter);
  1422. /* Wait until the write operation will be taken into account:
  1423. at least four TX_CLK/RX_CLK clock cycles */
  1424. tmpreg = (heth->Instance)->MACFFR;
  1425. HAL_Delay(ETH_REG_WRITE_DELAY);
  1426. (heth->Instance)->MACFFR = tmpreg;
  1427. /*--------------- ETHERNET MACHTHR and MACHTLR Configuration --------------*/
  1428. /* Write to ETHERNET MACHTHR */
  1429. (heth->Instance)->MACHTHR = (uint32_t)macinit.HashTableHigh;
  1430. /* Write to ETHERNET MACHTLR */
  1431. (heth->Instance)->MACHTLR = (uint32_t)macinit.HashTableLow;
  1432. /*----------------------- ETHERNET MACFCR Configuration -------------------*/
  1433. /* Get the ETHERNET MACFCR value */
  1434. tmpreg = (heth->Instance)->MACFCR;
  1435. /* Clear xx bits */
  1436. tmpreg &= ETH_MACFCR_CLEAR_MASK;
  1437. /* Set the PT bit according to ETH PauseTime value */
  1438. /* Set the DZPQ bit according to ETH ZeroQuantaPause value */
  1439. /* Set the PLT bit according to ETH PauseLowThreshold value */
  1440. /* Set the UP bit according to ETH UnicastPauseFrameDetect value */
  1441. /* Set the RFE bit according to ETH ReceiveFlowControl value */
  1442. /* Set the TFE bit according to ETH TransmitFlowControl value */
  1443. tmpreg |= (uint32_t)((macinit.PauseTime << 16) |
  1444. macinit.ZeroQuantaPause |
  1445. macinit.PauseLowThreshold |
  1446. macinit.UnicastPauseFrameDetect |
  1447. macinit.ReceiveFlowControl |
  1448. macinit.TransmitFlowControl);
  1449. /* Write to ETHERNET MACFCR */
  1450. (heth->Instance)->MACFCR = (uint32_t)tmpreg;
  1451. /* Wait until the write operation will be taken into account:
  1452. at least four TX_CLK/RX_CLK clock cycles */
  1453. tmpreg = (heth->Instance)->MACFCR;
  1454. HAL_Delay(ETH_REG_WRITE_DELAY);
  1455. (heth->Instance)->MACFCR = tmpreg;
  1456. /*----------------------- ETHERNET MACVLANTR Configuration ----------------*/
  1457. /* Set the ETV bit according to ETH VLANTagComparison value */
  1458. /* Set the VL bit according to ETH VLANTagIdentifier value */
  1459. (heth->Instance)->MACVLANTR = (uint32_t)(macinit.VLANTagComparison |
  1460. macinit.VLANTagIdentifier);
  1461. /* Wait until the write operation will be taken into account:
  1462. at least four TX_CLK/RX_CLK clock cycles */
  1463. tmpreg = (heth->Instance)->MACVLANTR;
  1464. HAL_Delay(ETH_REG_WRITE_DELAY);
  1465. (heth->Instance)->MACVLANTR = tmpreg;
  1466. /* Ethernet DMA default initialization ************************************/
  1467. dmainit.DropTCPIPChecksumErrorFrame = ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE;
  1468. dmainit.ReceiveStoreForward = ETH_RECEIVESTOREFORWARD_ENABLE;
  1469. dmainit.FlushReceivedFrame = ETH_FLUSHRECEIVEDFRAME_ENABLE;
  1470. dmainit.TransmitStoreForward = ETH_TRANSMITSTOREFORWARD_ENABLE;
  1471. dmainit.TransmitThresholdControl = ETH_TRANSMITTHRESHOLDCONTROL_64BYTES;
  1472. dmainit.ForwardErrorFrames = ETH_FORWARDERRORFRAMES_DISABLE;
  1473. dmainit.ForwardUndersizedGoodFrames = ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE;
  1474. dmainit.ReceiveThresholdControl = ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES;
  1475. dmainit.SecondFrameOperate = ETH_SECONDFRAMEOPERARTE_ENABLE;
  1476. dmainit.AddressAlignedBeats = ETH_ADDRESSALIGNEDBEATS_ENABLE;
  1477. dmainit.FixedBurst = ETH_FIXEDBURST_ENABLE;
  1478. dmainit.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT;
  1479. dmainit.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT;
  1480. dmainit.EnhancedDescriptorFormat = ETH_DMAENHANCEDDESCRIPTOR_ENABLE;
  1481. dmainit.DescriptorSkipLength = 0x0;
  1482. dmainit.DMAArbitration = ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1;
  1483. /* Get the ETHERNET DMAOMR value */
  1484. tmpreg = (heth->Instance)->DMAOMR;
  1485. /* Clear xx bits */
  1486. tmpreg &= ETH_DMAOMR_CLEAR_MASK;
  1487. /* Set the DT bit according to ETH DropTCPIPChecksumErrorFrame value */
  1488. /* Set the RSF bit according to ETH ReceiveStoreForward value */
  1489. /* Set the DFF bit according to ETH FlushReceivedFrame value */
  1490. /* Set the TSF bit according to ETH TransmitStoreForward value */
  1491. /* Set the TTC bit according to ETH TransmitThresholdControl value */
  1492. /* Set the FEF bit according to ETH ForwardErrorFrames value */
  1493. /* Set the FUF bit according to ETH ForwardUndersizedGoodFrames value */
  1494. /* Set the RTC bit according to ETH ReceiveThresholdControl value */
  1495. /* Set the OSF bit according to ETH SecondFrameOperate value */
  1496. tmpreg |= (uint32_t)(dmainit.DropTCPIPChecksumErrorFrame |
  1497. dmainit.ReceiveStoreForward |
  1498. dmainit.FlushReceivedFrame |
  1499. dmainit.TransmitStoreForward |
  1500. dmainit.TransmitThresholdControl |
  1501. dmainit.ForwardErrorFrames |
  1502. dmainit.ForwardUndersizedGoodFrames |
  1503. dmainit.ReceiveThresholdControl |
  1504. dmainit.SecondFrameOperate);
  1505. /* Write to ETHERNET DMAOMR */
  1506. (heth->Instance)->DMAOMR = (uint32_t)tmpreg;
  1507. /* Wait until the write operation will be taken into account:
  1508. at least four TX_CLK/RX_CLK clock cycles */
  1509. tmpreg = (heth->Instance)->DMAOMR;
  1510. HAL_Delay(ETH_REG_WRITE_DELAY);
  1511. (heth->Instance)->DMAOMR = tmpreg;
  1512. /*----------------------- ETHERNET DMABMR Configuration ------------------*/
  1513. /* Set the AAL bit according to ETH AddressAlignedBeats value */
  1514. /* Set the FB bit according to ETH FixedBurst value */
  1515. /* Set the RPBL and 4*PBL bits according to ETH RxDMABurstLength value */
  1516. /* Set the PBL and 4*PBL bits according to ETH TxDMABurstLength value */
  1517. /* Set the Enhanced DMA descriptors bit according to ETH EnhancedDescriptorFormat value*/
  1518. /* Set the DSL bit according to ETH DesciptorSkipLength value */
  1519. /* Set the PR and DA bits according to ETH DMAArbitration value */
  1520. (heth->Instance)->DMABMR = (uint32_t)(dmainit.AddressAlignedBeats |
  1521. dmainit.FixedBurst |
  1522. dmainit.RxDMABurstLength | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
  1523. dmainit.TxDMABurstLength |
  1524. dmainit.EnhancedDescriptorFormat |
  1525. (dmainit.DescriptorSkipLength << 2) |
  1526. dmainit.DMAArbitration |
  1527. ETH_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
  1528. /* Wait until the write operation will be taken into account:
  1529. at least four TX_CLK/RX_CLK clock cycles */
  1530. tmpreg = (heth->Instance)->DMABMR;
  1531. HAL_Delay(ETH_REG_WRITE_DELAY);
  1532. (heth->Instance)->DMABMR = tmpreg;
  1533. if((heth->Init).RxMode == ETH_RXINTERRUPT_MODE)
  1534. {
  1535. /* Enable the Ethernet Rx Interrupt */
  1536. __HAL_ETH_DMA_ENABLE_IT((heth), ETH_DMA_IT_NIS | ETH_DMA_IT_R);
  1537. }
  1538. /* Initialize MAC address in ethernet MAC */
  1539. ETH_MACAddressConfig(heth, ETH_MAC_ADDRESS0, heth->Init.MACAddr);
  1540. }
  1541. /**
  1542. * @brief Configures the selected MAC address.
  1543. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1544. * the configuration information for ETHERNET module
  1545. * @param MacAddr: The MAC address to configure
  1546. * This parameter can be one of the following values:
  1547. * @arg ETH_MAC_Address0: MAC Address0
  1548. * @arg ETH_MAC_Address1: MAC Address1
  1549. * @arg ETH_MAC_Address2: MAC Address2
  1550. * @arg ETH_MAC_Address3: MAC Address3
  1551. * @param Addr: Pointer to MAC address buffer data (6 bytes)
  1552. * @retval HAL status
  1553. */
  1554. static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
  1555. {
  1556. uint32_t tmpreg;
  1557. /* Check the parameters */
  1558. assert_param(IS_ETH_MAC_ADDRESS0123(MacAddr));
  1559. /* Calculate the selected MAC address high register */
  1560. tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4];
  1561. /* Load the selected MAC address high register */
  1562. (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_HBASE + MacAddr))) = tmpreg;
  1563. /* Calculate the selected MAC address low register */
  1564. tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0];
  1565. /* Load the selected MAC address low register */
  1566. (*(__IO uint32_t *)((uint32_t)(ETH_MAC_ADDR_LBASE + MacAddr))) = tmpreg;
  1567. }
  1568. /**
  1569. * @brief Enables the MAC transmission.
  1570. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1571. * the configuration information for ETHERNET module
  1572. * @retval None
  1573. */
  1574. static void ETH_MACTransmissionEnable(ETH_HandleTypeDef *heth)
  1575. {
  1576. __IO uint32_t tmpreg = 0;
  1577. /* Enable the MAC transmission */
  1578. (heth->Instance)->MACCR |= ETH_MACCR_TE;
  1579. /* Wait until the write operation will be taken into account:
  1580. at least four TX_CLK/RX_CLK clock cycles */
  1581. tmpreg = (heth->Instance)->MACCR;
  1582. HAL_Delay(ETH_REG_WRITE_DELAY);
  1583. (heth->Instance)->MACCR = tmpreg;
  1584. }
  1585. /**
  1586. * @brief Disables the MAC transmission.
  1587. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1588. * the configuration information for ETHERNET module
  1589. * @retval None
  1590. */
  1591. static void ETH_MACTransmissionDisable(ETH_HandleTypeDef *heth)
  1592. {
  1593. __IO uint32_t tmpreg = 0;
  1594. /* Disable the MAC transmission */
  1595. (heth->Instance)->MACCR &= ~ETH_MACCR_TE;
  1596. /* Wait until the write operation will be taken into account:
  1597. at least four TX_CLK/RX_CLK clock cycles */
  1598. tmpreg = (heth->Instance)->MACCR;
  1599. HAL_Delay(ETH_REG_WRITE_DELAY);
  1600. (heth->Instance)->MACCR = tmpreg;
  1601. }
  1602. /**
  1603. * @brief Enables the MAC reception.
  1604. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1605. * the configuration information for ETHERNET module
  1606. * @retval None
  1607. */
  1608. static void ETH_MACReceptionEnable(ETH_HandleTypeDef *heth)
  1609. {
  1610. __IO uint32_t tmpreg = 0;
  1611. /* Enable the MAC reception */
  1612. (heth->Instance)->MACCR |= ETH_MACCR_RE;
  1613. /* Wait until the write operation will be taken into account:
  1614. at least four TX_CLK/RX_CLK clock cycles */
  1615. tmpreg = (heth->Instance)->MACCR;
  1616. HAL_Delay(ETH_REG_WRITE_DELAY);
  1617. (heth->Instance)->MACCR = tmpreg;
  1618. }
  1619. /**
  1620. * @brief Disables the MAC reception.
  1621. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1622. * the configuration information for ETHERNET module
  1623. * @retval None
  1624. */
  1625. static void ETH_MACReceptionDisable(ETH_HandleTypeDef *heth)
  1626. {
  1627. __IO uint32_t tmpreg = 0;
  1628. /* Disable the MAC reception */
  1629. (heth->Instance)->MACCR &= ~ETH_MACCR_RE;
  1630. /* Wait until the write operation will be taken into account:
  1631. at least four TX_CLK/RX_CLK clock cycles */
  1632. tmpreg = (heth->Instance)->MACCR;
  1633. HAL_Delay(ETH_REG_WRITE_DELAY);
  1634. (heth->Instance)->MACCR = tmpreg;
  1635. }
  1636. /**
  1637. * @brief Enables the DMA transmission.
  1638. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1639. * the configuration information for ETHERNET module
  1640. * @retval None
  1641. */
  1642. static void ETH_DMATransmissionEnable(ETH_HandleTypeDef *heth)
  1643. {
  1644. /* Enable the DMA transmission */
  1645. (heth->Instance)->DMAOMR |= ETH_DMAOMR_ST;
  1646. }
  1647. /**
  1648. * @brief Disables the DMA transmission.
  1649. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1650. * the configuration information for ETHERNET module
  1651. * @retval None
  1652. */
  1653. static void ETH_DMATransmissionDisable(ETH_HandleTypeDef *heth)
  1654. {
  1655. /* Disable the DMA transmission */
  1656. (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_ST;
  1657. }
  1658. /**
  1659. * @brief Enables the DMA reception.
  1660. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1661. * the configuration information for ETHERNET module
  1662. * @retval None
  1663. */
  1664. static void ETH_DMAReceptionEnable(ETH_HandleTypeDef *heth)
  1665. {
  1666. /* Enable the DMA reception */
  1667. (heth->Instance)->DMAOMR |= ETH_DMAOMR_SR;
  1668. }
  1669. /**
  1670. * @brief Disables the DMA reception.
  1671. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1672. * the configuration information for ETHERNET module
  1673. * @retval None
  1674. */
  1675. static void ETH_DMAReceptionDisable(ETH_HandleTypeDef *heth)
  1676. {
  1677. /* Disable the DMA reception */
  1678. (heth->Instance)->DMAOMR &= ~ETH_DMAOMR_SR;
  1679. }
  1680. /**
  1681. * @brief Clears the ETHERNET transmit FIFO.
  1682. * @param heth: pointer to a ETH_HandleTypeDef structure that contains
  1683. * the configuration information for ETHERNET module
  1684. * @retval None
  1685. */
  1686. static void ETH_FlushTransmitFIFO(ETH_HandleTypeDef *heth)
  1687. {
  1688. __IO uint32_t tmpreg = 0;
  1689. /* Set the Flush Transmit FIFO bit */
  1690. (heth->Instance)->DMAOMR |= ETH_DMAOMR_FTF;
  1691. /* Wait until the write operation will be taken into account:
  1692. at least four TX_CLK/RX_CLK clock cycles */
  1693. tmpreg = (heth->Instance)->DMAOMR;
  1694. HAL_Delay(ETH_REG_WRITE_DELAY);
  1695. (heth->Instance)->DMAOMR = tmpreg;
  1696. }
  1697. /**
  1698. * @}
  1699. */
  1700. #endif /* ETH */
  1701. #endif /* HAL_ETH_MODULE_ENABLED */
  1702. /**
  1703. * @}
  1704. */
  1705. /**
  1706. * @}
  1707. */
  1708. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/