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  1. /**
  2. ******************************************************************************
  3. * @file stm32wbxx_ll_dma.h
  4. * @author MCD Application Team
  5. * @brief Header file of DMA LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32WBxx_LL_DMA_H
  21. #define STM32WBxx_LL_DMA_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32wbxx.h"
  27. #include "stm32wbxx_ll_dmamux.h"
  28. /** @addtogroup STM32WBxx_LL_Driver
  29. * @{
  30. */
  31. #if defined (DMA1) || defined (DMA2)
  32. /** @defgroup DMA_LL DMA
  33. * @{
  34. */
  35. /* Private types -------------------------------------------------------------*/
  36. /* Private variables ---------------------------------------------------------*/
  37. /* Private constants ---------------------------------------------------------*/
  38. /* Private macros ------------------------------------------------------------*/
  39. /** @defgroup DMA_LL_Private_Macros DMA Private Macros
  40. * @{
  41. */
  42. /**
  43. * @brief Helper macro to convert DMA Instance and index into DMA channel
  44. * @param __DMA_INSTANCE__ DMAx
  45. * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
  46. * @retval Pointer to the DMA channel
  47. */
  48. #if defined (DMA2)
  49. #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \
  50. (((__DMA_INSTANCE__) == DMA1) ? (DMA1_Channel1 + (__CHANNEL_INDEX__)) : (DMA2_Channel1 + (__CHANNEL_INDEX__)))
  51. #else
  52. #define __LL_DMA_INSTANCE_TO_CHANNEL(__DMA_INSTANCE__, __CHANNEL_INDEX__) \
  53. (DMA1_Channel1 + (__CHANNEL_INDEX__))
  54. #endif
  55. /**
  56. * @brief Helper macro to convert DMA Instance and index into DMAMUX channel
  57. * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7.
  58. * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7 (**** only available on chip which support DMA2 ****).
  59. * @param __DMA_INSTANCE__ DMAx
  60. * @param __CHANNEL_INDEX__ 0 to 6 to map DMAx_Channel1 to DMAx_Channel7
  61. * @retval Pointer to the DMA channel
  62. */
  63. #if defined (DMA2)
  64. #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
  65. (((__DMA_INSTANCE__) == DMA1) ? (DMAMUX1_Channel0 + (__CHANNEL_INDEX__)) : (DMAMUX1_Channel7 + (__CHANNEL_INDEX__)))
  66. #else
  67. #define __LL_DMA_INSTANCE_TO_DMAMUX_CCR(__DMA_INSTANCE__, __CHANNEL_INDEX__)\
  68. (DMAMUX1_Channel0 + (__CHANNEL_INDEX__))
  69. #endif
  70. /**
  71. * @}
  72. */
  73. /* Exported types ------------------------------------------------------------*/
  74. #if defined(USE_FULL_LL_DRIVER)
  75. /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
  76. * @{
  77. */
  78. typedef struct
  79. {
  80. uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
  81. or as Source base address in case of memory to memory transfer direction.
  82. This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
  83. uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
  84. or as Destination base address in case of memory to memory transfer direction.
  85. This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
  86. uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
  87. from memory to memory or from peripheral to memory.
  88. This parameter can be a value of @ref DMA_LL_EC_DIRECTION
  89. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
  90. uint32_t Mode; /*!< Specifies the normal or circular operation mode.
  91. This parameter can be a value of @ref DMA_LL_EC_MODE
  92. @note: The circular buffer mode cannot be used if the memory to memory
  93. data transfer direction is configured on the selected Channel
  94. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
  95. uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
  96. is incremented or not.
  97. This parameter can be a value of @ref DMA_LL_EC_PERIPH
  98. This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
  99. uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
  100. is incremented or not.
  101. This parameter can be a value of @ref DMA_LL_EC_MEMORY
  102. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
  103. uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
  104. in case of memory to memory transfer direction.
  105. This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
  106. This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
  107. uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
  108. in case of memory to memory transfer direction.
  109. This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
  110. This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
  111. uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
  112. The data unit is equal to the source buffer configuration set in PeripheralSize
  113. or MemorySize parameters depending in the transfer direction.
  114. This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
  115. This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
  116. uint32_t PeriphRequest; /*!< Specifies the peripheral request.
  117. This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
  118. This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
  119. uint32_t Priority; /*!< Specifies the channel priority level.
  120. This parameter can be a value of @ref DMA_LL_EC_PRIORITY
  121. This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
  122. } LL_DMA_InitTypeDef;
  123. /**
  124. * @}
  125. */
  126. #endif /*USE_FULL_LL_DRIVER*/
  127. /* Exported constants --------------------------------------------------------*/
  128. /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
  129. * @{
  130. */
  131. /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
  132. * @brief Flags defines which can be used with LL_DMA_WriteReg function
  133. * @{
  134. */
  135. #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
  136. #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
  137. #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
  138. #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
  139. #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
  140. #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
  141. #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
  142. #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
  143. #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
  144. #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
  145. #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
  146. #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
  147. #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
  148. #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
  149. #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
  150. #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
  151. #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
  152. #define LL_DMA_IFCR_CTCIF5