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  1. /**
  2. ******************************************************************************
  3. * @file stm32l4xx_ll_sdmmc.c
  4. * @author MCD Application Team
  5. * @version V1.3.0
  6. * @date 29-January-2016
  7. * @brief SDMMC Low Layer HAL module driver.
  8. * This file provides firmware functions to manage the following
  9. * functionalities of the SDMMC peripheral:
  10. * + Initialization/de-initialization functions
  11. * + I/O operation functions
  12. * + Peripheral Control functions
  13. * + Peripheral State functions
  14. *
  15. @verbatim
  16. ==============================================================================
  17. ##### SDMMC peripheral features #####
  18. ==============================================================================
  19. [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
  20. peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
  21. devices.
  22. [..] The SDMMC features include the following:
  23. (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
  24. for three different data bus modes: 1-bit (default), 4-bit and 8-bit
  25. (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
  26. (+) Full compliance with SD Memory Card Specifications Version 2.0
  27. (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
  28. different data bus modes: 1-bit (default) and 4-bit
  29. (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
  30. Rev1.1)
  31. (+) Data transfer up to 48 MHz for the 8 bit mode
  32. (+) Data and command output enable signals to control external bidirectional drivers.
  33. ##### How to use this driver #####
  34. ==============================================================================
  35. [..]
  36. This driver is a considered as a driver of service for external devices drivers
  37. that interfaces with the SDMMC peripheral.
  38. According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs
  39. is used in the device's driver to perform SDMMC operations and functionalities.
  40. This driver is almost transparent for the final user, it is only used to implement other
  41. functionalities of the external device.
  42. [..]
  43. (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
  44. PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
  45. PLL is well configured.
  46. The SDMMC peripheral uses two clock signals:
  47. (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
  48. (++) APB2 bus clock (PCLK2)
  49. -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
  50. Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
  51. (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
  52. peripheral.
  53. (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx)
  54. function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
  55. (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
  56. (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT)
  57. and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode.
  58. (+) When using the DMA mode
  59. (++) Configure the DMA in the MSP layer of the external device
  60. (++) Active the needed channel Request
  61. (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
  62. __SDMMC_DMA_DISABLE().
  63. (+) To control the CPSM (Command Path State Machine) and send
  64. commands to the card use the SDMMC_SendCommand(SDMMCx),
  65. SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
  66. to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according
  67. to the selected command to be sent.
  68. The parameters that should be filled are:
  69. (++) Command Argument
  70. (++) Command Index
  71. (++) Command Response type
  72. (++) Command Wait
  73. (++) CPSM Status (Enable or Disable).
  74. -@@- To check if the command is well received, read the SDMMC_CMDRESP
  75. register using the SDMMC_GetCommandResponse().
  76. The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
  77. SDMMC_GetResponse() function.
  78. (+) To control the DPSM (Data Path State Machine) and send/receive
  79. data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(),
  80. SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
  81. *** Read Operations ***
  82. =======================
  83. [..]
  84. (#) First, user has to fill the data structure (pointer to
  85. SDMMC_DataInitTypeDef) according to the selected data type to be received.
  86. The parameters that should be filled are:
  87. (++) Data TimeOut
  88. (++) Data Length
  89. (++) Data Block size
  90. (++) Data Transfer direction: should be from card (To SDMMC)
  91. (++) Data Transfer mode
  92. (++) DPSM Status (Enable or Disable)
  93. (#) Configure the SDMMC resources to receive the data from the card
  94. according to selected transfer mode (Refer to Step 8, 9 and 10).
  95. (#) Send the selected Read command (refer to step 11).
  96. (#) Use the SDMMC flags/interrupts to check the transfer status.
  97. *** Write Operations ***
  98. ========================
  99. [..]
  100. (#) First, user has to fill the data structure (pointer to
  101. SDMMC_DataInitTypeDef) according to the selected data type to be received.
  102. The parameters that should be filled are:
  103. (++) Data TimeOut
  104. (++) Data Length
  105. (++) Data Block size
  106. (++) Data Transfer direction: should be to card (To CARD)
  107. (++) Data Transfer mode
  108. (++) DPSM Status (Enable or Disable)
  109. (#) Configure the SDMMC resources to send the data to the card according to
  110. selected transfer mode.
  111. (#) Send the selected Write command.
  112. (#) Use the SDMMC flags/interrupts to check the transfer status.
  113. @endverbatim
  114. ******************************************************************************
  115. * @attention
  116. *
  117. * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  118. *
  119. * Redistribution and use in source and binary forms, with or without modification,
  120. * are permitted provided that the following conditions are met:
  121. * 1. Redistributions of source code must retain the above copyright notice,
  122. * this list of conditions and the following disclaimer.
  123. * 2. Redistributions in binary form must reproduce the above copyright notice,
  124. * this list of conditions and the following disclaimer in the documentation
  125. * and/or other materials provided with the distribution.
  126. * 3. Neither the name of STMicroelectronics nor the names of its contributors
  127. * may be used to endorse or promote products derived from this software
  128. * without specific prior written permission.
  129. *
  130. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  131. * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  132. * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  133. * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  134. * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  135. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  136. * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  137. * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  138. * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  139. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  140. *
  141. ******************************************************************************
  142. */
  143. /* Includes ------------------------------------------------------------------*/
  144. #include "stm32l4xx_hal.h"
  145. /** @addtogroup STM32L4xx_HAL_Driver
  146. * @{
  147. */
  148. /** @defgroup SDMMC_LL SDMMC Low Layer
  149. * @brief Low layer module for SD
  150. * @{
  151. */
  152. #if defined (HAL_SD_MODULE_ENABLED)
  153. /* Private typedef -----------------------------------------------------------*/
  154. /* Private define ------------------------------------------------------------*/
  155. /* Private macro -------------------------------------------------------------*/
  156. /* Private variables ---------------------------------------------------------*/
  157. /* Private function prototypes -----------------------------------------------*/
  158. /* Exported functions --------------------------------------------------------*/
  159. /** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
  160. * @{
  161. */
  162. /** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions
  163. * @brief Initialization and Configuration functions
  164. *
  165. @verbatim
  166. ===============================================================================
  167. ##### Initialization/de-initialization functions #####
  168. ===============================================================================
  169. [..] This section provides functions allowing to:
  170. @endverbatim
  171. * @{
  172. */
  173. /**
  174. * @brief Initializes the SDMMC according to the specified
  175. * parameters in the SDMMC_InitTypeDef and initialize the associated handle.
  176. * @param SDMMCx: Pointer to SDMMC register base
  177. * @param Init: SDMMC initialization structure
  178. * @retval HAL status
  179. */
  180. HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
  181. {
  182. /* Check the parameters */
  183. assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
  184. assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge));
  185. assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
  186. assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
  187. assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
  188. assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
  189. assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
  190. /* Set SDMMC configuration parameters */
  191. /* Write to SDMMC CLKCR */
  192. MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge |\
  193. Init.ClockBypass |\
  194. Init.ClockPowerSave |\
  195. Init.BusWide |\
  196. Init.HardwareFlowControl |\
  197. Init.ClockDiv);
  198. return HAL_OK;
  199. }
  200. /**
  201. * @}
  202. */
  203. /** @defgroup HAL_SDMMC_LL_Group2 IO operation functions
  204. * @brief Data transfers functions
  205. *
  206. @verbatim
  207. ===============================================================================
  208. ##### I/O operation functions #####
  209. ===============================================================================
  210. [..]
  211. This subsection provides a set of functions allowing to manage the SDMMC data
  212. transfers.
  213. @endverbatim
  214. * @{
  215. */
  216. /**
  217. * @brief Read data (word) from Rx FIFO in blocking mode (polling)
  218. * @param SDMMCx: Pointer to SDMMC register base
  219. * @retval HAL status
  220. */
  221. uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
  222. {
  223. /* Read data from Rx FIFO */
  224. return (SDMMCx->FIFO);
  225. }
  226. /**
  227. * @brief Write data (word) to Tx FIFO in blocking mode (polling)
  228. * @param SDMMCx: Pointer to SDMMC register base
  229. * @param pWriteData: pointer to data to write
  230. * @retval HAL status
  231. */
  232. HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
  233. {
  234. /* Write data to FIFO */
  235. SDMMCx->FIFO = *pWriteData;
  236. return HAL_OK;
  237. }
  238. /**
  239. * @}
  240. */
  241. /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
  242. * @brief management functions
  243. *
  244. @verbatim
  245. ===============================================================================
  246. ##### Peripheral Control functions #####
  247. ===============================================================================
  248. [..]
  249. This subsection provides a set of functions allowing to control the SDMMC data
  250. transfers.
  251. @endverbatim
  252. * @{
  253. */
  254. /**
  255. * @brief Set SDMMC Power state to ON.
  256. * @param SDMMCx: Pointer to SDMMC register base
  257. * @retval HAL status
  258. */
  259. HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
  260. {
  261. /* Set power state to ON */
  262. SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
  263. return HAL_OK;
  264. }
  265. /**
  266. * @brief Set SDMMC Power state to OFF.
  267. * @param SDMMCx: Pointer to SDMMC register base
  268. * @retval HAL status
  269. */
  270. HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
  271. {
  272. /* Set power state to OFF */
  273. SDMMCx->POWER = (uint32_t)0x00000000;
  274. return HAL_OK;
  275. }
  276. /**
  277. * @brief Get SDMMC Power state.
  278. * @param SDMMCx: Pointer to SDMMC register base
  279. * @retval Power status of the controller. The returned value can be one of the
  280. * following values:
  281. * - 0x00: Power OFF
  282. * - 0x02: Power UP
  283. * - 0x03: Power ON
  284. */
  285. uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)
  286. {
  287. return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
  288. }
  289. /**
  290. * @brief Configure the SDMMC command path according to the specified parameters in
  291. * SDMMC_CmdInitTypeDef structure and send the command
  292. * @param SDMMCx: Pointer to SDMMC register base
  293. * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
  294. * the configuration information for the SDMMC command
  295. * @retval HAL status
  296. */
  297. HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
  298. {
  299. /* Check the parameters */
  300. assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
  301. assert_param(IS_SDMMC_RESPONSE(Command->Response));
  302. assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
  303. assert_param(IS_SDMMC_CPSM(Command->CPSM));
  304. /* Set the SDMMC Argument value */
  305. SDMMCx->ARG = Command->Argument;
  306. /* Set SDMMC command parameters */
  307. /* Write to SDMMC CMD register */
  308. MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, Command->CmdIndex |\
  309. Command->Response |\
  310. Command->WaitForInterrupt |\
  311. Command->CPSM);
  312. return HAL_OK;
  313. }
  314. /**
  315. * @brief Return the command index of last command for which response received
  316. * @param SDMMCx: Pointer to SDMMC register base
  317. * @retval Command index of the last command response received
  318. */
  319. uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
  320. {
  321. return (uint8_t)(SDMMCx->RESPCMD);
  322. }
  323. /**
  324. * @brief Return the response received from the card for the last command
  325. * @param SDMMCx: Pointer to SDMMC register base
  326. * @param Response: Specifies the SDMMC response register.
  327. * This parameter can be one of the following values:
  328. * @arg SDMMC_RESP1: Response Register 1
  329. * @arg SDMMC_RESP2: Response Register 2
  330. * @arg SDMMC_RESP3: Response Register 3
  331. * @arg SDMMC_RESP4: Response Register 4
  332. * @retval The Corresponding response register value
  333. */
  334. uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
  335. {
  336. __IO uint32_t tmp = 0;
  337. /* Check the parameters */
  338. assert_param(IS_SDMMC_RESP(Response));
  339. /* Get the response */
  340. tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
  341. return (*(__IO uint32_t *) tmp);
  342. }
  343. /**
  344. * @brief Configure the SDMMC data path according to the specified
  345. * parameters in the SDMMC_DataInitTypeDef.
  346. * @param SDMMCx: Pointer to SDMMC register base
  347. * @param Data : pointer to a SDMMC_DataInitTypeDef structure
  348. * that contains the configuration information for the SDMMC data.
  349. * @retval HAL status
  350. */
  351. HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
  352. {
  353. /* Check the parameters */
  354. assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
  355. assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
  356. assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
  357. assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
  358. assert_param(IS_SDMMC_DPSM(Data->DPSM));
  359. /* Set the SDMMC Data TimeOut value */
  360. SDMMCx->DTIMER = Data->DataTimeOut;
  361. /* Set the SDMMC DataLength value */
  362. SDMMCx->DLEN = Data->DataLength;
  363. /* Set the SDMMC data configuration parameters */
  364. /* Write to SDMMC DCTRL */
  365. MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\
  366. Data->TransferDir |\
  367. Data->TransferMode |\
  368. Data->DPSM);
  369. return HAL_OK;
  370. }
  371. /**
  372. * @brief Returns number of remaining data bytes to be transferred.
  373. * @param SDMMCx: Pointer to SDMMC register base
  374. * @retval Number of remaining data bytes to be transferred
  375. */
  376. uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
  377. {
  378. return (SDMMCx->DCOUNT);
  379. }
  380. /**
  381. * @brief Get the FIFO data
  382. * @param SDMMCx: Pointer to SDMMC register base
  383. * @retval Data received
  384. */
  385. uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
  386. {
  387. return (SDMMCx->FIFO);
  388. }
  389. /**
  390. * @brief Sets one of the two options of inserting read wait interval.
  391. * @param SDMMCx: Pointer to SDMMC register base
  392. * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
  393. * This parameter can be:
  394. * @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
  395. * @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
  396. * @retval None
  397. */
  398. HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
  399. {
  400. /* Check the parameters */
  401. assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
  402. /* Set SDMMC read wait mode */
  403. MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode);
  404. return HAL_OK;
  405. }
  406. /**
  407. * @}
  408. */
  409. /**
  410. * @}
  411. */
  412. #endif /* (HAL_SD_MODULE_ENABLED) */
  413. /**
  414. * @}
  415. */
  416. /**
  417. * @}
  418. */
  419. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/