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stm32lib/STM32L0xx_HAL_Driver/Inc/stm32l0xx_ll_bus.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32l0xx_ll_bus.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of BUS LL module.

  6. 

  7.   @verbatim

  8.                       ##### RCC Limitations #####

  9.   ==============================================================================

  10.     [..]

  11.       A delay between an RCC peripheral clock enable and the effective peripheral

  12.       enabling should be taken into account in order to manage the peripheral read/write

  13.       from/to registers.

  14.       (+) This delay depends on the peripheral mapping.

  15.         (++) AHB & APB peripherals, 1 dummy read is necessary

  16. 

  17.     [..]

  18.       Workarounds:

  19.       (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

  20.           inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

  21. 

  22.   @endverbatim

  23.   ******************************************************************************

  24.   * @attention

  25.   *

  26.   * <h2><center>&copy; Copyright(c) 2016 STMicroelectronics.

  27.   * All rights reserved.</center></h2>

  28.   *

  29.   * This software component is licensed by ST under BSD 3-Clause license,

  30.   * the "License"; You may not use this file except in compliance with the

  31.   * License. You may obtain a copy of the License at:

  32.   *                        opensource.org/licenses/BSD-3-Clause

  33.   *

  34.   ******************************************************************************

  35.   */

  36. 

  37. /* Define to prevent recursive inclusion -------------------------------------*/

  38. #ifndef __STM32L0xx_LL_BUS_H

  39. #define __STM32L0xx_LL_BUS_H

  40. 

  41. #ifdef __cplusplus

  42. extern "C" {

  43. #endif

  44. 

  45. /* Includes ------------------------------------------------------------------*/

  46. #include "stm32l0xx.h"

  47. 

  48. /** @addtogroup STM32L0xx_LL_Driver

  49.   * @{

  50.   */

  51. 

  52. #if defined(RCC)

  53. 

  54. /** @defgroup BUS_LL BUS

  55.   * @{

  56.   */

  57. 

  58. /* Private types -------------------------------------------------------------*/

  59. /* Private variables ---------------------------------------------------------*/

  60. 

  61. /* Private constants ---------------------------------------------------------*/

  62. 

  63. /* Private macros ------------------------------------------------------------*/

  64. 

  65. /* Exported types ------------------------------------------------------------*/

  66. /* Exported constants --------------------------------------------------------*/

  67. /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants

  68.   * @{

  69.   */

  70. 

  71. /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH

  72.   * @{

  73.   */

  74. #define LL_AHB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU

  75. #define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHBENR_DMA1EN      /*!< DMA1 clock enable */

  76. #define LL_AHB1_GRP1_PERIPH_MIF            RCC_AHBENR_MIFEN       /*!< MIF clock enable */

  77. #define LL_AHB1_GRP1_PERIPH_SRAM           RCC_AHBSMENR_SRAMSMEN  /*!< Sleep Mode SRAM clock enable */

  78. #define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHBENR_CRCEN       /*!< CRC clock enable */

  79. #if defined(TSC)

  80. #define LL_AHB1_GRP1_PERIPH_TSC            RCC_AHBENR_TSCEN       /*!< TSC clock enable */

  81. #endif /*TSC*/

  82. #if defined(RNG)

  83. #define LL_AHB1_GRP1_PERIPH_RNG            RCC_AHBENR_RNGEN       /*!< RNG clock enable */

  84. #endif /*RNG*/

  85. #if defined(AES)

  86. #define LL_AHB1_GRP1_PERIPH_CRYP           RCC_AHBENR_CRYPEN      /*!< CRYP clock enable */

  87. #endif /*AES*/

  88. /**

  89.   * @}

  90.   */

  91. 

  92. 

  93. /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH

  94.   * @{

  95.   */

  96. #define LL_APB1_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU

  97. #define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1ENR_TIM2EN     /*!< TIM2 clock enable */

  98. #if defined(TIM3)

  99. #define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1ENR_TIM3EN     /*!< TIM3 clock enable */

  100. #endif

  101. #if defined(TIM6)

  102. #define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1ENR_TIM6EN     /*!< TIM6 clock enable */

  103. #endif

  104. #if defined(TIM7)

  105. #define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1ENR_TIM7EN     /*!< TIM7 clock enable */

  106. #endif

  107. #if defined(LCD)

  108. #define LL_APB1_GRP1_PERIPH_LCD            RCC_APB1ENR_LCDEN      /*!< LCD clock enable */

  109. #endif /*LCD*/

  110. #define LL_APB1_GRP1_PERIPH_WWDG           RCC_APB1ENR_WWDGEN     /*!< WWDG clock enable */

  111. #if defined(SPI2)

  112. #define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1ENR_SPI2EN     /*!< SPI2 clock enable */

  113. #endif

  114. #define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1ENR_USART2EN   /*!< USART2 clock enable */

  115. #define LL_APB1_GRP1_PERIPH_LPUART1        RCC_APB1ENR_LPUART1EN  /*!< LPUART1 clock enable */

  116. #if defined(USART4)

  117. #define LL_APB1_GRP1_PERIPH_USART4         RCC_APB1ENR_USART4EN   /*!< USART4 clock enable */

  118. #endif

  119. #if defined(USART5)

  120. #define LL_APB1_GRP1_PERIPH_USART5         RCC_APB1ENR_USART5EN   /*!< USART5 clock enable */

  121. #endif

  122. #define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1ENR_I2C1EN     /*!< I2C1 clock enable */

  123. #if defined(I2C2)

  124. #define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1ENR_I2C2EN     /*!< I2C2 clock enable */

  125. #endif

  126. #if defined(USB)

  127. #define LL_APB1_GRP1_PERIPH_USB            RCC_APB1ENR_USBEN      /*!< USB clock enable */

  128. #endif /*USB*/

  129. #if defined(CRS)

  130. #define LL_APB1_GRP1_PERIPH_CRS            RCC_APB1ENR_CRSEN      /*!< CRS clock enable */

  131. #endif /*CRS*/

  132. #define LL_APB1_GRP1_PERIPH_PWR            RCC_APB1ENR_PWREN      /*!< PWR clock enable */

  133. #if defined(DAC)

  134. #define LL_APB1_GRP1_PERIPH_DAC1           RCC_APB1ENR_DACEN      /*!< DAC clock enable */

  135. #endif

  136. #if defined(I2C3)

  137. #define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1ENR_I2C3EN     /*!< I2C3 clock enable */

  138. #endif

  139. #define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1ENR_LPTIM1EN   /*!< LPTIM1 clock enable */

  140. /**

  141.   * @}

  142.   */

  143. 

  144. 

  145. 

  146. 

  147. /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH

  148.   * @{

  149.   */

  150. #define LL_APB2_GRP1_PERIPH_ALL            (uint32_t)0xFFFFFFFFU

  151. #define LL_APB2_GRP1_PERIPH_SYSCFG         RCC_APB2ENR_SYSCFGEN  /*!< SYSCFG clock enable */

  152. #define LL_APB2_GRP1_PERIPH_TIM21          RCC_APB2ENR_TIM21EN   /*!< TIM21 clock enable */

  153. #if defined(TIM22)

  154. #define LL_APB2_GRP1_PERIPH_TIM22          RCC_APB2ENR_TIM22EN   /*!< TIM22 clock enable */

  155. #endif

  156. #define LL_APB2_GRP1_PERIPH_FW             RCC_APB2ENR_FWEN      /*!< FireWall clock enable */

  157. #define LL_APB2_GRP1_PERIPH_ADC1           RCC_APB2ENR_ADC1EN    /*!< ADC1 clock enable */

  158. #define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN    /*!< SPI1 clock enable */

  159. #if defined(USART1)

  160. #define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN  /*!< USART1 clock enable */

  161. #endif

  162. #define LL_APB2_GRP1_PERIPH_DBGMCU         RCC_APB2ENR_DBGMCUEN  /*!< DBGMCU clock enable */

  163. 

  164. /**

  165.   * @}

  166.   */

  167. 

  168. 

  169. 

  170. /** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH  IOP GRP1 PERIPH

  171.   * @{

  172.   */

  173. #define LL_IOP_GRP1_PERIPH_ALL             (uint32_t)0xFFFFFFFFU

  174. #define LL_IOP_GRP1_PERIPH_GPIOA           RCC_IOPENR_GPIOAEN    /*!< GPIO port A control */

  175. #define LL_IOP_GRP1_PERIPH_GPIOB           RCC_IOPENR_GPIOBEN    /*!< GPIO port B control */

  176. #define LL_IOP_GRP1_PERIPH_GPIOC           RCC_IOPENR_GPIOCEN    /*!< GPIO port C control */

  177. #if defined(GPIOD)

  178. #define LL_IOP_GRP1_PERIPH_GPIOD           RCC_IOPENR_GPIODEN    /*!< GPIO port D control */

  179. #endif /*GPIOD*/

  180. #if defined(GPIOE)

  181. #define LL_IOP_GRP1_PERIPH_GPIOE           RCC_IOPENR_GPIOEEN    /*!< GPIO port H control */

  182. #endif /*GPIOE*/

  183. #if defined(GPIOH)

  184. #define LL_IOP_GRP1_PERIPH_GPIOH           RCC_IOPENR_GPIOHEN    /*!< GPIO port H control */

  185. #endif /*GPIOH*/

  186. /**

  187.   * @}

  188.   */

  189. 

  190. 

  191. /**

  192.   * @}

  193.   */

  194. 

  195. /* Exported macro ------------------------------------------------------------*/

  196. /* Exported functions --------------------------------------------------------*/

  197. /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions

  198.   * @{

  199.   */

  200. 

  201. /** @defgroup BUS_LL_EF_AHB1 AHB1

  202.   * @{

  203.   */

  204. 

  205. /**

  206.   * @brief  Enable AHB1 peripherals clock.

  207.   * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_EnableClock\n

  208.   *         AHBENR      MIFEN        LL_AHB1_GRP1_EnableClock\n

  209.   *         AHBENR      CRCEN        LL_AHB1_GRP1_EnableClock\n

  210.   *         AHBENR      TSCEN        LL_AHB1_GRP1_EnableClock\n

  211.   *         AHBENR      RNGEN        LL_AHB1_GRP1_EnableClock\n

  212.   *         AHBENR      CRYPEN       LL_AHB1_GRP1_EnableClock

  213.   * @param  Periphs This parameter can be a combination of the following values:

  214.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  215.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  216.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  217.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  218.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  219.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  220.   *

  221.   *         (*) value not defined in all devices.

  222.   * @retval None

  223. */

  224. __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)

  225. {

  226.   __IO uint32_t tmpreg;

  227.   SET_BIT(RCC->AHBENR, Periphs);

  228.   /* Delay after an RCC peripheral clock enabling */

  229.   tmpreg = READ_BIT(RCC->AHBENR, Periphs);

  230.   (void)tmpreg;

  231. }

  232. 

  233. /**

  234.   * @brief  Check if AHB1 peripheral clock is enabled or not

  235.   * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_IsEnabledClock\n

  236.   *         AHBENR      MIFEN        LL_AHB1_GRP1_IsEnabledClock\n

  237.   *         AHBENR      CRCEN        LL_AHB1_GRP1_IsEnabledClock\n

  238.   *         AHBENR      TSCEN        LL_AHB1_GRP1_IsEnabledClock\n

  239.   *         AHBENR      RNGEN        LL_AHB1_GRP1_IsEnabledClock\n

  240.   *         AHBENR      CRYPEN       LL_AHB1_GRP1_IsEnabledClock

  241.   * @param  Periphs This parameter can be a combination of the following values:

  242.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  243.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  244.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  245.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  246.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  247.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  248.   *

  249.   *         (*) value not defined in all devices.

  250.   * @retval State of Periphs (1 or 0).

  251. */

  252. __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

  253. {

  254.   return ((READ_BIT(RCC->AHBENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  255. }

  256. 

  257. /**

  258.   * @brief  Disable AHB1 peripherals clock.

  259.   * @rmtoll AHBENR      DMAEN        LL_AHB1_GRP1_DisableClock\n

  260.   *         AHBENR      MIFEN        LL_AHB1_GRP1_DisableClock\n

  261.   *         AHBENR      CRCEN        LL_AHB1_GRP1_DisableClock\n

  262.   *         AHBENR      TSCEN        LL_AHB1_GRP1_DisableClock\n

  263.   *         AHBENR      RNGEN        LL_AHB1_GRP1_DisableClock\n

  264.   *         AHBENR      CRYPEN       LL_AHB1_GRP1_DisableClock

  265.   * @param  Periphs This parameter can be a combination of the following values:

  266.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  267.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  268.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  269.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  270.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  271.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  272.   *

  273.   *         (*) value not defined in all devices.

  274.   * @retval None

  275. */

  276. __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)

  277. {

  278.   CLEAR_BIT(RCC->AHBENR, Periphs);

  279. }

  280. 

  281. /**

  282.   * @brief  Force AHB1 peripherals reset.

  283.   * @rmtoll AHBRSTR      DMARST        LL_AHB1_GRP1_ForceReset\n

  284.   *         AHBRSTR      MIFRST        LL_AHB1_GRP1_ForceReset\n

  285.   *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ForceReset\n

  286.   *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ForceReset\n

  287.   *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ForceReset\n

  288.   *         AHBRSTR      CRYPRST       LL_AHB1_GRP1_ForceReset

  289.   * @param  Periphs This parameter can be a combination of the following values:

  290.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL

  291.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  292.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  293.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  294.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  295.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  296.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  297.   *

  298.   *         (*) value not defined in all devices.

  299.   * @retval None

  300. */

  301. __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)

  302. {

  303.   SET_BIT(RCC->AHBRSTR, Periphs);

  304. }

  305. 

  306. /**

  307.   * @brief  Release AHB1 peripherals reset.

  308.   * @rmtoll AHBRSTR      DMARST        LL_AHB1_GRP1_ReleaseReset\n

  309.   *         AHBRSTR      MIFRST        LL_AHB1_GRP1_ReleaseReset\n

  310.   *         AHBRSTR      CRCRST        LL_AHB1_GRP1_ReleaseReset\n

  311.   *         AHBRSTR      TSCRST        LL_AHB1_GRP1_ReleaseReset\n

  312.   *         AHBRSTR      RNGRST        LL_AHB1_GRP1_ReleaseReset\n

  313.   *         AHBRSTR      CRYPRST       LL_AHB1_GRP1_ReleaseReset

  314.   * @param  Periphs This parameter can be a combination of the following values:

  315.   *         @arg @ref LL_AHB1_GRP1_PERIPH_ALL

  316.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  317.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  318.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  319.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  320.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  321.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  322.   *

  323.   *         (*) value not defined in all devices.

  324.   * @retval None

  325. */

  326. __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)

  327. {

  328.   CLEAR_BIT(RCC->AHBRSTR, Periphs);

  329. }

  330. 

  331. /**

  332.   * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.

  333.   * @rmtoll AHBSMENR     DMASMEN       LL_AHB1_GRP1_EnableClockSleep\n

  334.   *         AHBSMENR     MIFSMEN       LL_AHB1_GRP1_EnableClockSleep\n

  335.   *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_EnableClockSleep\n

  336.   *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_EnableClockSleep\n

  337.   *         AHBSMENR     TSCSMEN       LL_AHB1_GRP1_EnableClockSleep\n

  338.   *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_EnableClockSleep\n

  339.   *         AHBSMENR     CRYPSMEN      LL_AHB1_GRP1_EnableClockSleep

  340.   * @param  Periphs This parameter can be a combination of the following values:

  341.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  342.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  343.   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM

  344.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  345.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  346.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  347.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  348.   *

  349.   *         (*) value not defined in all devices.

  350.   * @retval None

  351. */

  352. __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

  353. {

  354.   __IO uint32_t tmpreg;

  355.   SET_BIT(RCC->AHBSMENR, Periphs);

  356.   /* Delay after an RCC peripheral clock enabling */

  357.   tmpreg = READ_BIT(RCC->AHBSMENR, Periphs);

  358.   (void)tmpreg;

  359. }

  360. 

  361. /**

  362.   * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.

  363.   * @rmtoll AHBSMENR     DMASMEN       LL_AHB1_GRP1_DisableClockSleep\n

  364.   *         AHBSMENR     MIFSMEN       LL_AHB1_GRP1_DisableClockSleep\n

  365.   *         AHBSMENR     SRAMSMEN      LL_AHB1_GRP1_DisableClockSleep\n

  366.   *         AHBSMENR     CRCSMEN       LL_AHB1_GRP1_DisableClockSleep\n

  367.   *         AHBSMENR     TSCSMEN       LL_AHB1_GRP1_DisableClockSleep\n

  368.   *         AHBSMENR     RNGSMEN       LL_AHB1_GRP1_DisableClockSleep\n

  369.   *         AHBSMENR     CRYPSMEN      LL_AHB1_GRP1_DisableClockSleep

  370.   * @param  Periphs This parameter can be a combination of the following values:

  371.   *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

  372.   *         @arg @ref LL_AHB1_GRP1_PERIPH_MIF

  373.   *         @arg @ref LL_AHB1_GRP1_PERIPH_SRAM

  374.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC

  375.   *         @arg @ref LL_AHB1_GRP1_PERIPH_TSC (*)

  376.   *         @arg @ref LL_AHB1_GRP1_PERIPH_RNG (*)

  377.   *         @arg @ref LL_AHB1_GRP1_PERIPH_CRYP (*)

  378.   *

  379.   *         (*) value not defined in all devices.

  380.   * @retval None

  381. */

  382. __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

  383. {

  384.   CLEAR_BIT(RCC->AHBSMENR, Periphs);

  385. }

  386. 

  387. /**

  388.   * @}

  389.   */

  390. 

  391. /** @defgroup BUS_LL_EF_APB1 APB1

  392.   * @{

  393.   */

  394. 

  395. /**

  396.   * @brief  Enable APB1 peripherals clock.

  397.   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_EnableClock\n

  398.   *         APB1ENR     TIM3EN        LL_APB1_GRP1_EnableClock\n

  399.   *         APB1ENR     TIM6EN        LL_APB1_GRP1_EnableClock\n

  400.   *         APB1ENR     TIM7EN        LL_APB1_GRP1_EnableClock\n

  401.   *         APB1ENR     LCDEN         LL_APB1_GRP1_EnableClock\n

  402.   *         APB1ENR     WWDGEN        LL_APB1_GRP1_EnableClock\n

  403.   *         APB1ENR     SPI2EN        LL_APB1_GRP1_EnableClock\n

  404.   *         APB1ENR     USART2EN      LL_APB1_GRP1_EnableClock\n

  405.   *         APB1ENR     LPUART1EN     LL_APB1_GRP1_EnableClock\n

  406.   *         APB1ENR     USART4EN      LL_APB1_GRP1_EnableClock\n

  407.   *         APB1ENR     USART5EN      LL_APB1_GRP1_EnableClock\n

  408.   *         APB1ENR     I2C1EN        LL_APB1_GRP1_EnableClock\n

  409.   *         APB1ENR     I2C2EN        LL_APB1_GRP1_EnableClock\n

  410.   *         APB1ENR     USBEN         LL_APB1_GRP1_EnableClock\n

  411.   *         APB1ENR     CRSEN         LL_APB1_GRP1_EnableClock\n

  412.   *         APB1ENR     PWREN         LL_APB1_GRP1_EnableClock\n

  413.   *         APB1ENR     DACEN         LL_APB1_GRP1_EnableClock\n

  414.   *         APB1ENR     I2C3EN        LL_APB1_GRP1_EnableClock\n

  415.   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_EnableClock

  416.   * @param  Periphs This parameter can be a combination of the following values:

  417.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  418.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  419.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  420.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  421.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  422.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  423.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  424.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  425.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  426.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  427.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  428.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  429.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  430.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  431.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  432.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  433.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  434.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  435.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  436.   *

  437.   *         (*) value not defined in all devices.

  438.   * @retval None

  439. */

  440. __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)

  441. {

  442.   __IO uint32_t tmpreg;

  443.   SET_BIT(RCC->APB1ENR, Periphs);

  444.   /* Delay after an RCC peripheral clock enabling */

  445.   tmpreg = READ_BIT(RCC->APB1ENR, Periphs);

  446.   (void)tmpreg;

  447. }

  448. 

  449. /**

  450.   * @brief  Check if APB1 peripheral clock is enabled or not

  451.   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n

  452.   *         APB1ENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n

  453.   *         APB1ENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n

  454.   *         APB1ENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n

  455.   *         APB1ENR     LCDEN         LL_APB1_GRP1_IsEnabledClock\n

  456.   *         APB1ENR     WWDGEN        LL_APB1_GRP1_IsEnabledClock\n

  457.   *         APB1ENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n

  458.   *         APB1ENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n

  459.   *         APB1ENR     LPUART1EN     LL_APB1_GRP1_IsEnabledClock\n

  460.   *         APB1ENR     USART4EN      LL_APB1_GRP1_IsEnabledClock\n

  461.   *         APB1ENR     USART5EN      LL_APB1_GRP1_IsEnabledClock\n

  462.   *         APB1ENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n

  463.   *         APB1ENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n

  464.   *         APB1ENR     USBEN         LL_APB1_GRP1_IsEnabledClock\n

  465.   *         APB1ENR     CRSEN         LL_APB1_GRP1_IsEnabledClock\n

  466.   *         APB1ENR     PWREN         LL_APB1_GRP1_IsEnabledClock\n

  467.   *         APB1ENR     DACEN         LL_APB1_GRP1_IsEnabledClock\n

  468.   *         APB1ENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n

  469.   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock

  470.   * @param  Periphs This parameter can be a combination of the following values:

  471.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  472.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  473.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  474.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  475.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  476.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  477.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  478.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  479.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  480.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  481.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  482.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  483.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  484.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  485.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  486.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  487.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  488.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  489.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  490.   *

  491.   *         (*) value not defined in all devices.

  492.   * @retval State of Periphs (1 or 0).

  493. */

  494. __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

  495. {

  496.   return ((READ_BIT(RCC->APB1ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  497. }

  498. 

  499. /**

  500.   * @brief  Disable APB1 peripherals clock.

  501.   * @rmtoll APB1ENR     TIM2EN        LL_APB1_GRP1_DisableClock\n

  502.   *         APB1ENR     TIM3EN        LL_APB1_GRP1_DisableClock\n

  503.   *         APB1ENR     TIM6EN        LL_APB1_GRP1_DisableClock\n

  504.   *         APB1ENR     TIM7EN        LL_APB1_GRP1_DisableClock\n

  505.   *         APB1ENR     LCDEN         LL_APB1_GRP1_DisableClock\n

  506.   *         APB1ENR     WWDGEN        LL_APB1_GRP1_DisableClock\n

  507.   *         APB1ENR     SPI2EN        LL_APB1_GRP1_DisableClock\n

  508.   *         APB1ENR     USART2EN      LL_APB1_GRP1_DisableClock\n

  509.   *         APB1ENR     LPUART1EN     LL_APB1_GRP1_DisableClock\n

  510.   *         APB1ENR     USART4EN      LL_APB1_GRP1_DisableClock\n

  511.   *         APB1ENR     USART5EN      LL_APB1_GRP1_DisableClock\n

  512.   *         APB1ENR     I2C1EN        LL_APB1_GRP1_DisableClock\n

  513.   *         APB1ENR     I2C2EN        LL_APB1_GRP1_DisableClock\n

  514.   *         APB1ENR     USBEN         LL_APB1_GRP1_DisableClock\n

  515.   *         APB1ENR     CRSEN         LL_APB1_GRP1_DisableClock\n

  516.   *         APB1ENR     PWREN         LL_APB1_GRP1_DisableClock\n

  517.   *         APB1ENR     DACEN         LL_APB1_GRP1_DisableClock\n

  518.   *         APB1ENR     I2C3EN        LL_APB1_GRP1_DisableClock\n

  519.   *         APB1ENR     LPTIM1EN      LL_APB1_GRP1_DisableClock

  520.   * @param  Periphs This parameter can be a combination of the following values:

  521.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  522.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  523.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  524.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  525.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  526.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  527.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  528.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  529.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  530.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  531.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  532.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  533.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  534.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  535.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  536.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  537.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  538.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  539.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  540.   *

  541.   *         (*) value not defined in all devices.

  542.   * @retval None

  543. */

  544. __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)

  545. {

  546.   CLEAR_BIT(RCC->APB1ENR, Periphs);

  547. }

  548. 

  549. /**

  550.   * @brief  Force APB1 peripherals reset.

  551.   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ForceReset\n

  552.   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ForceReset\n

  553.   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ForceReset\n

  554.   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ForceReset\n

  555.   *         APB1RSTR     LCDRST         LL_APB1_GRP1_ForceReset\n

  556.   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ForceReset\n

  557.   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ForceReset\n

  558.   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ForceReset\n

  559.   *         APB1RSTR     LPUART1RST     LL_APB1_GRP1_ForceReset\n

  560.   *         APB1RSTR     USART4RST      LL_APB1_GRP1_ForceReset\n

  561.   *         APB1RSTR     USART5RST      LL_APB1_GRP1_ForceReset\n

  562.   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ForceReset\n

  563.   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ForceReset\n

  564.   *         APB1RSTR     USBRST         LL_APB1_GRP1_ForceReset\n

  565.   *         APB1RSTR     CRSRST         LL_APB1_GRP1_ForceReset\n

  566.   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ForceReset\n

  567.   *         APB1RSTR     DACRST         LL_APB1_GRP1_ForceReset\n

  568.   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ForceReset\n

  569.   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ForceReset

  570.   * @param  Periphs This parameter can be a combination of the following values:

  571.   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL

  572.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  573.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  574.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  575.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  576.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  577.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  578.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  579.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  580.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  581.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  582.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  583.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  584.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  585.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  586.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  587.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  588.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  589.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  590.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  591.   *

  592.   *         (*) value not defined in all devices.

  593.   * @retval None

  594. */

  595. __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)

  596. {

  597.   SET_BIT(RCC->APB1RSTR, Periphs);

  598. }

  599. 

  600. /**

  601.   * @brief  Release APB1 peripherals reset.

  602.   * @rmtoll APB1RSTR     TIM2RST        LL_APB1_GRP1_ReleaseReset\n

  603.   *         APB1RSTR     TIM3RST        LL_APB1_GRP1_ReleaseReset\n

  604.   *         APB1RSTR     TIM6RST        LL_APB1_GRP1_ReleaseReset\n

  605.   *         APB1RSTR     TIM7RST        LL_APB1_GRP1_ReleaseReset\n

  606.   *         APB1RSTR     LCDRST         LL_APB1_GRP1_ReleaseReset\n

  607.   *         APB1RSTR     WWDGRST        LL_APB1_GRP1_ReleaseReset\n

  608.   *         APB1RSTR     SPI2RST        LL_APB1_GRP1_ReleaseReset\n

  609.   *         APB1RSTR     USART2RST      LL_APB1_GRP1_ReleaseReset\n

  610.   *         APB1RSTR     LPUART1RST     LL_APB1_GRP1_ReleaseReset\n

  611.   *         APB1RSTR     USART4RST      LL_APB1_GRP1_ReleaseReset\n

  612.   *         APB1RSTR     USART5RST      LL_APB1_GRP1_ReleaseReset\n

  613.   *         APB1RSTR     I2C1RST        LL_APB1_GRP1_ReleaseReset\n

  614.   *         APB1RSTR     I2C2RST        LL_APB1_GRP1_ReleaseReset\n

  615.   *         APB1RSTR     USBRST         LL_APB1_GRP1_ReleaseReset\n

  616.   *         APB1RSTR     CRSRST         LL_APB1_GRP1_ReleaseReset\n

  617.   *         APB1RSTR     PWRRST         LL_APB1_GRP1_ReleaseReset\n

  618.   *         APB1RSTR     DACRST         LL_APB1_GRP1_ReleaseReset\n

  619.   *         APB1RSTR     I2C3RST        LL_APB1_GRP1_ReleaseReset\n

  620.   *         APB1RSTR     LPTIM1RST      LL_APB1_GRP1_ReleaseReset

  621.   * @param  Periphs This parameter can be a combination of the following values:

  622.   *         @arg @ref LL_APB1_GRP1_PERIPH_ALL

  623.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  624.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  625.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  626.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  627.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  628.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  629.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  630.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  631.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  632.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  633.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  634.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  635.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  636.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  637.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  638.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  639.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  640.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  641.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  642.   *

  643.   *         (*) value not defined in all devices.

  644.   * @retval None

  645. */

  646. __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)

  647. {

  648.   CLEAR_BIT(RCC->APB1RSTR, Periphs);

  649. }

  650. 

  651. /**

  652.   * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

  653.   * @rmtoll APB1SMENR    TIM2SMEN      LL_APB1_GRP1_EnableClockSleep\n

  654.   *         APB1SMENR    TIM3SMEN      LL_APB1_GRP1_EnableClockSleep\n

  655.   *         APB1SMENR    TIM6SMEN      LL_APB1_GRP1_EnableClockSleep\n

  656.   *         APB1SMENR    TIM7SMEN      LL_APB1_GRP1_EnableClockSleep\n

  657.   *         APB1SMENR    LCDSMEN       LL_APB1_GRP1_EnableClockSleep\n

  658.   *         APB1SMENR    WWDGSMEN      LL_APB1_GRP1_EnableClockSleep\n

  659.   *         APB1SMENR    SPI2SMEN      LL_APB1_GRP1_EnableClockSleep\n

  660.   *         APB1SMENR    USART2SMEN    LL_APB1_GRP1_EnableClockSleep\n

  661.   *         APB1SMENR    LPUART1SMEN   LL_APB1_GRP1_EnableClockSleep\n

  662.   *         APB1SMENR    USART4SMEN    LL_APB1_GRP1_EnableClockSleep\n

  663.   *         APB1SMENR    USART5SMEN    LL_APB1_GRP1_EnableClockSleep\n

  664.   *         APB1SMENR    I2C1SMEN      LL_APB1_GRP1_EnableClockSleep\n

  665.   *         APB1SMENR    I2C2SMEN      LL_APB1_GRP1_EnableClockSleep\n

  666.   *         APB1SMENR    USBSMEN       LL_APB1_GRP1_EnableClockSleep\n

  667.   *         APB1SMENR    CRSSMEN       LL_APB1_GRP1_EnableClockSleep\n

  668.   *         APB1SMENR    PWRSMEN       LL_APB1_GRP1_EnableClockSleep\n

  669.   *         APB1SMENR    DACSMEN       LL_APB1_GRP1_EnableClockSleep\n

  670.   *         APB1SMENR    I2C3SMEN      LL_APB1_GRP1_EnableClockSleep\n

  671.   *         APB1SMENR    LPTIM1SMEN    LL_APB1_GRP1_EnableClockSleep

  672.   * @param  Periphs This parameter can be a combination of the following values:

  673.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  674.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  675.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  676.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  677.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  678.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  679.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  680.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  681.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  682.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  683.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  684.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  685.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  686.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  687.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  688.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  689.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  690.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  691.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  692.   *

  693.   *         (*) value not defined in all devices.

  694.   * @retval None

  695. */

  696. __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

  697. {

  698.   __IO uint32_t tmpreg;

  699.   SET_BIT(RCC->APB1SMENR, Periphs);

  700.   /* Delay after an RCC peripheral clock enabling */

  701.   tmpreg = READ_BIT(RCC->APB1SMENR, Periphs);

  702.   (void)tmpreg;

  703. }

  704. 

  705. /**

  706.   * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

  707.   * @rmtoll APB1SMENR    TIM2SMEN      LL_APB1_GRP1_DisableClockSleep\n

  708.   *         APB1SMENR    TIM3SMEN      LL_APB1_GRP1_DisableClockSleep\n

  709.   *         APB1SMENR    TIM6SMEN      LL_APB1_GRP1_DisableClockSleep\n

  710.   *         APB1SMENR    TIM7SMEN      LL_APB1_GRP1_DisableClockSleep\n

  711.   *         APB1SMENR    LCDSMEN       LL_APB1_GRP1_DisableClockSleep\n

  712.   *         APB1SMENR    WWDGSMEN      LL_APB1_GRP1_DisableClockSleep\n

  713.   *         APB1SMENR    SPI2SMEN      LL_APB1_GRP1_DisableClockSleep\n

  714.   *         APB1SMENR    USART2SMEN    LL_APB1_GRP1_DisableClockSleep\n

  715.   *         APB1SMENR    LPUART1SMEN   LL_APB1_GRP1_DisableClockSleep\n

  716.   *         APB1SMENR    USART4SMEN    LL_APB1_GRP1_DisableClockSleep\n

  717.   *         APB1SMENR    USART5SMEN    LL_APB1_GRP1_DisableClockSleep\n

  718.   *         APB1SMENR    I2C1SMEN      LL_APB1_GRP1_DisableClockSleep\n

  719.   *         APB1SMENR    I2C2SMEN      LL_APB1_GRP1_DisableClockSleep\n

  720.   *         APB1SMENR    USBSMEN       LL_APB1_GRP1_DisableClockSleep\n

  721.   *         APB1SMENR    CRSSMEN       LL_APB1_GRP1_DisableClockSleep\n

  722.   *         APB1SMENR    PWRSMEN       LL_APB1_GRP1_DisableClockSleep\n

  723.   *         APB1SMENR    DACSMEN       LL_APB1_GRP1_DisableClockSleep\n

  724.   *         APB1SMENR    I2C3SMEN      LL_APB1_GRP1_DisableClockSleep\n

  725.   *         APB1SMENR    LPTIM1SMEN    LL_APB1_GRP1_DisableClockSleep

  726.   * @param  Periphs This parameter can be a combination of the following values:

  727.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

  728.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)

  729.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*)

  730.   *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*)

  731.   *         @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)

  732.   *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG

  733.   *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)

  734.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

  735.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPUART1

  736.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART4 (*)

  737.   *         @arg @ref LL_APB1_GRP1_PERIPH_USART5 (*)

  738.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

  739.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)

  740.   *         @arg @ref LL_APB1_GRP1_PERIPH_USB (*)

  741.   *         @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)

  742.   *         @arg @ref LL_APB1_GRP1_PERIPH_PWR

  743.   *         @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*)

  744.   *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3 (*)

  745.   *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

  746.   *

  747.   *         (*) value not defined in all devices.

  748.   * @retval None

  749. */

  750. __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

  751. {

  752.   CLEAR_BIT(RCC->APB1SMENR, Periphs);

  753. }

  754. 

  755. /**

  756.   * @}

  757.   */

  758. 

  759. /** @defgroup BUS_LL_EF_APB2 APB2

  760.   * @{

  761.   */

  762. 

  763. /**

  764.   * @brief  Enable APB2 peripherals clock.

  765.   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_EnableClock\n

  766.   *         APB2ENR      TIM21EN       LL_APB2_GRP1_EnableClock\n

  767.   *         APB2ENR      TIM22EN       LL_APB2_GRP1_EnableClock\n

  768.   *         APB2ENR      FWEN          LL_APB2_GRP1_EnableClock\n

  769.   *         APB2ENR      ADCEN         LL_APB2_GRP1_EnableClock\n

  770.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n

  771.   *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n

  772.   *         APB2ENR      DBGEN         LL_APB2_GRP1_EnableClock

  773.   * @param  Periphs This parameter can be a combination of the following values:

  774.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  775.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  776.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  777.   *         @arg @ref LL_APB2_GRP1_PERIPH_FW

  778.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  779.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  780.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)

  781.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  782.   *

  783.   *         (*) value not defined in all devices.

  784.   * @retval None

  785. */

  786. __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)

  787. {

  788.   __IO uint32_t tmpreg;

  789.   SET_BIT(RCC->APB2ENR, Periphs);

  790.   /* Delay after an RCC peripheral clock enabling */

  791.   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);

  792.   (void)tmpreg;

  793. }

  794. 

  795. /**

  796.   * @brief  Check if APB2 peripheral clock is enabled or not

  797.   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_IsEnabledClock\n

  798.   *         APB2ENR      TIM21EN       LL_APB2_GRP1_IsEnabledClock\n

  799.   *         APB2ENR      TIM22EN       LL_APB2_GRP1_IsEnabledClock\n

  800.   *         APB2ENR      FWEN          LL_APB2_GRP1_IsEnabledClock\n

  801.   *         APB2ENR      ADCEN         LL_APB2_GRP1_IsEnabledClock\n

  802.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n

  803.   *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n

  804.   *         APB2ENR      DBGEN         LL_APB2_GRP1_IsEnabledClock

  805.   * @param  Periphs This parameter can be a combination of the following values:

  806.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  807.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  808.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  809.   *         @arg @ref LL_APB2_GRP1_PERIPH_FW

  810.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  811.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  812.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)

  813.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  814.   *

  815.   *         (*) value not defined in all devices.

  816.   * @retval State of Periphs (1 or 0).

  817. */

  818. __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

  819. {

  820.   return ((READ_BIT(RCC->APB2ENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  821. }

  822. 

  823. /**

  824.   * @brief  Disable APB2 peripherals clock.

  825.   * @rmtoll APB2ENR      SYSCFGEN      LL_APB2_GRP1_DisableClock\n

  826.   *         APB2ENR      TIM21EN       LL_APB2_GRP1_DisableClock\n

  827.   *         APB2ENR      TIM22EN       LL_APB2_GRP1_DisableClock\n

  828.   *         APB2ENR      FWEN          LL_APB2_GRP1_DisableClock\n

  829.   *         APB2ENR      ADCEN         LL_APB2_GRP1_DisableClock\n

  830.   *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n

  831.   *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n

  832.   *         APB2ENR      DBGEN         LL_APB2_GRP1_DisableClock

  833.   * @param  Periphs This parameter can be a combination of the following values:

  834.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  835.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  836.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  837.   *         @arg @ref LL_APB2_GRP1_PERIPH_FW

  838.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  839.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  840.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)

  841.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  842.   *

  843.   *         (*) value not defined in all devices.

  844.   * @retval None

  845. */

  846. __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)

  847. {

  848.   CLEAR_BIT(RCC->APB2ENR, Periphs);

  849. }

  850. 

  851. /**

  852.   * @brief  Force APB2 peripherals reset.

  853.   * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ForceReset\n

  854.   *         APB2RSTR     TIM21RST      LL_APB2_GRP1_ForceReset\n

  855.   *         APB2RSTR     TIM22RST      LL_APB2_GRP1_ForceReset\n

  856.   *         APB2RSTR     ADCRST        LL_APB2_GRP1_ForceReset\n

  857.   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n

  858.   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n

  859.   *         APB2RSTR     DBGRST        LL_APB2_GRP1_ForceReset

  860.   * @param  Periphs This parameter can be a combination of the following values:

  861.   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL

  862.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  863.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  864.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  865.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  866.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  867.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1 (*)

  868.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  869.   *

  870.   *         (*) value not defined in all devices.

  871.   * @retval None

  872. */

  873. __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)

  874. {

  875.   SET_BIT(RCC->APB2RSTR, Periphs);

  876. }

  877. 

  878. /**

  879.   * @brief  Release APB2 peripherals reset.

  880.   * @rmtoll APB2RSTR     SYSCFGRST     LL_APB2_GRP1_ReleaseReset\n

  881.   *         APB2RSTR     TIM21RST      LL_APB2_GRP1_ReleaseReset\n

  882.   *         APB2RSTR     TIM22RST      LL_APB2_GRP1_ReleaseReset\n

  883.   *         APB2RSTR     ADCRST        LL_APB2_GRP1_ReleaseReset\n

  884.   *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n

  885.   *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n

  886.   *         APB2RSTR     DBGRST        LL_APB2_GRP1_ReleaseReset

  887.   * @param  Periphs This parameter can be a combination of the following values:

  888.   *         @arg @ref LL_APB2_GRP1_PERIPH_ALL

  889.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  890.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  891.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  892.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  893.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  894.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)

  895.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  896.   *

  897.   *         (*) value not defined in all devices.

  898.   * @retval None

  899. */

  900. __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)

  901. {

  902.   CLEAR_BIT(RCC->APB2RSTR, Periphs);

  903. }

  904. 

  905. /**

  906.   * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.

  907.   * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_EnableClockSleep\n

  908.   *         APB2SMENR    TIM21SMEN     LL_APB2_GRP1_EnableClockSleep\n

  909.   *         APB2SMENR    TIM22SMEN     LL_APB2_GRP1_EnableClockSleep\n

  910.   *         APB2SMENR    ADCSMEN       LL_APB2_GRP1_EnableClockSleep\n

  911.   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_EnableClockSleep\n

  912.   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_EnableClockSleep\n

  913.   *         APB2SMENR    DBGSMEN       LL_APB2_GRP1_EnableClockSleep

  914.   * @param  Periphs This parameter can be a combination of the following values:

  915.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  916.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  917.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  918.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  919.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  920.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)

  921.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  922.   *

  923.   *         (*) value not defined in all devices.

  924.   * @retval None

  925. */

  926. __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

  927. {

  928.   __IO uint32_t tmpreg;

  929.   SET_BIT(RCC->APB2SMENR, Periphs);

  930.   /* Delay after an RCC peripheral clock enabling */

  931.   tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);

  932.   (void)tmpreg;

  933. }

  934. 

  935. /**

  936.   * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.

  937.   * @rmtoll APB2SMENR    SYSCFGSMEN    LL_APB2_GRP1_DisableClockSleep\n

  938.   *         APB2SMENR    TIM21SMEN     LL_APB2_GRP1_DisableClockSleep\n

  939.   *         APB2SMENR    TIM22SMEN     LL_APB2_GRP1_DisableClockSleep\n

  940.   *         APB2SMENR    ADCSMEN       LL_APB2_GRP1_DisableClockSleep\n

  941.   *         APB2SMENR    SPI1SMEN      LL_APB2_GRP1_DisableClockSleep\n

  942.   *         APB2SMENR    USART1SMEN    LL_APB2_GRP1_DisableClockSleep\n

  943.   *         APB2SMENR    DBGSMEN       LL_APB2_GRP1_DisableClockSleep

  944.   * @param  Periphs This parameter can be a combination of the following values:

  945.   *         @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG

  946.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM21

  947.   *         @arg @ref LL_APB2_GRP1_PERIPH_TIM22  (*)

  948.   *         @arg @ref LL_APB2_GRP1_PERIPH_ADC1

  949.   *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

  950.   *         @arg @ref LL_APB2_GRP1_PERIPH_USART1  (*)

  951.   *         @arg @ref LL_APB2_GRP1_PERIPH_DBGMCU

  952.   *

  953.   *         (*) value not defined in all devices.

  954.   * @retval None

  955. */

  956. __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

  957. {

  958.   CLEAR_BIT(RCC->APB2SMENR, Periphs);

  959. }

  960. 

  961. /**

  962.   * @}

  963.   */

  964. /** @defgroup BUS_LL_EF_IOP IOP

  965.   * @{

  966.   */

  967. 

  968. /**

  969.   * @brief  Enable IOP peripherals clock.

  970.   * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_EnableClock\n

  971.   *         IOPENR       GPIOBEN       LL_IOP_GRP1_EnableClock\n

  972.   *         IOPENR       GPIOCEN       LL_IOP_GRP1_EnableClock\n

  973.   *         IOPENR       GPIODEN       LL_IOP_GRP1_EnableClock\n

  974.   *         IOPENR       GPIOEEN       LL_IOP_GRP1_EnableClock\n

  975.   *         IOPENR       GPIOHEN       LL_IOP_GRP1_EnableClock

  976.   * @param  Periphs This parameter can be a combination of the following values:

  977.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  978.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  979.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  980.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  981.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  982.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  983.   *

  984.   *         (*) value not defined in all devices.

  985.   * @retval None

  986. */

  987. __STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)

  988. {

  989.   __IO uint32_t tmpreg;

  990.   SET_BIT(RCC->IOPENR, Periphs);

  991.   /* Delay after an RCC peripheral clock enabling */

  992.   tmpreg = READ_BIT(RCC->IOPENR, Periphs);

  993.   (void)tmpreg;

  994. }

  995. 

  996. /**

  997.   * @brief  Check if IOP peripheral clock is enabled or not

  998.   * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_IsEnabledClock\n

  999.   *         IOPENR       GPIOBEN       LL_IOP_GRP1_IsEnabledClock\n

  1000.   *         IOPENR       GPIOCEN       LL_IOP_GRP1_IsEnabledClock\n

  1001.   *         IOPENR       GPIODEN       LL_IOP_GRP1_IsEnabledClock\n

  1002.   *         IOPENR       GPIOEEN       LL_IOP_GRP1_IsEnabledClock\n

  1003.   *         IOPENR       GPIOHEN       LL_IOP_GRP1_IsEnabledClock

  1004.   * @param  Periphs This parameter can be a combination of the following values:

  1005.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  1006.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  1007.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  1008.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  1009.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  1010.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  1011.   *

  1012.   *         (*) value not defined in all devices.

  1013.   * @retval State of Periphs (1 or 0).

  1014. */

  1015. __STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)

  1016. {

  1017.   return ((READ_BIT(RCC->IOPENR, Periphs) == (Periphs)) ? 1UL : 0UL);

  1018. }

  1019. 

  1020. /**

  1021.   * @brief  Disable IOP peripherals clock.

  1022.   * @rmtoll IOPENR       GPIOAEN       LL_IOP_GRP1_DisableClock\n

  1023.   *         IOPENR       GPIOBEN       LL_IOP_GRP1_DisableClock\n

  1024.   *         IOPENR       GPIOCEN       LL_IOP_GRP1_DisableClock\n

  1025.   *         IOPENR       GPIODEN       LL_IOP_GRP1_DisableClock\n

  1026.   *         IOPENR       GPIOEEN       LL_IOP_GRP1_DisableClock\n

  1027.   *         IOPENR       GPIOHEN       LL_IOP_GRP1_DisableClock

  1028.   * @param  Periphs This parameter can be a combination of the following values:

  1029.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  1030.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  1031.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  1032.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  1033.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  1034.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  1035.   *

  1036.   *         (*) value not defined in all devices.

  1037.   * @retval None

  1038. */

  1039. __STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)

  1040. {

  1041.   CLEAR_BIT(RCC->IOPENR, Periphs);

  1042. }

  1043. 

  1044. /**

  1045.   * @brief  Disable IOP peripherals clock.

  1046.   * @rmtoll IOPRSTR      GPIOASMEN     LL_IOP_GRP1_ForceReset\n

  1047.   *         IOPRSTR      GPIOBSMEN     LL_IOP_GRP1_ForceReset\n

  1048.   *         IOPRSTR      GPIOCSMEN     LL_IOP_GRP1_ForceReset\n

  1049.   *         IOPRSTR      GPIODSMEN     LL_IOP_GRP1_ForceReset\n

  1050.   *         IOPRSTR      GPIOESMEN     LL_IOP_GRP1_ForceReset\n

  1051.   *         IOPRSTR      GPIOHSMEN     LL_IOP_GRP1_ForceReset

  1052.   * @param  Periphs This parameter can be a combination of the following values:

  1053.   *         @arg @ref LL_IOP_GRP1_PERIPH_ALL

  1054.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  1055.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  1056.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  1057.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  1058.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  1059.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  1060.   *

  1061.   *         (*) value not defined in all devices.

  1062.   * @retval None

  1063. */

  1064. __STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)

  1065. {

  1066.   SET_BIT(RCC->IOPRSTR, Periphs);

  1067. }

  1068. 

  1069. /**

  1070.   * @brief  Release IOP peripherals reset.

  1071.   * @rmtoll IOPRSTR      GPIOASMEN     LL_IOP_GRP1_ReleaseReset\n

  1072.   *         IOPRSTR      GPIOBSMEN     LL_IOP_GRP1_ReleaseReset\n

  1073.   *         IOPRSTR      GPIOCSMEN     LL_IOP_GRP1_ReleaseReset\n

  1074.   *         IOPRSTR      GPIODSMEN     LL_IOP_GRP1_ReleaseReset\n

  1075.   *         IOPRSTR      GPIOESMEN     LL_IOP_GRP1_ReleaseReset\n

  1076.   *         IOPRSTR      GPIOHSMEN     LL_IOP_GRP1_ReleaseReset

  1077.   * @param  Periphs This parameter can be a combination of the following values:

  1078.   *         @arg @ref LL_IOP_GRP1_PERIPH_ALL

  1079.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  1080.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  1081.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  1082.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  1083.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  1084.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  1085.   *

  1086.   *         (*) value not defined in all devices.

  1087.   * @retval None

  1088. */

  1089. __STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)

  1090. {

  1091.   CLEAR_BIT(RCC->IOPRSTR, Periphs);

  1092. }

  1093. 

  1094. /**

  1095.   * @brief  Enable IOP peripherals clock during Low Power (Sleep) mode.

  1096.   * @rmtoll IOPSMENR     GPIOARST      LL_IOP_GRP1_EnableClockSleep\n

  1097.   *         IOPSMENR     GPIOBRST      LL_IOP_GRP1_EnableClockSleep\n

  1098.   *         IOPSMENR     GPIOCRST      LL_IOP_GRP1_EnableClockSleep\n

  1099.   *         IOPSMENR     GPIODRST      LL_IOP_GRP1_EnableClockSleep\n

  1100.   *         IOPSMENR     GPIOERST      LL_IOP_GRP1_EnableClockSleep\n

  1101.   *         IOPSMENR     GPIOHRST      LL_IOP_GRP1_EnableClockSleep

  1102.   * @param  Periphs This parameter can be a combination of the following values:

  1103.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  1104.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  1105.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  1106.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  1107.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  1108.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  1109.   *

  1110.   *         (*) value not defined in all devices.

  1111.   * @retval None

  1112. */

  1113. __STATIC_INLINE void LL_IOP_GRP1_EnableClockSleep(uint32_t Periphs)

  1114. {

  1115.   __IO uint32_t tmpreg;

  1116.   SET_BIT(RCC->IOPSMENR, Periphs);

  1117.   /* Delay after an RCC peripheral clock enabling */

  1118.   tmpreg = READ_BIT(RCC->IOPSMENR, Periphs);

  1119.   (void)tmpreg;

  1120. }

  1121. 

  1122. /**

  1123.   * @brief  Disable IOP peripherals clock during Low Power (Sleep) mode.

  1124.   * @rmtoll IOPSMENR     GPIOARST      LL_IOP_GRP1_DisableClockSleep\n

  1125.   *         IOPSMENR     GPIOBRST      LL_IOP_GRP1_DisableClockSleep\n

  1126.   *         IOPSMENR     GPIOCRST      LL_IOP_GRP1_DisableClockSleep\n

  1127.   *         IOPSMENR     GPIODRST      LL_IOP_GRP1_DisableClockSleep\n

  1128.   *         IOPSMENR     GPIOERST      LL_IOP_GRP1_DisableClockSleep\n

  1129.   *         IOPSMENR     GPIOHRST      LL_IOP_GRP1_DisableClockSleep

  1130.   * @param  Periphs This parameter can be a combination of the following values:

  1131.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOA

  1132.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOB

  1133.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOC

  1134.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOD (*)

  1135.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOE (*)

  1136.   *         @arg @ref LL_IOP_GRP1_PERIPH_GPIOH (*)

  1137.   *

  1138.   *         (*) value not defined in all devices.

  1139.   * @retval None

  1140. */

  1141. __STATIC_INLINE void LL_IOP_GRP1_DisableClockSleep(uint32_t Periphs)

  1142. {

  1143.   CLEAR_BIT(RCC->IOPSMENR, Periphs);

  1144. }

  1145. 

  1146. /**

  1147.   * @}

  1148.   */

  1149. 

  1150. 

  1151. /**

  1152.   * @}

  1153.   */

  1154. 

  1155. /**

  1156.   * @}

  1157.   */

  1158. 

  1159. #endif /* defined(RCC) */

  1160. 

  1161. /**

  1162.   * @}

  1163.   */

  1164. 

  1165. #ifdef __cplusplus

  1166. }

  1167. #endif

  1168. 

  1169. #endif /* __STM32L0xx_LL_BUS_H */

  1170. 

  1171. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/