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stm32lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32l4xx_hal_dma.h

  4.   * @author  MCD Application Team

  5.   * @version V1.3.0

  6.   * @date    29-January-2016

  7.   * @brief   Header file of DMA HAL module.

  8.   ******************************************************************************

  9.   * @attention

  10.   *

  11.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  12.   *

  13.   * Redistribution and use in source and binary forms, with or without modification,

  14.   * are permitted provided that the following conditions are met:

  15.   *   1. Redistributions of source code must retain the above copyright notice,

  16.   *      this list of conditions and the following disclaimer.

  17.   *   2. Redistributions in binary form must reproduce the above copyright notice,

  18.   *      this list of conditions and the following disclaimer in the documentation

  19.   *      and/or other materials provided with the distribution.

  20.   *   3. Neither the name of STMicroelectronics nor the names of its contributors

  21.   *      may be used to endorse or promote products derived from this software

  22.   *      without specific prior written permission.

  23.   *

  24.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  25.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  26.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  27.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  28.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  29.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  30.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  31.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  32.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  33.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  34.   *

  35.   ******************************************************************************

  36.   */

  37. 

  38. /* Define to prevent recursive inclusion -------------------------------------*/

  39. #ifndef __STM32L4xx_HAL_DMA_H

  40. #define __STM32L4xx_HAL_DMA_H

  41. 

  42. #ifdef __cplusplus

  43.  extern "C" {

  44. #endif

  45. 

  46. /* Includes ------------------------------------------------------------------*/

  47. #include "stm32l4xx_hal_def.h"

  48. 

  49. /** @addtogroup STM32L4xx_HAL_Driver

  50.   * @{

  51.   */

  52. 

  53. /** @addtogroup DMA

  54.   * @{

  55.   */

  56. 

  57. /* Exported types ------------------------------------------------------------*/

  58. /** @defgroup DMA_Exported_Types DMA Exported Types

  59.   * @{

  60.   */

  61. 

  62. /**

  63.   * @brief  DMA Configuration Structure definition

  64.   */

  65. typedef struct

  66. {

  67.   uint32_t Request;                   /*!< Specifies the request selected for the specified channel.

  68.                                            This parameter can be a value of @ref DMA_request */

  69. 

  70.   uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,

  71.                                            from memory to memory or from peripheral to memory.

  72.                                            This parameter can be a value of @ref DMA_Data_transfer_direction */

  73. 

  74.   uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.

  75.                                            This parameter can be a value of @ref DMA_Peripheral_incremented_mode */

  76. 

  77.   uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.

  78.                                            This parameter can be a value of @ref DMA_Memory_incremented_mode */

  79. 

  80.   uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.

  81.                                            This parameter can be a value of @ref DMA_Peripheral_data_size */

  82. 

  83.   uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.

  84.                                            This parameter can be a value of @ref DMA_Memory_data_size */

  85. 

  86.   uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.

  87.                                            This parameter can be a value of @ref DMA_mode

  88.                                            @note The circular buffer mode cannot be used if the memory-to-memory

  89.                                                  data transfer is configured on the selected Channel */

  90. 

  91.   uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.

  92.                                            This parameter can be a value of @ref DMA_Priority_level */

  93. } DMA_InitTypeDef;

  94. 

  95. /**

  96.   * @brief DMA Configuration enumeration values definition

  97.   */

  98. typedef enum

  99. {

  100.   DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */

  101.   DMA_PRIORITY        = 1       /*!< Control related priority level Parameter in DMA_InitTypeDef  */

  102. 

  103. } DMA_ControlTypeDef;

  104. 

  105. /**

  106.   * @brief  HAL DMA State structures definition

  107.   */

  108. typedef enum

  109. {

  110.   HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */

  111.   HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use  */

  112.   HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success               */

  113.   HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */

  114.   HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                      */

  115.   HAL_DMA_STATE_ERROR             = 0x04   /*!< DMA error state                        */

  116. }HAL_DMA_StateTypeDef;

  117. 

  118. /**

  119.   * @brief  HAL DMA Error Code structure definition

  120.   */

  121. typedef enum

  122. {

  123.   HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */

  124.   HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */

  125. }HAL_DMA_LevelCompleteTypeDef;

  126. 

  127. /**

  128.   * @brief  DMA handle Structure definition

  129.   */

  130. typedef struct __DMA_HandleTypeDef

  131. {

  132.   DMA_Channel_TypeDef    *Instance;                                                /*!< Register base address                  */

  133.                                                                                 

  134.   DMA_InitTypeDef       Init;                                                      /*!< DMA communication parameters           */

  135.                                                                                 

  136.   HAL_LockTypeDef       Lock;                                                      /*!< DMA locking object                     */

  137.                                                                                 

  138.   __IO HAL_DMA_StateTypeDef  State;                                                /*!< DMA transfer state                     */

  139.                                                                                 

  140.   void                  *Parent;                                                   /*!< Parent object state                    */

  141. 

  142.   void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */

  143. 

  144.   void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */

  145. 

  146.   void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */

  147. 

  148.   __IO uint32_t          ErrorCode;                                                /*!< DMA Error code                         */

  149. }DMA_HandleTypeDef;

  150. 

  151. /**

  152.   * @}

  153.   */

  154. 

  155. /* Exported constants --------------------------------------------------------*/

  156. 

  157. /** @defgroup DMA_Exported_Constants DMA Exported Constants

  158.   * @{

  159.   */

  160. 

  161. /** @defgroup DMA_Error_Code DMA Error Code

  162.   * @{

  163.   */

  164. #define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */

  165. #define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */

  166. #define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */

  167. /**

  168.   * @}

  169.   */

  170. 

  171. /** @defgroup DMA_request DMA request

  172.   * @{

  173.   */

  174. #define DMA_REQUEST_0                     ((uint32_t)0x00000000)

  175. #define DMA_REQUEST_1                     ((uint32_t)0x00000001)

  176. #define DMA_REQUEST_2                     ((uint32_t)0x00000002)

  177. #define DMA_REQUEST_3                     ((uint32_t)0x00000003)

  178. #define DMA_REQUEST_4                     ((uint32_t)0x00000004)

  179. #define DMA_REQUEST_5                     ((uint32_t)0x00000005)

  180. #define DMA_REQUEST_6                     ((uint32_t)0x00000006)

  181. #define DMA_REQUEST_7                     ((uint32_t)0x00000007)

  182. /**

  183.   * @}

  184.   */

  185. 

  186. /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction

  187.   * @{

  188.   */

  189. #define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */

  190. #define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */

  191. #define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */

  192. /**

  193.   * @}

  194.   */

  195. 

  196. /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode

  197.   * @{

  198.   */

  199. #define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */

  200. #define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */

  201. /**

  202.   * @}

  203.   */

  204. 

  205. /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode

  206.   * @{

  207.   */

  208. #define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */

  209. #define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */

  210. /**

  211.   * @}

  212.   */

  213. 

  214. /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size

  215.   * @{

  216.   */

  217. #define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */

  218. #define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */

  219. #define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */

  220. /**

  221.   * @}

  222.   */

  223. 

  224. /** @defgroup DMA_Memory_data_size DMA Memory data size

  225.   * @{

  226.   */

  227. #define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */

  228. #define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */

  229. #define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */

  230. /**

  231.   * @}

  232.   */

  233. 

  234. /** @defgroup DMA_mode DMA mode

  235.   * @{

  236.   */

  237. #define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */

  238. #define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */

  239. /**

  240.   * @}

  241.   */

  242. 

  243. /** @defgroup DMA_Priority_level DMA Priority level

  244.   * @{

  245.   */

  246. #define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */

  247. #define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */

  248. #define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */

  249. #define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */

  250. /**

  251.   * @}

  252.   */

  253. 

  254. 

  255. /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions

  256.   * @{

  257.   */

  258. #define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)

  259. #define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)

  260. #define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)

  261. /**

  262.   * @}

  263.   */

  264. 

  265. /** @defgroup DMA_flag_definitions DMA flag definitions

  266.   * @{

  267.   */

  268. #define DMA_FLAG_GL1                      ((uint32_t)0x00000001)

  269. #define DMA_FLAG_TC1                      ((uint32_t)0x00000002)

  270. #define DMA_FLAG_HT1                      ((uint32_t)0x00000004)

  271. #define DMA_FLAG_TE1                      ((uint32_t)0x00000008)

  272. #define DMA_FLAG_GL2                      ((uint32_t)0x00000010)

  273. #define DMA_FLAG_TC2                      ((uint32_t)0x00000020)

  274. #define DMA_FLAG_HT2                      ((uint32_t)0x00000040)

  275. #define DMA_FLAG_TE2                      ((uint32_t)0x00000080)

  276. #define DMA_FLAG_GL3                      ((uint32_t)0x00000100)

  277. #define DMA_FLAG_TC3                      ((uint32_t)0x00000200)

  278. #define DMA_FLAG_HT3                      ((uint32_t)0x00000400)

  279. #define DMA_FLAG_TE3                      ((uint32_t)0x00000800)

  280. #define DMA_FLAG_GL4                      ((uint32_t)0x00001000)

  281. #define DMA_FLAG_TC4                      ((uint32_t)0x00002000)

  282. #define DMA_FLAG_HT4                      ((uint32_t)0x00004000)

  283. #define DMA_FLAG_TE4                      ((uint32_t)0x00008000)

  284. #define DMA_FLAG_GL5                      ((uint32_t)0x00010000)

  285. #define DMA_FLAG_TC5                      ((uint32_t)0x00020000)

  286. #define DMA_FLAG_HT5                      ((uint32_t)0x00040000)

  287. #define DMA_FLAG_TE5                      ((uint32_t)0x00080000)

  288. #define DMA_FLAG_GL6                      ((uint32_t)0x00100000)

  289. #define DMA_FLAG_TC6                      ((uint32_t)0x00200000)

  290. #define DMA_FLAG_HT6                      ((uint32_t)0x00400000)

  291. #define DMA_FLAG_TE6                      ((uint32_t)0x00800000)

  292. #define DMA_FLAG_GL7                      ((uint32_t)0x01000000)

  293. #define DMA_FLAG_TC7                      ((uint32_t)0x02000000)

  294. #define DMA_FLAG_HT7                      ((uint32_t)0x04000000)

  295. #define DMA_FLAG_TE7                      ((uint32_t)0x08000000)

  296. /**

  297.   * @}

  298.   */

  299. 

  300. /**

  301.   * @}

  302.   */

  303. 

  304. /* Exported macros -----------------------------------------------------------*/

  305. /** @defgroup DMA_Exported_Macros DMA Exported Macros

  306.   * @{

  307.   */

  308. 

  309. /** @brief  Reset DMA handle state.

  310.   * @param  __HANDLE__: DMA handle

  311.   * @retval None

  312.   */

  313. #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

  314. 

  315. /**

  316.   * @brief  Enable the specified DMA Channel.

  317.   * @param  __HANDLE__: DMA handle

  318.   * @retval None

  319.   */

  320. #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)

  321. 

  322. /**

  323.   * @brief  Disable the specified DMA Channel.

  324.   * @param  __HANDLE__: DMA handle

  325.   * @retval None

  326.   */

  327. #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)

  328. 

  329. 

  330. /* Interrupt & Flag management */

  331. 

  332. /**

  333.   * @brief  Return the current DMA Channel transfer complete flag.

  334.   * @param  __HANDLE__: DMA handle

  335.   * @retval The specified transfer complete flag index.

  336.   */

  337. 

  338. #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \

  339. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\

  340.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\

  341.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\

  342.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\

  343.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\

  344.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\

  345.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\

  346.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\

  347.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\

  348.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\

  349.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\

  350.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\

  351.    DMA_FLAG_TC7)

  352. 

  353. /**

  354.   * @brief  Return the current DMA Channel half transfer complete flag.

  355.   * @param  __HANDLE__: DMA handle

  356.   * @retval The specified half transfer complete flag index.

  357.   */

  358. #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\

  359. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\

  360.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\

  361.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\

  362.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\

  363.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\

  364.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\

  365.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\

  366.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\

  367.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\

  368.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\

  369.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\

  370.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\

  371.    DMA_FLAG_HT7)

  372. 

  373. /**

  374.   * @brief  Return the current DMA Channel transfer error flag.

  375.   * @param  __HANDLE__: DMA handle

  376.   * @retval The specified transfer error flag index.

  377.   */

  378. #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\

  379. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\

  380.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\

  381.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\

  382.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\

  383.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\

  384.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\

  385.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\

  386.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\

  387.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\

  388.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\

  389.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\

  390.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\

  391.    DMA_FLAG_TE7)

  392. 

  393. /**

  394.   * @brief  Return the current DMA Channel Global interrupt flag.

  395.   * @param  __HANDLE__: DMA handle

  396.   * @retval The specified transfer error flag index.

  397.   */

  398. #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\

  399. (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\

  400.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\

  401.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\

  402.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\

  403.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\

  404.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\

  405.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\

  406.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\

  407.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\

  408.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\

  409.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\

  410.  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\

  411.    DMA_ISR_GIF7)

  412. 

  413. /**

  414.   * @brief  Get the DMA Channel pending flags.

  415.   * @param  __HANDLE__: DMA handle

  416.   * @param  __FLAG__: Get the specified flag.

  417.   *          This parameter can be any combination of the following values:

  418.   *            @arg DMA_FLAG_TCIFx:  Transfer complete flag

  419.   *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag

  420.   *            @arg DMA_FLAG_TEIFx:  Transfer error flag

  421.   *            @arg DMA_ISR_GIFx: Global interrupt flag

  422.   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.

  423.   * @retval The state of FLAG (SET or RESET).

  424.   */

  425. #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \

  426.  (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))

  427. 

  428. /**

  429.   * @brief  Clear the DMA Channel pending flags.

  430.   * @param  __HANDLE__: DMA handle

  431.   * @param  __FLAG__: specifies the flag to clear.

  432.   *          This parameter can be any combination of the following values:

  433.   *            @arg DMA_FLAG_TCIFx:  Transfer complete flag

  434.   *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag

  435.   *            @arg DMA_FLAG_TEIFx:  Transfer error flag

  436.   *            @arg DMA_ISR_GIFx: Global interrupt flag

  437.   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.

  438.   * @retval None

  439.   */

  440. #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \

  441.  (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))

  442. 

  443. /**

  444.   * @brief  Enable the specified DMA Channel interrupts.

  445.   * @param  __HANDLE__: DMA handle

  446.   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.

  447.   *          This parameter can be any combination of the following values:

  448.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask

  449.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask

  450.   *            @arg DMA_IT_TE:  Transfer error interrupt mask

  451.   * @retval None

  452.   */

  453. #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

  454. 

  455. /**

  456.   * @brief  Disable the specified DMA Channel interrupts.

  457.   * @param  __HANDLE__: DMA handle

  458.   * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.

  459.   *          This parameter can be any combination of the following values:

  460.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask

  461.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask

  462.   *            @arg DMA_IT_TE:  Transfer error interrupt mask

  463.   * @retval None

  464.   */

  465. #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

  466. 

  467. /**

  468.   * @brief  Check whether the specified DMA Channel interrupt is enabled or not.

  469.   * @param  __HANDLE__: DMA handle

  470.   * @param  __INTERRUPT__: specifies the DMA interrupt source to check.

  471.   *          This parameter can be one of the following values:

  472.   *            @arg DMA_IT_TC:  Transfer complete interrupt mask

  473.   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask

  474.   *            @arg DMA_IT_TE:  Transfer error interrupt mask

  475.   * @retval The state of DMA_IT (SET or RESET).

  476.   */

  477. #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

  478. 

  479. /**

  480.   * @}

  481.   */

  482. 

  483. /* Exported functions --------------------------------------------------------*/

  484. 

  485. /** @addtogroup DMA_Exported_Functions

  486.   * @{

  487.   */

  488. 

  489. /** @addtogroup DMA_Exported_Functions_Group1

  490.   * @{

  491.   */

  492. /* Initialization and de-initialization functions *****************************/

  493. HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);

  494. HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);

  495. /**

  496.   * @}

  497.   */

  498. 

  499. /** @addtogroup DMA_Exported_Functions_Group2

  500.   * @{

  501.   */

  502. /* IO operation functions *****************************************************/

  503. HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);

  504. HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);

  505. HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);

  506. HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);

  507. void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);

  508. /**

  509.   * @}

  510.   */

  511. 

  512. /** @addtogroup DMA_Exported_Functions_Group3

  513.   * @{

  514.   */

  515. /* Peripheral State and Error functions ***************************************/

  516. HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);

  517. uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);

  518. /**

  519.   * @}

  520.   */

  521. 

  522. /**

  523.   * @}

  524.   */

  525. 

  526. /* Private macros ------------------------------------------------------------*/

  527. /** @defgroup DMA_Private_Macros DMA Private Macros

  528.   * @{

  529.   */

  530. 

  531. #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \

  532.                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \

  533.                                      ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

  534. 

  535. #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))

  536. 

  537. #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \

  538.                                             ((STATE) == DMA_PINC_DISABLE))

  539. 

  540. #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \

  541.                                         ((STATE) == DMA_MINC_DISABLE))

  542. 

  543. #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \

  544.                                      ((REQUEST) == DMA_REQUEST_1) || \

  545.                                      ((REQUEST) == DMA_REQUEST_2) || \

  546.                                      ((REQUEST) == DMA_REQUEST_3) || \

  547.                                      ((REQUEST) == DMA_REQUEST_4) || \

  548.                                      ((REQUEST) == DMA_REQUEST_5) || \

  549.                                      ((REQUEST) == DMA_REQUEST_6) || \

  550.                                      ((REQUEST) == DMA_REQUEST_7))

  551. 

  552. #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \

  553.                                            ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \

  554.                                            ((SIZE) == DMA_PDATAALIGN_WORD))

  555. 

  556. #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \

  557.                                        ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \

  558.                                        ((SIZE) == DMA_MDATAALIGN_WORD ))

  559. 

  560. #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \

  561.                            ((MODE) == DMA_CIRCULAR))

  562. 

  563. #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \

  564.                                    ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \

  565.                                    ((PRIORITY) == DMA_PRIORITY_HIGH)   || \

  566.                                    ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

  567. 

  568. /**

  569.   * @}

  570.   */ 

  571. 

  572. /* Private functions ---------------------------------------------------------*/

  573. 

  574. /**

  575.   * @}

  576.   */

  577. 

  578. /**

  579.   * @}

  580.   */

  581. 

  582. #ifdef __cplusplus

  583. }

  584. #endif

  585. 

  586. #endif /* __STM32L4xx_HAL_DMA_H */

  587. 

  588. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/