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stm32lib/STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32l4xx_hal.h

  4.   * @author  MCD Application Team

  5.   * @version V1.3.0

  6.   * @date    29-January-2016

  7.   * @brief   This file contains all the functions prototypes for the HAL

  8.   *          module driver.

  9.   ******************************************************************************

  10.   * @attention

  11.   *

  12.   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>

  13.   *

  14.   * Redistribution and use in source and binary forms, with or without modification,

  15.   * are permitted provided that the following conditions are met:

  16.   *   1. Redistributions of source code must retain the above copyright notice,

  17.   *      this list of conditions and the following disclaimer.

  18.   *   2. Redistributions in binary form must reproduce the above copyright notice,

  19.   *      this list of conditions and the following disclaimer in the documentation

  20.   *      and/or other materials provided with the distribution.

  21.   *   3. Neither the name of STMicroelectronics nor the names of its contributors

  22.   *      may be used to endorse or promote products derived from this software

  23.   *      without specific prior written permission.

  24.   *

  25.   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

  26.   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

  27.   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE

  28.   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE

  29.   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL

  30.   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR

  31.   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER

  32.   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,

  33.   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE

  34.   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

  35.   *

  36.   ******************************************************************************

  37.   */

  38. 

  39. /* Define to prevent recursive inclusion -------------------------------------*/

  40. #ifndef __STM32L4xx_HAL_H

  41. #define __STM32L4xx_HAL_H

  42. 

  43. #ifdef __cplusplus

  44.  extern "C" {

  45. #endif

  46. 

  47. /* Includes ------------------------------------------------------------------*/

  48. #include "stm32l4xx_hal_conf.h"

  49. 

  50. /** @addtogroup STM32L4xx_HAL_Driver

  51.   * @{

  52.   */

  53. 

  54. /** @addtogroup HAL

  55.   * @{

  56.   */

  57. 

  58. /* Exported types ------------------------------------------------------------*/

  59. /* Exported constants --------------------------------------------------------*/

  60. /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants

  61.   * @{

  62.   */

  63. 

  64. /** @defgroup SYSCFG_BootMode Boot Mode

  65.   * @{

  66.   */

  67. #define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)

  68. #define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0

  69. #define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1

  70. #define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)

  71. #define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)

  72. 

  73. /**

  74.   * @}

  75.   */

  76. 

  77. /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts

  78.   * @{

  79.   */

  80. #define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */

  81. #define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */

  82. #define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */

  83. #define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */

  84. #define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */

  85. #define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */

  86. 

  87. /**

  88.   * @}

  89.   */

  90. 

  91. /** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection

  92.   * @{

  93.   */

  94. #define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */

  95. #define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */

  96. #define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */

  97. #define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */

  98. #define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */

  99. #define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */

  100. #define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */

  101. #define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */

  102. #define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */

  103. #define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */

  104. #define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */

  105. #define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */

  106. #define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */

  107. #define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */

  108. #define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */

  109. #define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */

  110. #define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */

  111. #define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */

  112. #define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */

  113. #define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */

  114. #define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */

  115. #define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */

  116. #define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */

  117. #define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */

  118. #define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */

  119. #define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */

  120. #define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */

  121. #define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */

  122. #define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */

  123. #define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */

  124. #define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */

  125. #define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */

  126. 

  127. /**

  128.   * @}

  129.   */

  130. 

  131. #if defined(VREFBUF)

  132. /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale

  133.   * @{

  134.   */

  135. #define SYSCFG_VREFBUF_VOLTAGE_SCALE0  ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */

  136. #define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */

  137. 

  138. /**

  139.   * @}

  140.   */

  141. 

  142. /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance

  143.   * @{

  144.   */

  145. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */

  146. #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */

  147. 

  148. /**

  149.   * @}

  150.   */

  151. #endif /* VREFBUF */

  152. 

  153. /** @defgroup SYSCFG_flags_definition Flags

  154.   * @{

  155.   */

  156. 

  157. #define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */

  158. #define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */

  159. 

  160. /**

  161.   * @}

  162.   */

  163. 

  164. /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO

  165.   * @{

  166.   */

  167. 

  168. /** @brief  Fast-mode Plus driving capability on a specific GPIO

  169.   */  

  170. #define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */

  171. #define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */

  172. #if defined(SYSCFG_CFGR1_I2C_PB8_FMP)

  173. #define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */

  174. #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */

  175. #if defined(SYSCFG_CFGR1_I2C_PB9_FMP)

  176. #define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */

  177. #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */

  178. 

  179. /**

  180.  * @}

  181.  */

  182. 

  183. /**

  184.   * @}

  185.   */

  186. 

  187. /* Exported macros -----------------------------------------------------------*/

  188. 

  189. /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros

  190.   * @{

  191.   */

  192. 

  193. /** @brief  Freeze/Unfreeze Peripherals in Debug mode

  194.   */

  195. #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)

  196. #define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)

  197. #define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)

  198. #endif

  199. 

  200. #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)

  201. #define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)

  202. #define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)

  203. #endif

  204. 

  205. #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)

  206. #define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)

  207. #define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)

  208. #endif

  209. 

  210. #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)

  211. #define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)

  212. #define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)

  213. #endif

  214. 

  215. #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)

  216. #define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

  217. #define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)

  218. #endif

  219. 

  220. #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)

  221. #define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)

  222. #define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)

  223. #endif

  224. 

  225. #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)

  226. #define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)

  227. #define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)

  228. #endif

  229. 

  230. #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)

  231. #define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)

  232. #define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)

  233. #endif

  234. 

  235. #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)

  236. #define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

  237. #define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)

  238. #endif

  239. 

  240. #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)

  241. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)

  242. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)

  243. #endif

  244. 

  245. #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)

  246. #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)

  247. #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)

  248. #endif

  249. 

  250. #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)

  251. #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)

  252. #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)

  253. #endif

  254. 

  255. #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)

  256. #define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)

  257. #define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)

  258. #endif

  259. 

  260. #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

  261. #define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

  262. #define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)

  263. #endif

  264. 

  265. #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)

  266. #define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)

  267. #define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)

  268. #endif

  269. 

  270. #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)

  271. #define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)

  272. #define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)

  273. #endif

  274. 

  275. #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)

  276. #define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)

  277. #define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)

  278. #endif

  279. 

  280. #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)

  281. #define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)

  282. #define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)

  283. #endif

  284. 

  285. #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)

  286. #define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)

  287. #define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)

  288. #endif

  289. 

  290. #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)

  291. #define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

  292. #define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)

  293. #endif

  294. 

  295. /**

  296.   * @}

  297.   */

  298. 

  299. /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros

  300.   * @{

  301.   */

  302. 

  303. /** @brief  Main Flash memory mapped at 0x00000000.

  304.   */

  305. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

  306. 

  307. /** @brief  System Flash memory mapped at 0x00000000.

  308.   */

  309. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)

  310. 

  311. /** @brief  Embedded SRAM mapped at 0x00000000.

  312.   */

  313. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))

  314. 

  315. /** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.

  316.   */

  317. #define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)

  318. 

  319. /** @brief  QUADSPI mapped at 0x00000000.

  320.   */

  321. #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))

  322. 

  323. /**

  324.   * @brief  Return the boot mode as configured by user.

  325.   * @retval The boot mode as configured by user. The returned value can be one

  326.   *         of the following values:

  327.   *           @arg @ref SYSCFG_BOOT_MAINFLASH

  328.   *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH

  329.   *           @arg @ref SYSCFG_BOOT_FMC

  330.   *           @arg @ref SYSCFG_BOOT_SRAM

  331.   *           @arg @ref SYSCFG_BOOT_QUADSPI

  332.   */

  333. #define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

  334. 

  335. /** @brief  SRAM2 page write protection enable macro

  336.   * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP

  337.   * @note   write protection can only be disabled by a system reset

  338.   */

  339. #define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\

  340.                                                          SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\

  341.                                                         }while(0)

  342. 

  343. /** @brief  SRAM2 page write protection unlock prior to erase

  344.   * @note   Writing a wrong key reactivates the write protection

  345.   */

  346. #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\

  347.                                                  SYSCFG->SKR = 0x53;\

  348.                                                 }while(0)

  349. 

  350. /** @brief  SRAM2 erase

  351.   * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase

  352.   */

  353. #define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)

  354. 

  355. /** @brief  Floating Point Unit interrupt enable/disable macros

  356.   * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts

  357.   */

  358. #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

  359.                                                                 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\

  360.                                                             }while(0)

  361. 

  362. #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\

  363.                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\

  364.                                                             }while(0)

  365. 

  366. /** @brief  SYSCFG Break ECC lock.

  367.   *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.

  368.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  369.   */

  370. #define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)

  371. 

  372. /** @brief  SYSCFG Break Cortex-M4 Lockup lock.

  373.   *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.

  374.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  375.   */

  376. #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)

  377. 

  378. /** @brief  SYSCFG Break PVD lock.

  379.   *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.

  380.   * @note   The selected configuration is locked and can be unlocked only by system reset.

  381.   */

  382. #define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)

  383. 

  384. /** @brief  SYSCFG Break SRAM2 parity lock.

  385.   *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.

  386.   * @note   The selected configuration is locked and can be unlocked by system reset.

  387.   */

  388. #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)

  389. 

  390. /** @brief  Check SYSCFG flag is set or not.

  391.   * @param  __FLAG__: specifies the flag to check.

  392.   *         This parameter can be one of the following values:

  393.   *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag

  394.   *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing

  395.   * @retval The new state of __FLAG__ (TRUE or FALSE).

  396.   */

  397. #define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)

  398. 

  399. /** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.

  400.   */

  401. #define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)

  402. 

  403. /** @brief  Fast-mode Plus driving capability enable/disable macros

  404.   * @param __FASTMODEPLUS__: This parameter can be a value of : 

  405.   *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6

  406.   *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 

  407.   *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8

  408.   *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9

  409.   */

  410. #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\

  411.                                                                 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\

  412.                                                                }while(0)

  413. 

  414. #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\

  415.                                                                 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\

  416.                                                                }while(0)

  417. 

  418. /**

  419.   * @}

  420.   */

  421. 

  422. /* Private macros ------------------------------------------------------------*/

  423. /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros

  424.   * @{

  425.   */

  426. 

  427. #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \

  428.                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \

  429.                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \

  430.                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \

  431.                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \

  432.                                                 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))

  433. 

  434. #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \

  435.                                             ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \

  436.                                             ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \

  437.                                             ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))

  438. 

  439. #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))

  440. 

  441. #if defined(VREFBUF)

  442. #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \

  443.                                                      ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))

  444. 

  445. #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \

  446.                                                       ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

  447. 

  448. #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

  449. #endif /* VREFBUF */

  450. 

  451. #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)

  452. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \

  453.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \

  454.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \

  455.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))

  456. #elif defined(SYSCFG_FASTMODEPLUS_PB8)

  457. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \

  458.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \

  459.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))

  460. #elif defined(SYSCFG_FASTMODEPLUS_PB9)

  461. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \

  462.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \

  463.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))

  464. #else

  465. #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \

  466.                                          (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))

  467. #endif

  468. /**

  469.   * @}

  470.   */

  471. 

  472. /* Exported functions --------------------------------------------------------*/

  473. 

  474. /** @addtogroup HAL_Exported_Functions

  475.   * @{

  476.   */

  477. 

  478. /** @addtogroup HAL_Exported_Functions_Group1

  479.   * @{

  480.   */

  481. 

  482. /* Initialization and de-initialization functions  ******************************/

  483. HAL_StatusTypeDef HAL_Init(void);

  484. HAL_StatusTypeDef HAL_DeInit(void);

  485. void HAL_MspInit(void);

  486. void HAL_MspDeInit(void);

  487. HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);

  488. 

  489. /**

  490.   * @}

  491.   */

  492. 

  493. /** @addtogroup HAL_Exported_Functions_Group2

  494.   * @{

  495.   */

  496. 

  497. /* Peripheral Control functions  ************************************************/

  498. void HAL_IncTick(void);

  499. void HAL_Delay(uint32_t Delay);

  500. uint32_t HAL_GetTick(void);

  501. void HAL_SuspendTick(void);

  502. void HAL_ResumeTick(void);

  503. uint32_t HAL_GetHalVersion(void);

  504. uint32_t HAL_GetREVID(void);

  505. uint32_t HAL_GetDEVID(void);

  506. 

  507. /**

  508.   * @}

  509.   */

  510. 

  511. /** @addtogroup HAL_Exported_Functions_Group3

  512.   * @{

  513.   */

  514. 

  515. /* DBGMCU Peripheral Control functions  *****************************************/

  516. void HAL_DBGMCU_EnableDBGSleepMode(void);

  517. void HAL_DBGMCU_DisableDBGSleepMode(void);

  518. void HAL_DBGMCU_EnableDBGStopMode(void);

  519. void HAL_DBGMCU_DisableDBGStopMode(void);

  520. void HAL_DBGMCU_EnableDBGStandbyMode(void);

  521. void HAL_DBGMCU_DisableDBGStandbyMode(void);

  522. 

  523. /**

  524.   * @}

  525.   */

  526. 

  527. /** @addtogroup HAL_Exported_Functions_Group4

  528.   * @{

  529.   */

  530. 

  531. /* SYSCFG Control functions  ****************************************************/

  532. void HAL_SYSCFG_SRAM2Erase(void);

  533. void HAL_SYSCFG_EnableMemorySwappingBank(void);

  534. void HAL_SYSCFG_DisableMemorySwappingBank(void);

  535. 

  536. #if defined(VREFBUF)

  537. void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);

  538. void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);

  539. void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);

  540. HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);

  541. void HAL_SYSCFG_DisableVREFBUF(void);

  542. #endif /* VREFBUF */

  543. 

  544. void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);

  545. void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);

  546. 

  547. /**

  548.   * @}

  549.   */

  550. 

  551. /**

  552.   * @}

  553.   */

  554. 

  555. /**

  556.   * @}

  557.   */

  558. 

  559. /**

  560.   * @}

  561.   */

  562. 

  563. #ifdef __cplusplus

  564. }

  565. #endif

  566. 

  567. #endif /* __STM32L4xx_HAL_H */

  568. 

  569. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/