From d23f17fccc27f54313c6960e80298a9b1d57b638 Mon Sep 17 00:00:00 2001 From: Damien George Date: Sun, 27 Aug 2017 21:56:20 +1000 Subject: [PATCH] F7_HAL/rcc: Adjust computation of SYSCLK to retain precision. --- STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c b/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c index ccdd52b..a7a65a0 100644 --- a/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c +++ b/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_rcc.c @@ -917,7 +917,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI) { /* HSE used as PLL clock source */ - pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + //pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))); + // dpgeorge: Adjust the way the arithmetic is done so it retains + // precision for the case that pllm doesn't evenly divide HSE_VALUE. + // Must be sure not to overflow, so divide by 4 first. HSE_VALUE + // should be a multiple of 4 (being a multiple of 100 is enough). + pllvco = ((HSE_VALUE / 4) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN))) / pllm * 4; } else {