Import STM32Cube_FW_L4_V1.3.0 on 29-Jan-2016

CMSIS/STM32L4xx/Include/stm32l4xx.h

@@ -0,0 +1,207 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.0.3
+  * @date    29-January-2016
+  * @brief   CMSIS STM32L4xx Device Peripheral Access Layer Header File.
+  *
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The STM32L4xx device used in the target application
+  *              - To use or not the peripheral's drivers in application code(i.e.
+  *                code will be based on direct access to peripheral's registers
+  *                rather than drivers API), this option is controlled by
+  *                "#define USE_HAL_DRIVER"
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx
+  * @{
+  */
+
+#ifndef __STM32L4xx_H
+#define __STM32L4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+
+/**
+  * @brief STM32 Family
+  */
+#if !defined (STM32L4)
+#define STM32L4
+#endif /* STM32L4 */
+
+/* Uncomment the line below according to the target STM32L4 device used in your
+   application
+  */
+
+#if !defined (STM32L471xx) && !defined (STM32L475xx) && !defined (STM32L476xx) && !defined (STM32L485xx) && !defined (STM32L486xx)
+  /* #define STM32L471xx */   /*!< STM32L471xx Devices */
+  /* #define STM32L475xx */   /*!< STM32L475xx Devices */
+  /* #define STM32L476xx */   /*!< STM32L476xx Devices */
+  /* #define STM32L485xx */   /*!< STM32L485xx Devices */
+  /* #define STM32L486xx */   /*!< STM32L486xx Devices */
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+#if !defined  (USE_HAL_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will
+   be based on direct access to peripherals registers
+   */
+  /*#define USE_HAL_DRIVER */
+#endif /* USE_HAL_DRIVER */
+
+/**
+  * @brief CMSIS Device version number V1.0.3
+  */
+#define __STM32L4_CMSIS_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4_CMSIS_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32L4_CMSIS_VERSION_SUB2   (0x03) /*!< [15:8]  sub2 version */
+#define __STM32L4_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4_CMSIS_VERSION        ((__STM32L4_CMSIS_VERSION_MAIN << 24)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB1 << 16)\
+                                       |(__STM32L4_CMSIS_VERSION_SUB2 << 8 )\
+                                       |(__STM32L4_CMSIS_VERSION_RC))
+
+/**
+  * @}
+  */
+
+/** @addtogroup Device_Included
+  * @{
+  */
+
+#if defined(STM32L471xx)
+  #include "stm32l471xx.h"
+#elif defined(STM32L475xx)
+  #include "stm32l475xx.h"
+#elif defined(STM32L476xx)
+  #include "stm32l476xx.h"
+#elif defined(STM32L485xx)
+  #include "stm32l485xx.h"
+#elif defined(STM32L486xx)
+  #include "stm32l486xx.h"
+#else
+ #error "Please select first the target STM32L4xx device used in your application (in stm32l4xx.h file)"
+#endif
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_types
+  * @{
+  */
+typedef enum
+{
+  RESET = 0,
+  SET = !RESET
+} FlagStatus, ITStatus;
+
+typedef enum
+{
+  DISABLE = 0,
+  ENABLE = !DISABLE
+} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum
+{
+  ERROR = 0,
+  SUCCESS = !ERROR
+} ErrorStatus;
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup Exported_macros
+  * @{
+  */
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
+
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
+
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))
+
+#define CLEAR_REG(REG)        ((REG) = (0x0))
+
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
+
+#define READ_REG(REG)         ((REG))
+
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
+
+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))
+
+
+/**
+  * @}
+  */
+
+#if defined (USE_HAL_DRIVER)
+ #include "stm32l4xx_hal.h"
+#endif /* USE_HAL_DRIVER */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __STM32L4xx_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32L4xx/Include/system_stm32l4xx.h

@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32l4xx.h
+  * @author  MCD Application Team
+  * @version V1.0.3
+  * @date    29-January-2016
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32L4xx devices.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32l4xx_system
+  * @{
+  */
+
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32L4XX_H
+#define __SYSTEM_STM32L4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32L4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32L4xx_System_Exported_Variables
+  * @{
+  */
+  /* The SystemCoreClock variable is updated in three ways:
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+extern uint32_t SystemCoreClock;            /*!< System Clock Frequency (Core Clock) */
+
+extern const uint8_t  AHBPrescTable[16];    /*!< AHB prescalers table values */
+extern const uint8_t  APBPrescTable[8];     /*!< APB prescalers table values */
+extern const uint32_t MSIRangeTable[12];    /*!< MSI ranges table values     */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32L4xx_System_Exported_Functions
+  * @{
+  */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32L4XX_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal.h

@@ -0,0 +1,569 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   This file contains all the functions prototypes for the HAL
+  *          module driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_H
+#define __STM32L4xx_HAL_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_conf.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HAL
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
+  * @{
+  */
+
+/** @defgroup SYSCFG_BootMode Boot Mode
+  * @{
+  */
+#define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
+#define SYSCFG_BOOT_SYSTEMFLASH        SYSCFG_MEMRMP_MEM_MODE_0
+#define SYSCFG_BOOT_FMC                SYSCFG_MEMRMP_MEM_MODE_1
+#define SYSCFG_BOOT_SRAM               (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
+#define SYSCFG_BOOT_QUADSPI            (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts
+  * @{
+  */
+#define SYSCFG_IT_FPU_IOC              SYSCFG_CFGR1_FPU_IE_0  /*!< Floating Point Unit Invalid operation Interrupt */
+#define SYSCFG_IT_FPU_DZC              SYSCFG_CFGR1_FPU_IE_1  /*!< Floating Point Unit Divide-by-zero Interrupt */
+#define SYSCFG_IT_FPU_UFC              SYSCFG_CFGR1_FPU_IE_2  /*!< Floating Point Unit Underflow Interrupt */
+#define SYSCFG_IT_FPU_OFC              SYSCFG_CFGR1_FPU_IE_3  /*!< Floating Point Unit Overflow Interrupt */
+#define SYSCFG_IT_FPU_IDC              SYSCFG_CFGR1_FPU_IE_4  /*!< Floating Point Unit Input denormal Interrupt */
+#define SYSCFG_IT_FPU_IXC              SYSCFG_CFGR1_FPU_IE_5  /*!< Floating Point Unit Inexact Interrupt */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_SRAM2WRP SRAM2 Write protection
+  * @{
+  */
+#define SYSCFG_SRAM2WRP_PAGE0          SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */
+#define SYSCFG_SRAM2WRP_PAGE1          SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */
+#define SYSCFG_SRAM2WRP_PAGE2          SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */
+#define SYSCFG_SRAM2WRP_PAGE3          SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */
+#define SYSCFG_SRAM2WRP_PAGE4          SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */
+#define SYSCFG_SRAM2WRP_PAGE5          SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */
+#define SYSCFG_SRAM2WRP_PAGE6          SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */
+#define SYSCFG_SRAM2WRP_PAGE7          SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */
+#define SYSCFG_SRAM2WRP_PAGE8          SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */
+#define SYSCFG_SRAM2WRP_PAGE9          SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */
+#define SYSCFG_SRAM2WRP_PAGE10         SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */
+#define SYSCFG_SRAM2WRP_PAGE11         SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */
+#define SYSCFG_SRAM2WRP_PAGE12         SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */
+#define SYSCFG_SRAM2WRP_PAGE13         SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */
+#define SYSCFG_SRAM2WRP_PAGE14         SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */
+#define SYSCFG_SRAM2WRP_PAGE15         SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */
+#define SYSCFG_SRAM2WRP_PAGE16         SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */
+#define SYSCFG_SRAM2WRP_PAGE17         SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */
+#define SYSCFG_SRAM2WRP_PAGE18         SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */
+#define SYSCFG_SRAM2WRP_PAGE19         SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */
+#define SYSCFG_SRAM2WRP_PAGE20         SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */
+#define SYSCFG_SRAM2WRP_PAGE21         SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */
+#define SYSCFG_SRAM2WRP_PAGE22         SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */
+#define SYSCFG_SRAM2WRP_PAGE23         SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */
+#define SYSCFG_SRAM2WRP_PAGE24         SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */
+#define SYSCFG_SRAM2WRP_PAGE25         SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */
+#define SYSCFG_SRAM2WRP_PAGE26         SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */
+#define SYSCFG_SRAM2WRP_PAGE27         SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */
+#define SYSCFG_SRAM2WRP_PAGE28         SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */
+#define SYSCFG_SRAM2WRP_PAGE29         SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */
+#define SYSCFG_SRAM2WRP_PAGE30         SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */
+#define SYSCFG_SRAM2WRP_PAGE31         SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */
+
+/**
+  * @}
+  */
+
+#if defined(VREFBUF)
+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale
+  * @{
+  */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0  ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1  VREFBUF_CSR_VRS        /*!< Voltage reference scale 1 (VREF_OUT2) */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance
+  * @{
+  */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */
+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */
+
+/**
+  * @}
+  */
+#endif /* VREFBUF */
+
+/** @defgroup SYSCFG_flags_definition Flags
+  * @{
+  */
+
+#define SYSCFG_FLAG_SRAM2_PE            SYSCFG_CFGR2_SPF       /*!< SRAM2 parity error */
+#define SYSCFG_FLAG_SRAM2_BUSY          SYSCFG_SCSR_SRAM2BSY   /*!< SRAM2 busy by erase operation */
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */  
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#if defined(SYSCFG_CFGR1_I2C_PB8_FMP)
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#endif /* SYSCFG_CFGR1_I2C_PB8_FMP */
+#if defined(SYSCFG_CFGR1_I2C_PB9_FMP)
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+#endif /* SYSCFG_CFGR1_I2C_PB9_FMP */
+
+/**
+ * @}
+ */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
+  * @{
+  */
+
+/** @brief  Freeze/Unfreeze Peripherals in Debug mode
+  */
+#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM2()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM2()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM3()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM3()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM4()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM4()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM5()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM5()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM6()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM6()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM7()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM7()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_FREEZE_RTC()            SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#define __HAL_DBGMCU_UNFREEZE_RTC()          CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_WWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_WWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_FREEZE_IWDG()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#define __HAL_DBGMCU_UNFREEZE_IWDG()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT()   SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP)
+#define __HAL_DBGMCU_FREEZE_CAN1()           SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
+#define __HAL_DBGMCU_UNFREEZE_CAN1()         CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM1()         SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM1()       CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP)
+#endif
+
+#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_FREEZE_LPTIM2()         SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#define __HAL_DBGMCU_UNFREEZE_LPTIM2()       CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM1()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM1()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM8()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM8()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM15()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM15()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM16()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM16()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP)
+#endif
+
+#if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_FREEZE_TIM17()          SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#define __HAL_DBGMCU_UNFREEZE_TIM17()        CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP)
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
+  * @{
+  */
+
+/** @brief  Main Flash memory mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FLASH()       CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief  System Flash memory mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
+
+/** @brief  Embedded SRAM mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_SRAM()        MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0))
+
+/** @brief  FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_FMC()         MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
+
+/** @brief  QUADSPI mapped at 0x00000000.
+  */
+#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI()     MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1))
+
+/**
+  * @brief  Return the boot mode as configured by user.
+  * @retval The boot mode as configured by user. The returned value can be one
+  *         of the following values:
+  *           @arg @ref SYSCFG_BOOT_MAINFLASH
+  *           @arg @ref SYSCFG_BOOT_SYSTEMFLASH
+  *           @arg @ref SYSCFG_BOOT_FMC
+  *           @arg @ref SYSCFG_BOOT_SRAM
+  *           @arg @ref SYSCFG_BOOT_QUADSPI
+  */
+#define __HAL_SYSCFG_GET_BOOT_MODE()           READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
+
+/** @brief  SRAM2 page write protection enable macro
+  * @param __SRAM2WRP__: This parameter can be a value of @ref SYSCFG_SRAM2WRP
+  * @note   write protection can only be disabled by a system reset
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE(__SRAM2WRP__)   do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\
+                                                         SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\
+                                                        }while(0)
+
+/** @brief  SRAM2 page write protection unlock prior to erase
+  * @note   Writing a wrong key reactivates the write protection
+  */
+#define __HAL_SYSCFG_SRAM2_WRP_UNLOCK()      do {SYSCFG->SKR = 0xCA;\
+                                                 SYSCFG->SKR = 0x53;\
+                                                }while(0)
+
+/** @brief  SRAM2 erase
+  * @note   __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase
+  */
+#define __HAL_SYSCFG_SRAM2_ERASE()           SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER)
+
+/** @brief  Floating Point Unit interrupt enable/disable macros
+  * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts
+  */
+#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__)    do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
+                                                            }while(0)
+
+#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__)   do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\
+                                                            }while(0)
+
+/** @brief  SYSCFG Break ECC lock.
+  *         Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_ECC_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL)
+
+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.
+  *         Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK()     SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL)
+
+/** @brief  SYSCFG Break PVD lock.
+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register.
+  * @note   The selected configuration is locked and can be unlocked only by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_PVD_LOCK()        SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL)
+
+/** @brief  SYSCFG Break SRAM2 parity lock.
+  *         Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input.
+  * @note   The selected configuration is locked and can be unlocked by system reset.
+  */
+#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK()  SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL)
+
+/** @brief  Check SYSCFG flag is set or not.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg @ref SYSCFG_FLAG_SRAM2_PE   SRAM2 Parity Error Flag
+  *            @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SYSCFG_GET_FLAG(__FLAG__)      ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0)
+
+/** @brief  Set the SPF bit to clear the SRAM Parity Error Flag.
+  */
+#define __HAL_SYSCFG_CLEAR_FLAG()            SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF)
+
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__: This parameter can be a value of : 
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros
+  * @{
+  */
+
+#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \
+                                                (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC))
+
+#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_PVD)           || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY)  || \
+                                            ((__CONFIG__) == SYSCFG_BREAK_LOCKUP))
+
+#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__)   (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF))
+
+#if defined(VREFBUF)
+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
+
+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
+
+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
+#endif /* VREFBUF */
+
+#if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#elif defined(SYSCFG_FASTMODEPLUS_PB8)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8))
+#elif defined(SYSCFG_FASTMODEPLUS_PB9)
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+#else
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7))
+#endif
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+HAL_StatusTypeDef HAL_Init(void);
+HAL_StatusTypeDef HAL_DeInit(void);
+void HAL_MspInit(void);
+void HAL_MspDeInit(void);
+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group2
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_IncTick(void);
+void HAL_Delay(uint32_t Delay);
+uint32_t HAL_GetTick(void);
+void HAL_SuspendTick(void);
+void HAL_ResumeTick(void);
+uint32_t HAL_GetHalVersion(void);
+uint32_t HAL_GetREVID(void);
+uint32_t HAL_GetDEVID(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group3
+  * @{
+  */
+
+/* DBGMCU Peripheral Control functions  *****************************************/
+void HAL_DBGMCU_EnableDBGSleepMode(void);
+void HAL_DBGMCU_DisableDBGSleepMode(void);
+void HAL_DBGMCU_EnableDBGStopMode(void);
+void HAL_DBGMCU_DisableDBGStopMode(void);
+void HAL_DBGMCU_EnableDBGStandbyMode(void);
+void HAL_DBGMCU_DisableDBGStandbyMode(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HAL_Exported_Functions_Group4
+  * @{
+  */
+
+/* SYSCFG Control functions  ****************************************************/
+void HAL_SYSCFG_SRAM2Erase(void);
+void HAL_SYSCFG_EnableMemorySwappingBank(void);
+void HAL_SYSCFG_DisableMemorySwappingBank(void);
+
+#if defined(VREFBUF)
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
+void HAL_SYSCFG_DisableVREFBUF(void);
+#endif /* VREFBUF */
+
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void);
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_can.h

@@ -0,0 +1,768 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_can.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of CAN HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_CAN_H
+#define __STM32L4xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_CAN_STATE_RESET             = 0x00,  /*!< CAN not yet initialized or disabled */
+  HAL_CAN_STATE_READY             = 0x01,  /*!< CAN initialized and ready for use   */
+  HAL_CAN_STATE_BUSY              = 0x02,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX           = 0x12,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX           = 0x22,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX        = 0x32,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_TIMEOUT           = 0x03,  /*!< Timeout state                       */
+  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;  /*!< Specifies the length of a time quantum.
+                            This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+  uint32_t Mode;       /*!< Specifies the CAN operating mode.
+                            This parameter can be a value of @ref CAN_operating_mode */
+
+  uint32_t SJW;        /*!< Specifies the maximum number of time quanta
+                            the CAN hardware is allowed to lengthen or
+                            shorten a bit to perform resynchronization.
+                            This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint32_t BS1;        /*!< Specifies the number of time quanta in Bit Segment 1.
+                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint32_t BS2;        /*!< Specifies the number of time quanta in Bit Segment 2.
+                            This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+  uint32_t TTCM;       /*!< Enable or disable the time triggered communication mode.
+                            This parameter can be set to ENABLE or DISABLE. */
+
+  uint32_t ABOM;       /*!< Enable or disable the automatic bus-off management.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t AWUM;       /*!< Enable or disable the automatic wake-up mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t NART;       /*!< Enable or disable the non-automatic retransmission mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t RFLM;       /*!< Enable or disable the receive FIFO Locked mode.
+                            This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t TXFP;       /*!< Enable or disable the transmit FIFO priority.
+                            This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+  * @brief  CAN filter configuration structure definition
+  */
+typedef struct
+{
+  uint32_t FilterIdHigh;          /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                       configuration, first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterIdLow;           /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                       configuration, second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterMaskIdHigh;      /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (MSBs for a 32-bit configuration,
+                                       first one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterMaskIdLow;       /*!< Specifies the filter mask number or identification number,
+                                       according to the mode (LSBs for a 32-bit configuration,
+                                       second one for a 16-bit configuration).
+                                       This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+  uint32_t FilterFIFOAssignment;  /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                       This parameter can be a value of @ref CAN_filter_FIFO */
+
+  uint32_t FilterNumber;          /*!< Specifies the filter which will be initialized.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+  uint32_t FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                       This parameter can be a value of @ref CAN_filter_mode */
+
+  uint32_t FilterScale;           /*!< Specifies the filter scale.
+                                       This parameter can be a value of @ref CAN_filter_scale */
+
+  uint32_t FilterActivation;      /*!< Enable or disable the filter.
+                                       This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t BankNumber;            /*!< Select the start slave bank filter.
+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 28 */ 
+
+}CAN_FilterConfTypeDef;
+
+/**
+  * @brief  CAN Tx message structure definition
+  */
+typedef struct
+{
+  uint32_t StdId;    /*!< Specifies the standard identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+  uint32_t ExtId;    /*!< Specifies the extended identifier.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+  uint32_t IDE;      /*!< Specifies the type of identifier for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;      /*!< Specifies the type of frame for the message that will be transmitted.
+                          This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;      /*!< Specifies the length of the frame that will be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+  uint8_t Data[8];   /*!< Contains the data to be transmitted.
+                          This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+  * @brief  CAN Rx message structure definition
+  */
+typedef struct
+{
+  uint32_t StdId;       /*!< Specifies the standard identifier.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+  uint32_t ExtId;       /*!< Specifies the extended identifier.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+  uint32_t IDE;         /*!< Specifies the type of identifier for the message that will be received.
+                             This parameter can be a value of @ref CAN_identifier_type */
+
+  uint32_t RTR;         /*!< Specifies the type of frame for the received message.
+                             This parameter can be a value of @ref CAN_remote_transmission_request */
+
+  uint32_t DLC;         /*!< Specifies the length of the frame that will be received.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+  uint32_t Data[8];     /*!< Contains the data to be received.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+  uint32_t FMI;         /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+                             This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+  uint32_t FIFONumber;  /*!< Specifies the receive FIFO number.
+                             This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+  * @brief  CAN handle Structure definition
+  */
+typedef struct
+{
+  CAN_TypeDef                 *Instance;  /*!< Register base address          */
+
+  CAN_InitTypeDef             Init;       /*!< CAN required parameters        */
+
+  CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
+
+  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
+
+  __IO HAL_CAN_StateTypeDef   State;      /*!< CAN communication state        */
+
+  HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
+
+  __IO uint32_t               ErrorCode;  /*!< CAN Error code                 */
+
+}CAN_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+  * @{
+  */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+  * @{
+  */
+#define   HAL_CAN_ERROR_NONE        ((uint32_t)0x00000000)    /*!< No error             */
+#define   HAL_CAN_ERROR_EWG         ((uint32_t)0x00000001)    /*!< EWG error            */
+#define   HAL_CAN_ERROR_EPV         ((uint32_t)0x00000002)    /*!< EPV error            */
+#define   HAL_CAN_ERROR_BOF         ((uint32_t)0x00000004)    /*!< BOF error            */
+#define   HAL_CAN_ERROR_STF         ((uint32_t)0x00000008)    /*!< Stuff error          */
+#define   HAL_CAN_ERROR_FOR         ((uint32_t)0x00000010)    /*!< Form error           */
+#define   HAL_CAN_ERROR_ACK         ((uint32_t)0x00000020)    /*!< Acknowledgment error */
+#define   HAL_CAN_ERROR_BR          ((uint32_t)0x00000040)    /*!< Bit recessive        */
+#define   HAL_CAN_ERROR_BD          ((uint32_t)0x00000080)    /*!< LEC dominant         */
+#define   HAL_CAN_ERROR_CRC         ((uint32_t)0x00000100)   /*!< LEC transfer error   */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_InitStatus CAN initialization Status
+  * @{
+  */
+#define CAN_INITSTATUS_FAILED       ((uint32_t)0x00000000)  /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS      ((uint32_t)0x00000001)  /*!< CAN initialization OK */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+  * @{
+  */
+#define CAN_MODE_NORMAL             ((uint32_t)0x00000000)                     /*!< Normal mode   */
+#define CAN_MODE_LOOPBACK           ((uint32_t)CAN_BTR_LBKM)                   /*!< Loopback mode */
+#define CAN_MODE_SILENT             ((uint32_t)CAN_BTR_SILM)                   /*!< Silent mode   */
+#define CAN_MODE_SILENT_LOOPBACK    ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM))  /*!< Loopback combined with silent mode */
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
+  * @{
+  */
+#define CAN_SJW_1TQ                 ((uint32_t)0x00000000)     /*!< 1 time quantum */
+#define CAN_SJW_2TQ                 ((uint32_t)CAN_BTR_SJW_0)  /*!< 2 time quantum */
+#define CAN_SJW_3TQ                 ((uint32_t)CAN_BTR_SJW_1)  /*!< 3 time quantum */
+#define CAN_SJW_4TQ                 ((uint32_t)CAN_BTR_SJW)    /*!< 4 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
+  * @{
+  */
+#define CAN_BS1_1TQ                 ((uint32_t)0x00000000)                                       /*!< 1 time quantum  */
+#define CAN_BS1_2TQ                 ((uint32_t)CAN_BTR_TS1_0)                                    /*!< 2 time quantum  */
+#define CAN_BS1_3TQ                 ((uint32_t)CAN_BTR_TS1_1)                                    /*!< 3 time quantum  */
+#define CAN_BS1_4TQ                 ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0))                  /*!< 4 time quantum  */
+#define CAN_BS1_5TQ                 ((uint32_t)CAN_BTR_TS1_2)                                    /*!< 5 time quantum  */
+#define CAN_BS1_6TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0))                  /*!< 6 time quantum  */
+#define CAN_BS1_7TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1))                  /*!< 7 time quantum  */
+#define CAN_BS1_8TQ                 ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 8 time quantum  */
+#define CAN_BS1_9TQ                 ((uint32_t)CAN_BTR_TS1_3)                                    /*!< 9 time quantum  */
+#define CAN_BS1_10TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0))                  /*!< 10 time quantum */
+#define CAN_BS1_11TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1))                  /*!< 11 time quantum */
+#define CAN_BS1_12TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0))  /*!< 12 time quantum */
+#define CAN_BS1_13TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2))                  /*!< 13 time quantum */
+#define CAN_BS1_14TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0))  /*!< 14 time quantum */
+#define CAN_BS1_15TQ                ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1))  /*!< 15 time quantum */
+#define CAN_BS1_16TQ                ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
+  * @{
+  */
+#define CAN_BS2_1TQ                 ((uint32_t)0x00000000)                       /*!< 1 time quantum */
+#define CAN_BS2_2TQ                 ((uint32_t)CAN_BTR_TS2_0)                    /*!< 2 time quantum */
+#define CAN_BS2_3TQ                 ((uint32_t)CAN_BTR_TS2_1)                    /*!< 3 time quantum */
+#define CAN_BS2_4TQ                 ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0))  /*!< 4 time quantum */
+#define CAN_BS2_5TQ                 ((uint32_t)CAN_BTR_TS2_2)                    /*!< 5 time quantum */
+#define CAN_BS2_6TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0))  /*!< 6 time quantum */
+#define CAN_BS2_7TQ                 ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1))  /*!< 7 time quantum */
+#define CAN_BS2_8TQ                 ((uint32_t)CAN_BTR_TS2)                      /*!< 8 time quantum */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+  * @{
+  */
+#define CAN_FILTERMODE_IDMASK       ((uint8_t)0x00)  /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST       ((uint8_t)0x01)  /*!< Identifier list mode */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+  * @{
+  */
+#define CAN_FILTERSCALE_16BIT       ((uint8_t)0x00)  /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT       ((uint8_t)0x01)  /*!< One 32-bit filter  */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+  * @{
+  */
+#define CAN_FILTER_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type CAN Identifier Type
+  * @{
+  */
+#define CAN_ID_STD             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_ID_EXT             ((uint32_t)0x00000004)  /*!< Extended Id */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+  * @{
+  */
+#define CAN_RTR_DATA                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_REMOTE              ((uint32_t)0x00000002)  /*!< Remote frame */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number
+  * @{
+  */
+#define CAN_FIFO0                   ((uint8_t)0x00)  /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                   ((uint8_t)0x01)  /*!< CAN FIFO 1 used to receive */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags CAN Flags
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x00000500)  /*!< Request MailBox0 flag         */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x00000508)  /*!< Request MailBox1 flag         */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x00000510)  /*!< Request MailBox2 flag         */
+#define CAN_FLAG_TXOK0             ((uint32_t)0x00000501)  /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1             ((uint32_t)0x00000509)  /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2             ((uint32_t)0x00000511)  /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0              ((uint32_t)0x0000051A)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1              ((uint32_t)0x0000051B)  /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2              ((uint32_t)0x0000051C)  /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0               ((uint32_t)0x00000203)  /*!< FIFO 0 Full flag    */
+#define CAN_FLAG_FOV0              ((uint32_t)0x00000204)  /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1               ((uint32_t)0x00000403)  /*!< FIFO 1 Full flag    */
+#define CAN_FLAG_FOV1              ((uint32_t)0x00000404)  /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x00000103)  /*!< Wake up flag           */
+#define CAN_FLAG_SLAK              ((uint32_t)0x00000101)  /*!< Sleep acknowledge flag */
+#define CAN_FLAG_SLAKI             ((uint32_t)0x00000104)  /*!< Sleep acknowledge flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x00000300)  /*!< Error warning flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x00000301)  /*!< Error passive flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x00000302)  /*!< Bus-Off flag         */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_interrupts CAN Interrupts
+  * @{
+  */
+#define CAN_IT_TME                  ((uint32_t)CAN_IER_TMEIE)   /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)CAN_IER_FMPIE0)  /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0                  ((uint32_t)CAN_IER_FFIE0)   /*!< FIFO 0 full interrupt            */
+#define CAN_IT_FOV0                 ((uint32_t)CAN_IER_FOVIE0)  /*!< FIFO 0 overrun interrupt         */
+#define CAN_IT_FMP1                 ((uint32_t)CAN_IER_FMPIE1)  /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1                  ((uint32_t)CAN_IER_FFIE1)   /*!< FIFO 1 full interrupt            */
+#define CAN_IT_FOV1                 ((uint32_t)CAN_IER_FOVIE1)  /*!< FIFO 1 overrun interrupt         */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)CAN_IER_WKUIE)  /*!< Wake-up interrupt           */
+#define CAN_IT_SLK                  ((uint32_t)CAN_IER_SLKIE)  /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt   */
+#define CAN_IT_EPV                  ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt   */
+#define CAN_IT_BOF                  ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt         */
+#define CAN_IT_LEC                  ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR                  ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt           */
+
+/**
+  * @}
+  */
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02)
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macro CAN Exported Macros
+  * @{
+  */
+
+/** @brief  Reset CAN handle state.
+  * @param  __HANDLE__: CAN handle.
+  * @retval None
+  */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+  * @brief  Enable the specified CAN interrupt.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __INTERRUPT__: CAN Interrupt.
+  * @retval None
+  */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified CAN interrupt.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __INTERRUPT__: CAN Interrupt.
+  * @retval None
+  */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Return the number of pending received messages.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval The number of pending message.
+  */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+
+/** @brief  Check whether the specified CAN flag is set or not.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief  Clear the specified CAN pending flag.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __FLAG__: specifies the flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+  *            @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+  *            @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+  *            @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+  *            @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+  *            @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0)
+
+
+/** @brief  Check whether the specified CAN interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
+  *         This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+  *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
+  *            @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+  * @brief  Check the transmission status of a CAN Frame.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @retval The new status of transmission  (TRUE or FALSE).
+  */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+
+
+/**
+  * @brief  Release the specified receive FIFO.
+  * @param  __HANDLE__: CAN handle.
+  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None
+  */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R |= CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R |= CAN_RF1R_RFOM1)) 
+
+/**
+  * @brief  Cancel a transmit request.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @retval None
+  */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR |= CAN_TSR_ABRQ2))
+
+/**
+  * @brief  Enable or disable the DBG Freeze for CAN.
+  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __NEWSTATE__: new state of the CAN peripheral. 
+  *         This parameter can be: ENABLE (CAN reception/transmission is frozen
+  *         during debug. Reception FIFO can still be accessed/controlled normally) 
+  *         or DISABLE (CAN is working during debug).
+  * @retval None
+  */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) 
+
+/**
+ * @}
+ */  
+ 
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
+  * @{
+  */
+  
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ * @{
+ */
+/* addtogroup and de-initialization functions *****************************/ 
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */ 
+ 
+/** @addtogroup CAN_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief    I/O operation functions 
+ * @{
+ */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */ 
+ 
+/** @addtogroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ *  @brief   CAN Peripheral State functions 
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */ 
+
+/**
+ * @}
+ */ 
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+  * @{
+  */
+/** @defgroup CAN_transmit_constants CAN Transmit Constants
+  * @{
+  */
+#define CAN_TXSTATUS_NOMAILBOX      ((uint8_t)0x04)  /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+/**
+  * @}
+  */
+#define CAN_FLAG_MASK     ((uint32_t)0x000000FF)
+
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+  * @{
+  */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+                           ((MODE) == CAN_MODE_LOOPBACK)|| \
+                           ((MODE) == CAN_MODE_SILENT) || \
+                           ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+                         ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+                                  ((MODE) == CAN_FILTERMODE_IDLIST))
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+                                    ((SCALE) == CAN_FILTERSCALE_32BIT))
+
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+                                  ((FIFO) == CAN_FILTER_FIFO1))
+
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE)  (((IDTYPE) == CAN_ID_STD) || \
+                                ((IDTYPE) == CAN_ID_EXT))
+
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_CAN_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_cortex.h

@@ -0,0 +1,467 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cortex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of CORTEX HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CORTEX_H
+#define __STM32L4xx_HAL_CORTEX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup CORTEX CORTEX
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
+  * @{
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
+  * @{
+  */
+typedef struct
+{
+  uint8_t                Enable;                /*!< Specifies the status of the region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */
+  uint8_t                Number;                /*!< Specifies the number of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */
+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */
+  uint8_t                Size;                  /*!< Specifies the size of the region to protect. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */
+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable. 
+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */
+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.
+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */
+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */
+  uint8_t                DisableExec;           /*!< Specifies the instruction access status. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */
+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */
+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */
+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region. 
+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */
+}MPU_Region_InitTypeDef;
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
+  * @{
+  */
+
+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
+  * @{
+  */
+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bit  for pre-emption priority,
+                                                                 4 bits for subpriority */
+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bit  for pre-emption priority,
+                                                                 3 bits for subpriority */
+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority,
+                                                                 2 bits for subpriority */
+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority,
+                                                                 1 bit  for subpriority */
+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority,
+                                                                 0 bit  for subpriority */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
+  * @{
+  */
+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
+/**
+  * @}
+  */
+
+#if (__MPU_PRESENT == 1)
+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
+  * @{
+  */
+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)
+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)
+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)
+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
+  * @{
+  */
+#define  MPU_REGION_ENABLE           ((uint8_t)0x01)
+#define  MPU_REGION_DISABLE          ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
+  * @{
+  */
+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)
+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
+  * @{
+  */
+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
+  * @{
+  */
+#define  MPU_ACCESS_CACHEABLE        ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_CACHEABLE    ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
+  * @{
+  */
+#define  MPU_ACCESS_BUFFERABLE       ((uint8_t)0x01)
+#define  MPU_ACCESS_NOT_BUFFERABLE   ((uint8_t)0x00)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels
+  * @{
+  */
+#define  MPU_TEX_LEVEL0              ((uint8_t)0x00)
+#define  MPU_TEX_LEVEL1              ((uint8_t)0x01)
+#define  MPU_TEX_LEVEL2              ((uint8_t)0x02)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
+  * @{
+  */
+#define   MPU_REGION_SIZE_32B        ((uint8_t)0x04)
+#define   MPU_REGION_SIZE_64B        ((uint8_t)0x05)
+#define   MPU_REGION_SIZE_128B       ((uint8_t)0x06)
+#define   MPU_REGION_SIZE_256B       ((uint8_t)0x07)
+#define   MPU_REGION_SIZE_512B       ((uint8_t)0x08)
+#define   MPU_REGION_SIZE_1KB        ((uint8_t)0x09)
+#define   MPU_REGION_SIZE_2KB        ((uint8_t)0x0A)
+#define   MPU_REGION_SIZE_4KB        ((uint8_t)0x0B)
+#define   MPU_REGION_SIZE_8KB        ((uint8_t)0x0C)
+#define   MPU_REGION_SIZE_16KB       ((uint8_t)0x0D)
+#define   MPU_REGION_SIZE_32KB       ((uint8_t)0x0E)
+#define   MPU_REGION_SIZE_64KB       ((uint8_t)0x0F)
+#define   MPU_REGION_SIZE_128KB      ((uint8_t)0x10)
+#define   MPU_REGION_SIZE_256KB      ((uint8_t)0x11)
+#define   MPU_REGION_SIZE_512KB      ((uint8_t)0x12)
+#define   MPU_REGION_SIZE_1MB        ((uint8_t)0x13)
+#define   MPU_REGION_SIZE_2MB        ((uint8_t)0x14)
+#define   MPU_REGION_SIZE_4MB        ((uint8_t)0x15)
+#define   MPU_REGION_SIZE_8MB        ((uint8_t)0x16)
+#define   MPU_REGION_SIZE_16MB       ((uint8_t)0x17)
+#define   MPU_REGION_SIZE_32MB       ((uint8_t)0x18)
+#define   MPU_REGION_SIZE_64MB       ((uint8_t)0x19)
+#define   MPU_REGION_SIZE_128MB      ((uint8_t)0x1A)
+#define   MPU_REGION_SIZE_256MB      ((uint8_t)0x1B)
+#define   MPU_REGION_SIZE_512MB      ((uint8_t)0x1C)
+#define   MPU_REGION_SIZE_1GB        ((uint8_t)0x1D)
+#define   MPU_REGION_SIZE_2GB        ((uint8_t)0x1E)
+#define   MPU_REGION_SIZE_4GB        ((uint8_t)0x1F)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 
+  * @{
+  */
+#define  MPU_REGION_NO_ACCESS        ((uint8_t)0x00)
+#define  MPU_REGION_PRIV_RW          ((uint8_t)0x01)
+#define  MPU_REGION_PRIV_RW_URO      ((uint8_t)0x02)
+#define  MPU_REGION_FULL_ACCESS      ((uint8_t)0x03)
+#define  MPU_REGION_PRIV_RO          ((uint8_t)0x05)
+#define  MPU_REGION_PRIV_RO_URO      ((uint8_t)0x06)
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
+  * @{
+  */
+#define  MPU_REGION_NUMBER0          ((uint8_t)0x00)
+#define  MPU_REGION_NUMBER1          ((uint8_t)0x01)
+#define  MPU_REGION_NUMBER2          ((uint8_t)0x02)
+#define  MPU_REGION_NUMBER3          ((uint8_t)0x03)
+#define  MPU_REGION_NUMBER4          ((uint8_t)0x04)
+#define  MPU_REGION_NUMBER5          ((uint8_t)0x05)
+#define  MPU_REGION_NUMBER6          ((uint8_t)0x06)
+#define  MPU_REGION_NUMBER7          ((uint8_t)0x07)
+/**
+  * @}
+  */
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
+  * @{
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and Configuration functions *****************************/
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SystemReset(void);
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Disable the MPU.
+  * @retval None
+  */
+__STATIC_INLINE void HAL_MPU_Disable(void)
+{
+  /* Disable fault exceptions */
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+  
+  /* Disable the MPU */
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/**
+  * @brief  Enable the MPU.
+  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+  *          NMI, FAULTMASK and privileged accessto the default memory 
+  *          This parameter can be one of the following values:
+  *            @arg MPU_HFNMI_PRIVDEF_NONE
+  *            @arg MPU_HARDFAULT_NMI
+  *            @arg MPU_PRIVILEGED_DEFAULT
+  *            @arg MPU_HFNMI_PRIVDEF
+  * @retval None
+  */
+__STATIC_INLINE void HAL_MPU_Enable(uint32_t MPU_Control)
+{
+  /* Enable the MPU */
+  MPU->CTRL   = MPU_Control | MPU_CTRL_ENABLE_Msk;
+  
+  /* Enable fault exceptions */
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+}
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 
+  * @brief   Cortex control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_NVIC_GetPriorityGrouping(void);
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
+void HAL_SYSTICK_IRQHandler(void);
+void HAL_SYSTICK_Callback(void);
+
+#if (__MPU_PRESENT == 1)
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
+#endif /* __MPU_PRESENT */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
+  * @{
+  */
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10)
+
+#define IS_NVIC_DEVICE_IRQ(IRQ)                ((IRQ) >= 0x00)
+
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
+
+#if (__MPU_PRESENT == 1)
+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
+                                     ((STATE) == MPU_REGION_DISABLE))
+
+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
+
+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
+
+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
+
+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \
+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
+
+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \
+                                ((TYPE) == MPU_TEX_LEVEL1)  || \
+                                ((TYPE) == MPU_TEX_LEVEL2))
+
+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \
+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))
+
+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER1) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER2) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER3) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER4) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER5) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER6) || \
+                                         ((NUMBER) == MPU_REGION_NUMBER7))
+
+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \
+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \
+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \
+                                     ((SIZE) == MPU_REGION_SIZE_4GB))
+
+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CORTEX_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac.h

@@ -0,0 +1,479 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of DAC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DAC_H
+#define __STM32L4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+typedef enum
+{
+  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
+ 
+}HAL_DAC_StateTypeDef;
+ 
+/** 
+  * @brief  DAC handle Structure definition  
+  */ 
+typedef struct
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+  
+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
+
+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
+  
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+  
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
+  
+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
+  
+}DAC_HandleTypeDef;
+
+/** 
+  * @brief   DAC Configuration sample and hold Channel structure definition  
+  */ 
+typedef struct
+{
+  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */  
+
+  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */    
+  
+  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */  
+}
+DAC_SampleAndHoldConfTypeDef;
+
+/** 
+  * @brief   DAC Configuration regular Channel structure definition  
+  */ 
+typedef struct
+{
+  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
+                                              This parameter can be a value of @ref DAC_SampleAndHold */
+  
+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection */
+  
+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref DAC_output_buffer */
+
+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .
+                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
+  
+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode 
+                                              This parameter must be a value of @ref DAC_UserTrimming 
+                                              DAC_UserTrimming is either factory or user trimming */
+                                        
+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value 
+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */ 
+      
+}DAC_ChannelConfTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+  * @{
+  */
+#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */
+#define  HAL_DAC_ERROR_TIMEOUT           0x08    /*!< Timeout error                     */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+  * @{
+  */
+
+#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2 |DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO                ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO                ((uint32_t)(DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
+
+/**
+  * @}
+  */   
+
+/** @defgroup DAC_output_buffer DAC output buffer
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
+#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_MCR_MODE1_1)
+
+/**
+  * @}
+  */
+    
+/** @defgroup DAC_Channel_selection DAC Channel selection
+  * @{
+  */
+#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
+#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment DAC data alignment
+  * @{
+  */
+#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
+#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
+#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+  * @{
+  */ 
+#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_IT_definition  DAC IT definition
+  * @{
+  */ 
+#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
+
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+  * @{
+  */
+#define DAC_CHIPCONNECT_DISABLE  ((uint32_t)0x00000000)
+#define DAC_CHIPCONNECT_ENABLE     ((uint32_t)DAC_MCR_MODE1_0)
+
+/**
+  * @}
+  */
+
+  /** @defgroup DAC_UserTrimming DAC User Trimming
+  * @{
+  */
+
+#define DAC_TRIMMING_FACTORY        ((uint32_t)0x00000000)           /*!< Factory trimming */
+#define DAC_TRIMMING_USER           ((uint32_t)0x00000001)           /*!< User trimming */
+   
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_SampleAndHold DAC power mode
+  * @{
+  */
+#define DAC_SAMPLEANDHOLD_DISABLE     ((uint32_t)0x00000000)
+#define DAC_SAMPLEANDHOLD_ENABLE      ((uint32_t)DAC_MCR_MODE1_2)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @brief Reset DAC handle state.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @retval None
+  */
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+
+/** @brief Enable the DAC channel.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __DAC_Channel__: specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
+
+/** @brief Disable the DAC channel.
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __DAC_Channel__: specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
+ 
+/** @brief Set DHR12R1 alignment.
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
+
+/** @brief  Set DHR12R2 alignment.
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
+
+/** @brief  Set DHR12RD alignment.
+  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt.
+  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief  Check whether the specified DAC interrupt source is enabled or not.
+  * @param __HANDLE__: DAC handle
+  * @param __INTERRUPT__: DAC interrupt source to check
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Get the selected DAC's flag status.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the DAC flag to get.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @retval None
+  */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the DAC's flag.
+  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __FLAG__: specifies the DAC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  * @retval None
+  */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+  * @}
+  */ 
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+  * @{
+  */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
+                                ((CHANNEL) == DAC_CHANNEL_2))
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+
+#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x0000000FF)
+
+/**
+  * @}
+  */
+  
+/* Include DAC HAL Extended module */
+#include "stm32l4xx_hal_dac_ex.h"   
+
+/* Exported functions --------------------------------------------------------*/  
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */  
+/* Initialization and de-initialization functions *****************************/ 
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+ * @{
+ */    
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
+
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+  * @{
+  */ 
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+  * @{
+  */     
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif 
+  
+
+#endif /*__STM32L4xx_HAL_DAC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dac_ex.h

@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of DAC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DAC_EX_H
+#define __STM32L4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+           
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DACEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+   
+/** 
+  * @brief  HAL State structures definition  
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+  * @{
+  */ 
+    
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+  * @}
+  */       
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+  * @{
+  */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))      
+
+#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x0000003FF)
+
+#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x0000003FF)
+
+#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
+                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
+
+
+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1F)
+
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
+
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+                                     ((TRIMMING) == DAC_TRIMMING_USER))
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+ * @{
+ */    
+/* IO operation functions *****************************************************/
+  
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group3
+  * @{
+  */ 
+/* Peripheral Control functions ***********************************************/
+
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
+uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
+   
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Private_Functions
+  * @{
+  */
+
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+/**
+ * @}
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif   
+
+#endif /*__STM32L4xx_HAL_DAC_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_def.h

@@ -0,0 +1,215 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_def.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   This file contains HAL common defines, enumeration, macros and
+  *          structures definitions.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DEF
+#define __STM32L4xx_HAL_DEF
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx.h"
+#include "Legacy/stm32_hal_legacy.h"  /* Aliases file for old names compatibility */
+#include <stdio.h>
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL Status structures definition
+  */
+typedef enum
+{
+  HAL_OK       = 0x00,
+  HAL_ERROR    = 0x01,
+  HAL_BUSY     = 0x02,
+  HAL_TIMEOUT  = 0x03
+} HAL_StatusTypeDef;
+
+/**
+  * @brief  HAL Lock structures definition
+  */
+typedef enum
+{
+  HAL_UNLOCKED = 0x00,
+  HAL_LOCKED   = 0x01
+} HAL_LockTypeDef;
+
+/* Exported macros -----------------------------------------------------------*/
+
+#define HAL_MAX_DELAY      0xFFFFFFFF
+
+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))
+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
+
+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)             \
+                        do{                                                      \
+                            (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
+                            (__DMA_HANDLE__).Parent = (__HANDLE__);              \
+                        } while(0)
+
+#define UNUSED(x) ((void)(x))
+                         
+/** @brief Reset the Handle's State field.
+  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @note  This macro can be used for the following purpose: 
+  *          - When the Handle is declared as local variable; before passing it as parameter
+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
+  *            to set to 0 the Handle's "State" field.
+  *            Otherwise, "State" field may have any random value and the first time the function 
+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
+  *            (i.e. HAL_PPP_MspInit() will not be executed).
+  *          - When there is a need to reconfigure the low level hardware: instead of calling
+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
+  * @retval None
+  */
+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
+
+#if (USE_RTOS == 1)
+  /* Reserved for future use */
+  #error " USE_RTOS should be 0 in the current HAL release "
+#else
+  #define __HAL_LOCK(__HANDLE__)                                           \
+                                do{                                        \
+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \
+                                    {                                      \
+                                       return HAL_BUSY;                    \
+                                    }                                      \
+                                    else                                   \
+                                    {                                      \
+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
+                                    }                                      \
+                                  }while (0)
+
+  #define __HAL_UNLOCK(__HANDLE__)                                          \
+                                  do{                                       \
+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \
+                                    }while (0)
+#endif /* USE_RTOS */
+
+#if  defined ( __GNUC__ )
+  #ifndef __weak
+    #define __weak   __attribute__((weak))
+  #endif /* __weak */
+  #ifndef __packed
+    #define __packed __attribute__((__packed__))
+  #endif /* __packed */
+#endif /* __GNUC__ */
+
+
+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
+#if defined   (__GNUC__)        /* GNU Compiler */
+  #ifndef __ALIGN_END
+    #define __ALIGN_END    __attribute__ ((aligned (4)))
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #define __ALIGN_BEGIN
+  #endif /* __ALIGN_BEGIN */
+#else
+  #ifndef __ALIGN_END
+    #define __ALIGN_END
+  #endif /* __ALIGN_END */
+  #ifndef __ALIGN_BEGIN
+    #if defined   (__CC_ARM)      /* ARM Compiler */
+      #define __ALIGN_BEGIN    __align(4)
+    #elif defined (__ICCARM__)    /* IAR Compiler */
+      #define __ALIGN_BEGIN
+    #endif /* __CC_ARM */
+  #endif /* __ALIGN_BEGIN */
+#endif /* __GNUC__ */
+
+/**
+  * @brief  __RAM_FUNC definition
+  */
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options.
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const'
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog.
+*/
+#define __RAM_FUNC HAL_StatusTypeDef
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc".
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
+
+#endif
+
+/** 
+  * @brief  __NOINLINE definition
+  */ 
+#if defined ( __CC_ARM   ) || defined   (  __GNUC__  )
+/* ARM & GNUCompiler 
+   ---------------- 
+*/
+#define __NOINLINE __attribute__ ( (noinline) )  
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+*/
+#define __NOINLINE _Pragma("optimize = no_inline")
+
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ___STM32L4xx_HAL_DEF */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_dma.h

@@ -0,0 +1,588 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of DMA HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_DMA_H
+#define __STM32L4xx_HAL_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DMA_Exported_Types DMA Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DMA Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Request;                   /*!< Specifies the request selected for the specified channel.
+                                           This parameter can be a value of @ref DMA_request */
+
+  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral,
+                                           from memory to memory or from peripheral to memory.
+                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
+
+  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
+
+  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
+                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
+
+  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
+                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
+
+  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
+                                           This parameter can be a value of @ref DMA_Memory_data_size */
+
+  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_mode
+                                           @note The circular buffer mode cannot be used if the memory-to-memory
+                                                 data transfer is configured on the selected Channel */
+
+  uint32_t Priority;                  /*!< Specifies the software priority for the DMAy Channelx.
+                                           This parameter can be a value of @ref DMA_Priority_level */
+} DMA_InitTypeDef;
+
+/**
+  * @brief DMA Configuration enumeration values definition
+  */
+typedef enum
+{
+  DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
+  DMA_PRIORITY        = 1       /*!< Control related priority level Parameter in DMA_InitTypeDef  */
+
+} DMA_ControlTypeDef;
+
+/**
+  * @brief  HAL DMA State structures definition
+  */
+typedef enum
+{
+  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled    */
+  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use  */
+  HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success               */
+  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing                 */
+  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                      */
+  HAL_DMA_STATE_ERROR             = 0x04   /*!< DMA error state                        */
+}HAL_DMA_StateTypeDef;
+
+/**
+  * @brief  HAL DMA Error Code structure definition
+  */
+typedef enum
+{
+  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
+  HAL_DMA_HALF_TRANSFER      = 0x01     /*!< Half Transfer     */
+}HAL_DMA_LevelCompleteTypeDef;
+
+/**
+  * @brief  DMA handle Structure definition
+  */
+typedef struct __DMA_HandleTypeDef
+{
+  DMA_Channel_TypeDef    *Instance;                                                /*!< Register base address                  */
+                                                                                
+  DMA_InitTypeDef       Init;                                                      /*!< DMA communication parameters           */
+                                                                                
+  HAL_LockTypeDef       Lock;                                                      /*!< DMA locking object                     */
+                                                                                
+  __IO HAL_DMA_StateTypeDef  State;                                                /*!< DMA transfer state                     */
+                                                                                
+  void                  *Parent;                                                   /*!< Parent object state                    */
+
+  void                  (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback       */
+
+  void                  (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback  */
+
+  void                  (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback          */
+
+  __IO uint32_t          ErrorCode;                                                /*!< DMA Error code                         */
+}DMA_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants DMA Exported Constants
+  * @{
+  */
+
+/** @defgroup DMA_Error_Code DMA Error Code
+  * @{
+  */
+#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
+#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
+#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_request DMA request
+  * @{
+  */
+#define DMA_REQUEST_0                     ((uint32_t)0x00000000)
+#define DMA_REQUEST_1                     ((uint32_t)0x00000001)
+#define DMA_REQUEST_2                     ((uint32_t)0x00000002)
+#define DMA_REQUEST_3                     ((uint32_t)0x00000003)
+#define DMA_REQUEST_4                     ((uint32_t)0x00000004)
+#define DMA_REQUEST_5                     ((uint32_t)0x00000005)
+#define DMA_REQUEST_6                     ((uint32_t)0x00000006)
+#define DMA_REQUEST_7                     ((uint32_t)0x00000007)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
+  * @{
+  */
+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_CCR_MEM2MEM)   /*!< Memory to memory direction     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
+  * @{
+  */
+#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)  /*!< Peripheral increment mode Enable */
+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)    /*!< Peripheral increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
+  * @{
+  */
+#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
+  * @{
+  */
+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Memory_data_size DMA Memory data size
+  * @{
+  */
+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_mode DMA mode
+  * @{
+  */
+#define DMA_NORMAL         ((uint32_t)0x00000000)       /*!< Normal mode                  */
+#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)     /*!< Circular mode                */
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Priority_level DMA Priority level
+  * @{
+  */
+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
+/**
+  * @}
+  */
+
+
+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
+  * @{
+  */
+#define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
+#define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
+#define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_flag_definitions DMA flag definitions
+  * @{
+  */
+#define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
+#define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
+#define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
+#define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
+#define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
+#define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
+#define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
+#define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
+#define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
+#define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
+#define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
+#define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
+#define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
+#define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
+#define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
+#define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
+#define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
+#define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
+#define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
+#define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
+#define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
+#define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
+#define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
+#define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
+#define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
+#define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
+#define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
+#define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DMA_Exported_Macros DMA Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DMA handle state.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |=  DMA_CCR_EN)
+
+/**
+  * @brief  Disable the specified DMA Channel.
+  * @param  __HANDLE__: DMA handle
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &=  ~DMA_CCR_EN)
+
+
+/* Interrupt & Flag management */
+
+/**
+  * @brief  Return the current DMA Channel transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer complete flag index.
+  */
+
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
+   DMA_FLAG_TC7)
+
+/**
+  * @brief  Return the current DMA Channel half transfer complete flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified half transfer complete flag index.
+  */
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
+   DMA_FLAG_HT7)
+
+/**
+  * @brief  Return the current DMA Channel transfer error flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
+   DMA_FLAG_TE7)
+
+/**
+  * @brief  Return the current DMA Channel Global interrupt flag.
+  * @param  __HANDLE__: DMA handle
+  * @retval The specified transfer error flag index.
+  */
+#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
+   DMA_ISR_GIF7)
+
+/**
+  * @brief  Get the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: Get the specified flag.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
+  *            @arg DMA_ISR_GIFx: Global interrupt flag
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+  * @retval The state of FLAG (SET or RESET).
+  */
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
+ (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
+
+/**
+  * @brief  Clear the DMA Channel pending flags.
+  * @param  __HANDLE__: DMA handle
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx:  Transfer complete flag
+  *            @arg DMA_FLAG_HTIFx:  Half transfer complete flag
+  *            @arg DMA_FLAG_TEIFx:  Transfer error flag
+  *            @arg DMA_ISR_GIFx: Global interrupt flag
+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Channel flag.
+  * @retval None
+  */
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
+ (DMA2->IFCR |= (__FLAG__)) : (DMA1->IFCR |= (__FLAG__)))
+
+/**
+  * @brief  Enable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified DMA Channel interrupts.
+  * @param  __HANDLE__: DMA handle
+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval None
+  */
+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified DMA Channel interrupt is enabled or not.
+  * @param  __HANDLE__: DMA handle
+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  * @retval The state of DMA_IT (SET or RESET).
+  */
+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DMA_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Macros DMA Private Macros
+  * @{
+  */
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
+
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
+                                            ((STATE) == DMA_PINC_DISABLE))
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
+                                        ((STATE) == DMA_MINC_DISABLE))
+
+#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \
+                                     ((REQUEST) == DMA_REQUEST_1) || \
+                                     ((REQUEST) == DMA_REQUEST_2) || \
+                                     ((REQUEST) == DMA_REQUEST_3) || \
+                                     ((REQUEST) == DMA_REQUEST_4) || \
+                                     ((REQUEST) == DMA_REQUEST_5) || \
+                                     ((REQUEST) == DMA_REQUEST_6) || \
+                                     ((REQUEST) == DMA_REQUEST_7))
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
+                                           ((SIZE) == DMA_PDATAALIGN_WORD))
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
+                           ((MODE) == DMA_CIRCULAR))
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_DMA_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash.h

@@ -0,0 +1,829 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash.h
+  * @author  MCD Application Team
+  * @version V1.3.0 
+  * @date    29-January-2016
+  * @brief   Header file of FLASH HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_FLASH_H
+#define __STM32L4xx_HAL_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Types FLASH Exported Types
+  * @{
+  */
+
+/**
+  * @brief  FLASH Erase structure definition
+  */
+typedef struct
+{ 
+  uint32_t TypeErase;   /*!< Mass erase or page erase.
+                             This parameter can be a value of @ref FLASH_Type_Erase */
+  uint32_t Banks;       /*!< Select bank to erase.
+                             This parameter must be a value of @ref FLASH_Banks 
+                             (FLASH_BANK_BOTH should be used only for mass erase) */        
+  uint32_t Page;        /*!< Initial Flash page to erase when page erase is disabled
+                             This parameter must be a value between 0 and (max number of pages in the bank - 1) 
+                             (eg : 255 for 1MB dual bank) */
+  uint32_t NbPages;     /*!< Number of pages to be erased.
+                             This parameter must be a value between 1 and (max number of pages in the bank - value of initial page)*/           
+} FLASH_EraseInitTypeDef;
+
+/**
+  * @brief  FLASH Option Bytes Program structure definition
+  */
+typedef struct
+{
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a combination of the values of @ref FLASH_OB_Type */
+  uint32_t WRPArea;        /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP).
+                                Only one WRP area could be programmed at the same time.
+                                This parameter can be value of @ref FLASH_OB_WRP_Area */
+  uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP).
+                                This parameter must be a value between 0 and (max number of pages in the bank - 1)
+                                (eg : 25 for 1MB dual bank) */
+  uint32_t WRPEndOffset;   /*!< Write protection end offset (used for OPTIONBYTE_WRP).
+                                This parameter must be a value between WRPStartOffset and (max number of pages in the bank - 1) */
+  uint32_t RDPLevel;       /*!< Set the read protection level.. (used for OPTIONBYTE_RDP).
+                                This parameter can be a value of @ref FLASH_OB_Read_Protection */
+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASH_OB_USER_Type */
+  uint32_t USERConfig;     /*!< Value of the user option byte (used for OPTIONBYTE_USER).
+                                This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL,
+                                @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY,
+                                @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, 
+                                @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, 
+                                @ref FLASH_OB_USER_WWDG_SW, @ref FLASH_OB_USER_BFB2, 
+                                @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_nBOOT1, 
+                                @ref FLASH_OB_USER_SRAM2_PE and @ref FLASH_OB_USER_SRAM2_RST */
+  uint32_t PCROPConfig;    /*!< Configuration of the PCROP (used for OPTIONBYTE_PCROP).
+                                This parameter must be a combination of @ref FLASH_Banks (except FLASH_BANK_BOTH) 
+                                and @ref FLASH_OB_PCROP_RDP */
+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between begin and end of bank 
+                                => Be careful of the bank swapping for the address */
+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
+                                This parameter must be a value between PCROP Start address and end of bank */
+} FLASH_OBProgramInitTypeDef;
+
+/**
+  * @brief  FLASH Procedure structure definition
+  */
+typedef enum 
+{
+  FLASH_PROC_NONE = 0,
+  FLASH_PROC_PAGE_ERASE,
+  FLASH_PROC_MASS_ERASE,
+  FLASH_PROC_PROGRAM,
+  FLASH_PROC_PROGRAM_LAST
+} FLASH_ProcedureTypeDef;
+
+/** 
+  * @brief  FLASH handle Structure definition  
+  */
+typedef struct
+{
+  HAL_LockTypeDef             Lock;              /* FLASH locking object */
+  __IO uint32_t               ErrorCode;         /* FLASH error code */
+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;  /* Internal variable to indicate which procedure is ongoing or not in IT context */
+  __IO uint32_t               Address;           /* Internal variable to save address selected for program in IT context */
+  __IO uint32_t               Bank;              /* Internal variable to save current bank selected during erase in IT context */
+  __IO uint32_t               Page;              /* Internal variable to define the current page which is erasing in IT context */
+  __IO uint32_t               NbPagesToErase;    /* Internal variable to save the remaining pages to erase in IT context */
+}FLASH_ProcessTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
+  * @{
+  */
+
+/** @defgroup FLASH_Error FLASH Error
+  * @{
+  */ 
+#define HAL_FLASH_ERROR_NONE      ((uint32_t)0x00000000)
+#define HAL_FLASH_ERROR_OP        ((uint32_t)0x00000001)
+#define HAL_FLASH_ERROR_PROG      ((uint32_t)0x00000002)
+#define HAL_FLASH_ERROR_WRP       ((uint32_t)0x00000004)
+#define HAL_FLASH_ERROR_PGA       ((uint32_t)0x00000008)
+#define HAL_FLASH_ERROR_SIZ       ((uint32_t)0x00000010)
+#define HAL_FLASH_ERROR_PGS       ((uint32_t)0x00000020)
+#define HAL_FLASH_ERROR_MIS       ((uint32_t)0x00000040)
+#define HAL_FLASH_ERROR_FAST      ((uint32_t)0x00000080)
+#define HAL_FLASH_ERROR_RD        ((uint32_t)0x00000100)
+#define HAL_FLASH_ERROR_OPTV      ((uint32_t)0x00000200)
+#define HAL_FLASH_ERROR_ECCD      ((uint32_t)0x00000400)
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Type_Erase FLASH Erase Type
+  * @{
+  */ 
+#define FLASH_TYPEERASE_PAGES     ((uint32_t)0x00)  /*!<Pages erase only*/
+#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01)  /*!<Flash mass erase activation*/
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Banks FLASH Banks
+  * @{
+  */
+#define FLASH_BANK_1              ((uint32_t)0x01)                          /*!< Bank 1   */
+#define FLASH_BANK_2              ((uint32_t)0x02)                          /*!< Bank 2   */
+#define FLASH_BANK_BOTH           ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2  */
+/**
+  * @}
+  */
+
+
+/** @defgroup FLASH_Type_Program FLASH Program Type
+  * @{
+  */
+#define FLASH_TYPEPROGRAM_DOUBLEWORD    ((uint32_t)0x00)  /*!<Program a double-word (64-bit) at a specified address.*/
+#define FLASH_TYPEPROGRAM_FAST          ((uint32_t)0x01)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
+                                                                 And another 32 row double-word (64-bit) will be programmed */
+#define FLASH_TYPEPROGRAM_FAST_AND_LAST ((uint32_t)0x02)  /*!<Fast program a 32 row double-word (64-bit) at a specified address.
+                                                                 And this is the last 32 row double-word (64-bit) programmed */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Type FLASH Option Bytes Type
+  * @{
+  */
+#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!< WRP option byte configuration */
+#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!< RDP option byte configuration */
+#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!< USER option byte configuration */
+#define OPTIONBYTE_PCROP          ((uint32_t)0x08)  /*!< PCROP option byte configuration */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_WRP_Area FLASH WRP Area
+  * @{
+  */ 
+#define OB_WRPAREA_BANK1_AREAA    ((uint32_t)0x00)  /*!< Flash Bank 1 Area A */
+#define OB_WRPAREA_BANK1_AREAB    ((uint32_t)0x01)  /*!< Flash Bank 1 Area B */
+#define OB_WRPAREA_BANK2_AREAA    ((uint32_t)0x02)  /*!< Flash Bank 2 Area A */
+#define OB_WRPAREA_BANK2_AREAB    ((uint32_t)0x04)  /*!< Flash Bank 2 Area B */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_OB_Read_Protection FLASH Option Bytes Read Protection
+  * @{
+  */
+#define OB_RDP_LEVEL_0            ((uint32_t)0xAA)
+#define OB_RDP_LEVEL_1            ((uint32_t)0xBB)
+#define OB_RDP_LEVEL_2            ((uint32_t)0xCC) /*!< Warning: When enabling read protection level 2 
+                                                        it's no more possible to go back to level 1 or 0 */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_Type FLASH Option Bytes User Type
+  * @{
+  */
+#define OB_USER_BOR_LEV           ((uint32_t)0x0001)                   /*!< BOR reset Level */
+#define OB_USER_nRST_STOP         ((uint32_t)0x0002)                   /*!< Reset generated when entering the stop mode */
+#define OB_USER_nRST_STDBY        ((uint32_t)0x0004)                   /*!< Reset generated when entering the standby mode */
+#define OB_USER_IWDG_SW           ((uint32_t)0x0008)                   /*!< Independent watchdog selection */
+#define OB_USER_IWDG_STOP         ((uint32_t)0x0010)                   /*!< Independent watchdog counter freeze in stop mode */
+#define OB_USER_IWDG_STDBY        ((uint32_t)0x0020)                   /*!< Independent watchdog counter freeze in standby mode */
+#define OB_USER_WWDG_SW           ((uint32_t)0x0040)                   /*!< Window watchdog selection */
+#define OB_USER_BFB2              ((uint32_t)0x0080)                   /*!< Dual-bank boot */
+#define OB_USER_DUALBANK          ((uint32_t)0x0100)                   /*!< Dual-Bank on 512KB or 256KB Flash memory devices */
+#define OB_USER_nBOOT1            ((uint32_t)0x0200)                   /*!< Boot configuration */
+#define OB_USER_SRAM2_PE          ((uint32_t)0x0400)                   /*!< SRAM2 parity check enable */
+#define OB_USER_SRAM2_RST         ((uint32_t)0x0800)                   /*!< SRAM2 Erase when system reset */
+#define OB_USER_nRST_SHDW         ((uint32_t)0x1000)                   /*!< Reset generated when entering the shutdown mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_BOR_LEVEL FLASH Option Bytes User BOR Level
+  * @{
+  */
+#define OB_BOR_LEVEL_0            ((uint32_t)FLASH_OPTR_BOR_LEV_0)     /*!< Reset level threshold is around 1.7V */
+#define OB_BOR_LEVEL_1            ((uint32_t)FLASH_OPTR_BOR_LEV_1)     /*!< Reset level threshold is around 2.0V */
+#define OB_BOR_LEVEL_2            ((uint32_t)FLASH_OPTR_BOR_LEV_2)     /*!< Reset level threshold is around 2.2V */
+#define OB_BOR_LEVEL_3            ((uint32_t)FLASH_OPTR_BOR_LEV_3)     /*!< Reset level threshold is around 2.5V */
+#define OB_BOR_LEVEL_4            ((uint32_t)FLASH_OPTR_BOR_LEV_4)     /*!< Reset level threshold is around 2.8V */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop 
+  * @{
+  */
+#define OB_STOP_RST               ((uint32_t)0x0000)                   /*!< Reset generated when entering the stop mode */
+#define OB_STOP_NORST             ((uint32_t)FLASH_OPTR_nRST_STOP)     /*!< No reset generated when entering the stop mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
+  * @{
+  */
+#define OB_STANDBY_RST            ((uint32_t)0x0000)                   /*!< Reset generated when entering the standby mode */
+#define OB_STANDBY_NORST          ((uint32_t)FLASH_OPTR_nRST_STDBY)    /*!< No reset generated when entering the standby mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
+  * @{
+  */
+#define OB_SHUTDOWN_RST           ((uint32_t)0x0000)                   /*!< Reset generated when entering the shutdown mode */
+#define OB_SHUTDOWN_NORST         ((uint32_t)FLASH_OPTR_nRST_SHDW)     /*!< No reset generated when entering the shutdown mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
+  * @{
+  */
+#define OB_IWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware independent watchdog */
+#define OB_IWDG_SW                ((uint32_t)FLASH_OPTR_IWDG_SW)       /*!< Software independent watchdog */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
+  * @{
+  */
+#define OB_IWDG_STOP_FREEZE       ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Stop mode */
+#define OB_IWDG_STOP_RUN          ((uint32_t)FLASH_OPTR_IWDG_STOP)     /*!< Independent watchdog counter is running in Stop mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
+  * @{
+  */
+#define OB_IWDG_STDBY_FREEZE      ((uint32_t)0x00000)                  /*!< Independent watchdog counter is frozen in Standby mode */
+#define OB_IWDG_STDBY_RUN         ((uint32_t)FLASH_OPTR_IWDG_STDBY)    /*!< Independent watchdog counter is running in Standby mode */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
+  * @{
+  */
+#define OB_WWDG_HW                ((uint32_t)0x00000)                  /*!< Hardware window watchdog */
+#define OB_WWDG_SW                ((uint32_t)FLASH_OPTR_WWDG_SW)       /*!< Software window watchdog */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_BFB2 FLASH Option Bytes User BFB2 Mode
+  * @{
+  */
+#define OB_BFB2_DISABLE           ((uint32_t)0x000000)                 /*!< Dual-bank boot disable */
+#define OB_BFB2_ENABLE            ((uint32_t)FLASH_OPTR_BFB2)          /*!< Dual-bank boot enable */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_DUALBANK FLASH Option Bytes User Dual-bank Type
+  * @{
+  */
+#define OB_DUALBANK_SINGLE        ((uint32_t)0x000000)                 /*!< 256 KB/512 KB Single-bank Flash */
+#define OB_DUALBANK_DUAL          ((uint32_t)FLASH_OPTR_DUALBANK)      /*!< 256 KB/512 KB Dual-bank Flash */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
+  * @{
+  */
+#define OB_BOOT1_SRAM             ((uint32_t)0x000000)                 /*!< Embedded SRAM1 is selected as boot space (if BOOT0=1) */
+#define OB_BOOT1_SYSTEM           ((uint32_t)FLASH_OPTR_nBOOT1)        /*!< System memory is selected as boot space (if BOOT0=1) */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_SRAM2_PE FLASH Option Bytes User SRAM2 Parity Check Type
+  * @{
+  */
+#define OB_SRAM2_PARITY_ENABLE    ((uint32_t)0x0000000)                /*!< SRAM2 parity check enable */
+#define OB_SRAM2_PARITY_DISABLE   ((uint32_t)FLASH_OPTR_SRAM2_PE)      /*!< SRAM2 parity check disable */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_USER_SRAM2_RST FLASH Option Bytes User SRAM2 Erase On Reset Type
+  * @{
+  */
+#define OB_SRAM2_RST_ERASE        ((uint32_t)0x0000000)                /*!< SRAM2 erased when a system reset occurs */
+#define OB_SRAM2_RST_NOT_ERASE    ((uint32_t)FLASH_OPTR_SRAM2_RST)     /*!< SRAM2 is not erased when a system reset occurs */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
+  * @{
+  */
+#define OB_PCROP_RDP_NOT_ERASE    ((uint32_t)0x00000000)               /*!< PCROP area is not erased when the RDP level 
+                                                                            is decreased from Level 1 to Level 0 */
+#define OB_PCROP_RDP_ERASE        ((uint32_t)FLASH_PCROP1ER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is 
+                                                                            decreased from Level 1 to Level 0 (full mass erase) */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Latency FLASH Latency
+  * @{
+  */ 
+#define FLASH_LATENCY_0           FLASH_ACR_LATENCY_0WS                /*!< FLASH Zero wait state */
+#define FLASH_LATENCY_1           FLASH_ACR_LATENCY_1WS                /*!< FLASH One wait state */
+#define FLASH_LATENCY_2           FLASH_ACR_LATENCY_2WS                /*!< FLASH Two wait states */
+#define FLASH_LATENCY_3           FLASH_ACR_LATENCY_3WS                /*!< FLASH Three wait states */
+#define FLASH_LATENCY_4           FLASH_ACR_LATENCY_4WS                /*!< FLASH Four wait states */
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys FLASH Keys
+  * @{
+  */ 
+#define FLASH_KEY1                ((uint32_t)0x45670123U)               /*!< Flash key1 */
+#define FLASH_KEY2                ((uint32_t)0xCDEF89ABU)               /*!< Flash key2: used with FLASH_KEY1 
+                                                                            to unlock the FLASH registers access */
+
+#define FLASH_PDKEY1              ((uint32_t)0x04152637U)               /*!< Flash power down key1 */
+#define FLASH_PDKEY2              ((uint32_t)0xFAFBFCFDU)               /*!< Flash power down key2: used with FLASH_PDKEY1 
+                                                                            to unlock the RUN_PD bit in FLASH_ACR */
+
+#define FLASH_OPTKEY1             ((uint32_t)0x08192A3BU)               /*!< Flash option byte key1 */
+#define FLASH_OPTKEY2             ((uint32_t)0x4C5D6E7FU)               /*!< Flash option byte key2: used with FLASH_OPTKEY1 
+                                                                            to allow option bytes operations */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Flags FLASH Flags Definition
+  * @{
+  */ 
+#define FLASH_FLAG_EOP            FLASH_SR_EOP                         /*!< FLASH End of operation flag */
+#define FLASH_FLAG_OPERR          FLASH_SR_OPERR                       /*!< FLASH Operation error flag */
+#define FLASH_FLAG_PROGERR        FLASH_SR_PROGERR                     /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR         FLASH_SR_WRPERR                      /*!< FLASH Write protection error flag */
+#define FLASH_FLAG_PGAERR         FLASH_SR_PGAERR                      /*!< FLASH Programming alignment error flag */
+#define FLASH_FLAG_SIZERR         FLASH_SR_SIZERR                      /*!< FLASH Size error flag  */
+#define FLASH_FLAG_PGSERR         FLASH_SR_PGSERR                      /*!< FLASH Programming sequence error flag */
+#define FLASH_FLAG_MISERR         FLASH_SR_MISERR                      /*!< FLASH Fast programming data miss error flag */
+#define FLASH_FLAG_FASTERR        FLASH_SR_FASTERR                     /*!< FLASH Fast programming error flag */
+#define FLASH_FLAG_RDERR          FLASH_SR_RDERR                       /*!< FLASH PCROP read error flag */
+#define FLASH_FLAG_OPTVERR        FLASH_SR_OPTVERR                     /*!< FLASH Option validity error flag  */
+#define FLASH_FLAG_BSY            FLASH_SR_BSY                         /*!< FLASH Busy flag */
+#define FLASH_FLAG_ECCC           FLASH_ECCR_ECCC                      /*!< FLASH ECC correction */
+#define FLASH_FLAG_ECCD           FLASH_ECCR_ECCD                      /*!< FLASH ECC detection */
+
+#define FLASH_FLAG_ALL_ERRORS     (FLASH_FLAG_OPERR   | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
+                                   FLASH_FLAG_PGAERR  | FLASH_FLAG_SIZERR  | FLASH_FLAG_PGSERR | \
+                                   FLASH_FLAG_MISERR  | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR  | \
+                                   FLASH_FLAG_OPTVERR | FLASH_FLAG_ECCD)
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition
+  * @brief FLASH Interrupt definition
+  * @{
+  */ 
+#define FLASH_IT_EOP              FLASH_CR_EOPIE                       /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_OPERR            FLASH_CR_ERRIE                       /*!< Error Interrupt source */
+#define FLASH_IT_RDERR            FLASH_CR_RDERRIE                     /*!< PCROP Read Error Interrupt source*/
+#define FLASH_IT_ECCC             (FLASH_ECCR_ECCIE >> 24)             /*!< ECC Correction Interrupt source */
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
+ *  @brief macros to control FLASH features 
+ *  @{
+ */
+
+/**
+  * @brief  Set the FLASH Latency.
+  * @param  __LATENCY__: FLASH Latency                   
+  *         This parameter can be one of the following values :
+  *     @arg FLASH_LATENCY_0: FLASH Zero wait state
+  *     @arg FLASH_LATENCY_1: FLASH One wait state    
+  *     @arg FLASH_LATENCY_2: FLASH Two wait states
+  *     @arg FLASH_LATENCY_3: FLASH Three wait states
+  *     @arg FLASH_LATENCY_4: FLASH Four wait states
+  * @retval None
+  */ 
+#define __HAL_FLASH_SET_LATENCY(__LATENCY__)    (MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__)))
+
+/**
+  * @brief  Get the FLASH Latency.
+  * @retval FLASH Latency                   
+  *         This parameter can be one of the following values :
+  *     @arg FLASH_LATENCY_0: FLASH Zero wait state
+  *     @arg FLASH_LATENCY_1: FLASH One wait state    
+  *     @arg FLASH_LATENCY_2: FLASH Two wait states
+  *     @arg FLASH_LATENCY_3: FLASH Three wait states
+  *     @arg FLASH_LATENCY_4: FLASH Four wait states
+  */ 
+#define __HAL_FLASH_GET_LATENCY()               READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)
+
+/**
+  * @brief  Enable the FLASH prefetch buffer.
+  * @retval None
+  */ 
+#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Disable the FLASH prefetch buffer.
+  * @retval None
+  */
+#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
+
+/**
+  * @brief  Enable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_ENABLE()  SET_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+  * @brief  Disable the FLASH instruction cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_INSTRUCTION_CACHE_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN)
+
+/**
+  * @brief  Enable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_ENABLE()         SET_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+  * @brief  Disable the FLASH data cache.
+  * @retval none
+  */ 
+#define __HAL_FLASH_DATA_CACHE_DISABLE()        CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN)
+
+/**
+  * @brief  Reset the FLASH instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_INSTRUCTION_CACHE_RESET()   do { SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);   \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST); \
+                                                   } while (0)
+
+/**
+  * @brief  Reset the FLASH data Cache.
+  * @note   This function must be used only when the data Cache is disabled.  
+  * @retval None
+  */
+#define __HAL_FLASH_DATA_CACHE_RESET()          do { SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);   \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST); \
+                                                   } while (0)
+
+/**
+  * @brief  Enable the FLASH power down during Low-power run mode.
+  * @note   Writing this bit  to 0 this bit, automatically the keys are
+  *         loss and a new unlock sequence is necessary to re-write it to 1.
+  */
+#define __HAL_FLASH_POWER_DOWN_ENABLE()         do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+                                                     SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD);   \
+                                                   } while (0)
+
+/**
+  * @brief  Disable the FLASH power down during Low-power run mode.
+  * @note   Writing this bit  to 0 this bit, automatically the keys are
+  *         loss and a new unlock sequence is necessary to re-write it to 1.
+  */
+#define __HAL_FLASH_POWER_DOWN_DISABLE()        do { WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY1); \
+                                                     WRITE_REG(FLASH->PDKEYR, FLASH_PDKEY2); \
+                                                     CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
+                                                   } while (0)
+
+/**
+  * @brief  Enable the FLASH power down during Low-Power sleep mode
+  * @retval none
+  */ 
+#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()    SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+  * @brief  Disable the FLASH power down during Low-Power sleep mode
+  * @retval none
+  */ 
+#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()   CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
+
+/**
+  * @}
+  */  
+
+/** @defgroup FLASH_Interrupt FLASH Interrupts Macros
+ *  @brief macros to handle FLASH interrupts
+ * @{
+ */ 
+
+/**
+  * @brief  Enable the specified FLASH interrupt.
+  * @param  __INTERRUPT__: FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_OPERR: Error Interrupt    
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
+  * @retval none
+  */  
+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    do { if((__INTERRUPT__) & FLASH_IT_ECCC) { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { SET_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+                                                   } while(0)
+
+/**
+  * @brief  Disable the specified FLASH interrupt.
+  * @param  __INTERRUPT__: FLASH interrupt 
+  *         This parameter can be any combination of the following values:
+  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
+  *     @arg FLASH_IT_OPERR: Error Interrupt    
+  *     @arg FLASH_IT_RDERR: PCROP Read Error Interrupt
+  *     @arg FLASH_IT_ECCC: ECC Correction Interrupt
+  * @retval none
+  */  
+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)   do { if((__INTERRUPT__) & FLASH_IT_ECCC) { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\
+                                                     if((__INTERRUPT__) & (~FLASH_IT_ECCC)) { CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
+                                                   } while(0)
+
+/**
+  * @brief  Check whether the specified FLASH flag is set or not.
+  * @param  __FLAG__: specifies the FLASH flag to check.
+  *   This parameter can be one of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag 
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+#define __HAL_FLASH_GET_FLAG(__FLAG__)          (((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) ? \
+                                                 (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__))  : \
+                                                 (READ_BIT(FLASH->SR,   (__FLAG__)) == (__FLAG__)))
+
+/**
+  * @brief  Clear the FLASH's pending flags.
+  * @param  __FLAG__: specifies the FLASH flags to clear.
+  *   This parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP: FLASH End of Operation flag
+  *     @arg FLASH_FLAG_OPERR: FLASH Operation error flag
+  *     @arg FLASH_FLAG_PROGERR: FLASH Programming error flag
+  *     @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag 
+  *     @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag
+  *     @arg FLASH_FLAG_SIZERR: FLASH Size error flag
+  *     @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag
+  *     @arg FLASH_FLAG_MISERR: FLASH Fast programming data miss error flag
+  *     @arg FLASH_FLAG_FASTERR: FLASH Fast programming error flag
+  *     @arg FLASH_FLAG_RDERR: FLASH PCROP read  error flag
+  *     @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag
+  *     @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected
+  *     @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected
+  *     @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags
+  * @retval None
+  */
+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)        do { if((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
+                                                     if((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\
+                                                   } while(0)
+/**
+  * @}
+  */  
+
+/* Include FLASH HAL Extended module */
+#include "stm32l4xx_hal_flash_ex.h"
+#include "stm32l4xx_hal_flash_ramfunc.h"
+
+/* Exported functions --------------------------------------------------------*/ 
+/** @addtogroup FLASH_Exported_Functions
+  * @{
+  */
+
+/* Program operation functions  ***********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef  HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+HAL_StatusTypeDef  HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
+/* FLASH IRQ handler method */
+void               HAL_FLASH_IRQHandler(void);
+/* Callbacks in non blocking modes */ 
+void               HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
+void               HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup FLASH_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef  HAL_FLASH_Unlock(void);
+HAL_StatusTypeDef  HAL_FLASH_Lock(void);
+/* Option bytes control */
+HAL_StatusTypeDef  HAL_FLASH_OB_Unlock(void);
+HAL_StatusTypeDef  HAL_FLASH_OB_Lock(void);
+HAL_StatusTypeDef  HAL_FLASH_OB_Launch(void);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup FLASH_Exported_Functions_Group3
+  * @{
+  */
+uint32_t HAL_FLASH_GetError(void);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants --------------------------------------------------------*/
+/** @defgroup FLASH_Private_Constants FLASH Private Constants
+  * @{
+  */
+#define FLASH_SIZE_DATA_REGISTER           ((uint32_t)0x1FFF75E0)
+    
+#define FLASH_SIZE                         ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFF)) ? (0x400 << 10) : \
+                                            (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) << 10))
+
+#define FLASH_BANK_SIZE                    (FLASH_SIZE >> 1)
+
+#define FLASH_PAGE_SIZE                    ((uint32_t)0x800)
+
+#define FLASH_TIMEOUT_VALUE                ((uint32_t)50000)/* 50 s */
+/**
+  * @}
+  */
+ 
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup FLASH_Private_Macros FLASH Private Macros
+ *  @{
+ */
+
+#define IS_FLASH_TYPEERASE(VALUE)          (((VALUE) == FLASH_TYPEERASE_PAGES) || \
+                                            ((VALUE) == FLASH_TYPEERASE_MASSERASE))  
+
+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2)  || \
+                                            ((BANK) == FLASH_BANK_BOTH))
+
+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
+                                            ((BANK) == FLASH_BANK_2))
+
+#define IS_FLASH_TYPEPROGRAM(VALUE)        (((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST) || \
+                                            ((VALUE) == FLASH_TYPEPROGRAM_FAST_AND_LAST))  
+
+#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE)        && ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0xFFFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0x7FFFF) : ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? \
+                                            ((ADDRESS) <= FLASH_BASE+0x3FFFF) : ((ADDRESS) <= FLASH_BASE+0xFFFFF))))) 
+
+#define IS_FLASH_OTP_ADDRESS(ADDRESS)      (((ADDRESS) >= 0x1FFF7000) && ((ADDRESS) <= 0x1FFF73FF))
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) || IS_FLASH_OTP_ADDRESS(ADDRESS))
+
+#define IS_FLASH_PAGE(PAGE)                (((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x400) ? ((PAGE) < 256) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x200) ? ((PAGE) < 128) : \
+                                            ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFF)) == 0x100) ? ((PAGE) < 64) : \
+                                            ((PAGE) < 256)))))
+
+#define IS_OPTIONBYTE(VALUE)               (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)))
+
+#define IS_OB_WRPAREA(VALUE)               (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \
+                                            ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB))
+
+#define IS_OB_RDP_LEVEL(LEVEL)             (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                            ((LEVEL) == OB_RDP_LEVEL_1)/* ||\
+                                            ((LEVEL) == OB_RDP_LEVEL_2)*/)
+
+#define IS_OB_USER_TYPE(TYPE)              (((TYPE) <= (uint32_t)0x1FFF) && ((TYPE) != 0))
+
+#define IS_OB_USER_BOR_LEVEL(LEVEL)        (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \
+                                            ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \
+                                            ((LEVEL) == OB_BOR_LEVEL_4))
+
+#define IS_OB_USER_STOP(VALUE)             (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST))
+
+#define IS_OB_USER_STANDBY(VALUE)          (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST))
+
+#define IS_OB_USER_SHUTDOWN(VALUE)         (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST))
+
+#define IS_OB_USER_IWDG(VALUE)             (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW))
+
+#define IS_OB_USER_IWDG_STOP(VALUE)        (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN))
+
+#define IS_OB_USER_IWDG_STDBY(VALUE)       (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN))
+
+#define IS_OB_USER_WWDG(VALUE)             (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW))
+
+#define IS_OB_USER_BFB2(VALUE)             (((VALUE) == OB_BFB2_DISABLE) || ((VALUE) == OB_BFB2_ENABLE))
+
+#define IS_OB_USER_DUALBANK(VALUE)         (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL))
+
+#define IS_OB_USER_BOOT1(VALUE)            (((VALUE) == OB_BOOT1_SRAM) || ((VALUE) == OB_BOOT1_SYSTEM))
+
+#define IS_OB_USER_SRAM2_PARITY(VALUE)     (((VALUE) == OB_SRAM2_PARITY_ENABLE) || ((VALUE) == OB_SRAM2_PARITY_DISABLE))
+
+#define IS_OB_USER_SRAM2_RST(VALUE)        (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE))
+
+#define IS_OB_PCROP_RDP(VALUE)             (((VALUE) == OB_PCROP_RDP_NOT_ERASE) || ((VALUE) == OB_PCROP_RDP_ERASE))
+
+#define IS_FLASH_LATENCY(LATENCY)          (((LATENCY) == FLASH_LATENCY_0) || \
+                                            ((LATENCY) == FLASH_LATENCY_1) || \
+                                            ((LATENCY) == FLASH_LATENCY_2) || \
+                                            ((LATENCY) == FLASH_LATENCY_3) || \
+                                            ((LATENCY) == FLASH_LATENCY_4))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_FLASH_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ex.h

@@ -0,0 +1,98 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0 
+  * @date    29-January-2016
+  * @brief   Header file of FLASH HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_FLASH_EX_H
+#define __STM32L4xx_HAL_FLASH_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASHEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/ 
+/** @addtogroup FLASHEx_Exported_Functions
+  * @{
+  */
+
+/* Extended Program operation functions  *************************************/
+/** @addtogroup FLASHEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_FLASH_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_flash_ramfunc.h

@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ramfunc.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of FLASH RAMFUNC driver.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_FLASH_RAMFUNC_H
+#define __STM32L4xx_FLASH_RAMFUNC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/* Exported macro ------------------------------------------------------------*/
+/** 
+  * @brief  __RAM_FUNC definition
+  */ 
+#if defined ( __CC_ARM   )
+/* ARM Compiler
+   ------------
+   RAM functions are defined using the toolchain options. 
+   Functions that are executed in RAM should reside in a separate source module.
+   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
+   area of a module to a memory space in physical RAM.
+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
+   dialog. 
+*/
+#define __RAM_FUNC HAL_StatusTypeDef 
+
+#elif defined ( __ICCARM__ )
+/* ICCARM Compiler
+   ---------------
+   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
+*/
+#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+
+#elif defined   (  __GNUC__  )
+/* GNU Compiler
+   ------------
+  RAM functions are defined using a specific toolchain attribute 
+   "__attribute__((section(".RamFunc")))".
+*/
+#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
+
+#endif
+                                      
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup FLASH_RAMFUNC_Exported_Functions_Group1
+  * @{
+  */
+/* Peripheral Control functions  ************************************************/
+__RAM_FUNC  HAL_FLASHEx_EnableRunPowerDown(void);
+__RAM_FUNC  HAL_FLASHEx_DisableRunPowerDown(void);
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_FLASH_RAMFUNC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio.h

@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_gpio.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of GPIO HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_GPIO_H
+#define __STM32L4xx_HAL_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Types GPIO Exported Types
+  * @{
+  */
+/**
+  * @brief   GPIO Init structure definition
+  */
+typedef struct
+{
+  uint32_t Pin;        /*!< Specifies the GPIO pins to be configured.
+                           This parameter can be any value of @ref GPIO_pins */
+
+  uint32_t Mode;       /*!< Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref GPIO_mode */
+
+  uint32_t Pull;       /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
+                           This parameter can be a value of @ref GPIO_pull */
+
+  uint32_t Speed;      /*!< Specifies the speed for the selected pins.
+                           This parameter can be a value of @ref GPIO_speed */
+
+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins 
+                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
+}GPIO_InitTypeDef;
+
+/**
+  * @brief  GPIO Bit SET and Bit RESET enumeration
+  */
+typedef enum
+{
+  GPIO_PIN_RESET = 0,
+  GPIO_PIN_SET
+}GPIO_PinState;
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
+  * @{
+  */
+/** @defgroup GPIO_pins GPIO pins
+  * @{
+  */
+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_mode GPIO mode
+  * @brief GPIO Configuration Mode
+  *        Elements values convention: 0xX0yz00YZ
+  *           - X  : GPIO mode or EXTI Mode
+  *           - y  : External IT or Event trigger detection
+  *           - z  : IO configuration on External IT or Event
+  *           - Y  : Output type (Push Pull or Open Drain)
+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
+  * @{
+  */
+#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
+#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
+#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
+#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
+#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
+#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
+#define  GPIO_MODE_ANALOG_ADC_CONTROL           ((uint32_t)0x0000000B)   /*!< Analog Mode for ADC conversion */
+#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
+#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
+#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
+#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
+#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
+#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_speed GPIO speed
+  * @brief GPIO Output Maximum frequency
+  * @{
+  */
+#define  GPIO_SPEED_FREQ_LOW        ((uint32_t)0x00000000)   /*!< range up to 5 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_MEDIUM     ((uint32_t)0x00000001)   /*!< range  5 MHz to 25 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_HIGH       ((uint32_t)0x00000002)   /*!< range 25 MHz to 50 MHz, please refer to the product datasheet */
+#define  GPIO_SPEED_FREQ_VERY_HIGH  ((uint32_t)0x00000003)   /*!< range 50 MHz to 80 MHz, please refer to the product datasheet */
+/**
+  * @}
+  */
+
+ /** @defgroup GPIO_pull GPIO pull
+   * @brief GPIO Pull-Up or Pull-Down Activation
+   * @{
+   */
+#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
+#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
+#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
+  * @{
+  */
+  
+/**
+  * @brief  Check whether the specified EXTI line flag is set or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  *         This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__)       (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending flags.
+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__)     (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Check whether the specified EXTI line is asserted or not.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval The new state of __EXTI_LINE__ (SET or RESET).
+  */
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)         (EXTI->PR1 & (__EXTI_LINE__))
+
+/**
+  * @brief  Clear the EXTI's line pending bits.
+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)       (EXTI->PR1 = (__EXTI_LINE__))
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  *          This parameter can be GPIO_PIN_x where x can be(0..15)
+  * @retval None
+  */
+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__)  (EXTI->SWIER1 |= (__EXTI_LINE__))
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @addtogroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+#define IS_GPIO_PIN_ACTION(ACTION)  (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
+
+#define IS_GPIO_PIN(__PIN__)        (((__PIN__) & GPIO_PIN_MASK) != (uint32_t)0x00)
+
+#define IS_GPIO_MODE(__MODE__)      (((__MODE__) == GPIO_MODE_INPUT)              ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_PP)          ||\
+                                     ((__MODE__) == GPIO_MODE_OUTPUT_OD)          ||\
+                                     ((__MODE__) == GPIO_MODE_AF_PP)              ||\
+                                     ((__MODE__) == GPIO_MODE_AF_OD)              ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING)          ||\
+                                     ((__MODE__) == GPIO_MODE_IT_FALLING)         ||\
+                                     ((__MODE__) == GPIO_MODE_IT_RISING_FALLING)  ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING)         ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_FALLING)        ||\
+                                     ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG)             ||\
+                                     ((__MODE__) == GPIO_MODE_ANALOG_ADC_CONTROL))
+
+#define IS_GPIO_SPEED(__SPEED__)    (((__SPEED__) == GPIO_SPEED_FREQ_LOW)       ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM)    ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_HIGH)      ||\
+                                     ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
+
+#define IS_GPIO_PULL(__PULL__)      (((__PULL__) == GPIO_NOPULL)   ||\
+                                     ((__PULL__) == GPIO_PULLUP)   || \
+                                     ((__PULL__) == GPIO_PULLDOWN))
+/**
+  * @}
+  */
+
+/* Include GPIO HAL Extended module */
+#include "stm32l4xx_hal_gpio_ex.h"
+
+/* Exported functions --------------------------------------------------------*/ 
+/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions
+ * @{
+ */
+     
+/* Initialization and de-initialization functions *****************************/
+void              HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
+void              HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions 
+ * @{
+ */
+   
+/* IO operation functions *****************************************************/
+GPIO_PinState     HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
+void              HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
+void              HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */  
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_GPIO_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_gpio_ex.h

@@ -0,0 +1,245 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_gpio_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of GPIO HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_GPIO_EX_H
+#define __STM32L4xx_HAL_GPIO_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIOEx GPIOEx
+  * @brief GPIO Extended HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
+  * @{
+  */
+
+/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
+  * @{
+  */
+
+#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+/*--------------STM32L471xx/STM32L475xx/STM32L476xx/STM32L485xx/STM32L486xx----*/
+/**
+  * @brief   AF 0 selection
+  */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
+#if defined(STM32L476xx) || defined(STM32L486xx)
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */
+#endif /* STM32L476xx || STM32L486xx */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+
+/**
+  * @brief   AF 1 selection
+  */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF1_TIM5          ((uint8_t)0x01)  /* TIM5 Alternate Function mapping */
+#define GPIO_AF1_TIM8          ((uint8_t)0x01)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#define GPIO_AF1_IR            ((uint8_t)0x01)  /* IR Alternate Function mapping */
+
+/**
+  * @brief   AF 2 selection
+  */
+#define GPIO_AF2_TIM1          ((uint8_t)0x02)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF2_TIM2          ((uint8_t)0x02)  /* TIM2 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/**
+  * @brief   AF 3 selection
+  */
+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP2    ((uint8_t)0x03)  /* TIM1/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF3_TIM1_COMP1    ((uint8_t)0x03)  /* TIM1/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 4 selection
+  */
+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */
+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */
+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */
+
+/**
+  * @brief   AF 5 selection
+  */
+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */
+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */
+
+/**
+  * @brief   AF 6 selection
+  */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM         ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+
+/**
+  * @brief   AF 7 selection
+  */
+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping     */
+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping     */
+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping     */
+
+/**
+  * @brief   AF 8 selection
+  */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping   */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping   */
+#define GPIO_AF8_LPUART1       ((uint8_t)0x08)  /* LPUART1 Alternate Function mapping */
+
+
+/**
+  * @brief   AF 9 selection
+  */
+#define GPIO_AF9_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping  */
+#define GPIO_AF9_TSC           ((uint8_t)0x09)  /* TSC Alternate Function mapping   */
+
+/**
+  * @brief   AF 10 selection
+  */
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+#define GPIO_AF10_OTG_FS       ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+#define GPIO_AF10_QUADSPI      ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
+
+#if defined(STM32L476xx) || defined(STM32L486xx)
+/**
+  * @brief   AF 11 selection
+  */
+#define GPIO_AF11_LCD           ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
+#endif /* STM32L476xx || STM32L486xx */
+
+/**
+  * @brief   AF 12 selection
+  */
+#define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SWPMI1        ((uint8_t)0xC)  /* SWPMI1 Alternate Function mapping  */
+#define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping  */
+
+/**
+  * @brief   AF 13 selection
+  */
+#define GPIO_AF13_SAI1          ((uint8_t)0x0D)   /* SAI1 Alternate Function mapping */
+#define GPIO_AF13_SAI2          ((uint8_t)0x0D)   /* SAI2 Alternate Function mapping */
+#define GPIO_AF13_TIM8_COMP2    ((uint8_t)0x0D)   /* TIM8/COMP2 Break in Alternate Function mapping  */
+#define GPIO_AF13_TIM8_COMP1    ((uint8_t)0x0D)   /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 14 selection
+  */
+#define GPIO_AF14_TIM2          ((uint8_t)0x0E)   /* TIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM15         ((uint8_t)0x0E)   /* TIM15 Alternate Function mapping */
+#define GPIO_AF14_TIM16         ((uint8_t)0x0E)   /* TIM16 Alternate Function mapping */
+#define GPIO_AF14_TIM17         ((uint8_t)0x0E)   /* TIM17 Alternate Function mapping */
+#define GPIO_AF14_LPTIM2        ((uint8_t)0x0E)   /* LPTIM2 Alternate Function mapping */
+#define GPIO_AF14_TIM8_COMP1    ((uint8_t)0x0E)   /* TIM8/COMP1 Break in Alternate Function mapping  */
+
+/**
+  * @brief   AF 15 selection
+  */
+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
+
+#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
+  * @{
+  */
+
+/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
+* @{
+  */
+#define GPIO_GET_INDEX(__GPIOx__)    (((__GPIOx__) == (GPIOA))? 0U :\
+                                      ((__GPIOx__) == (GPIOB))? 1U :\
+                                      ((__GPIOx__) == (GPIOC))? 2U :\
+                                      ((__GPIOx__) == (GPIOD))? 3U :\
+                                      ((__GPIOx__) == (GPIOE))? 4U :\
+                                      ((__GPIOx__) == (GPIOF))? 5U :\
+                                      ((__GPIOx__) == (GPIOG))? 6U : 7U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_GPIO_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c.h

@@ -0,0 +1,665 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of I2C HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_I2C_H
+#define __STM32L4xx_HAL_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"  
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup I2C_Exported_Types I2C Exported Types
+  * @{
+  */
+
+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
+  * @brief  I2C Configuration Structure definition  
+  * @{
+  */
+typedef struct
+{
+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.
+                                  This parameter calculated by referring to I2C initialization 
+                                         section in Reference manual */
+
+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.
+                                  This parameter can be a 7-bit or 10-bit address. */
+
+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_addressing_mode */
+
+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.
+                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
+
+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected
+                                  This parameter can be a 7-bit address. */
+
+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
+                                  This parameter can be a value of @ref I2C_own_address2_masks */
+
+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.
+                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
+
+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.
+                                  This parameter can be a value of @ref I2C_nostretch_mode */
+
+}I2C_InitTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup HAL_state_structure_definition HAL state structure definition
+  * @brief  HAL State structure definition
+  * @{
+  */ 
+
+typedef enum
+{
+  HAL_I2C_STATE_RESET             = 0x00,   /*!< Peripheral is not yet Initialized         */
+  HAL_I2C_STATE_READY             = 0x20,   /*!< Peripheral Initialized and ready for use  */
+  HAL_I2C_STATE_BUSY              = 0x24,   /*!< An internal process is ongoing            */
+  HAL_I2C_STATE_BUSY_TX           = 0x21,   /*!< Data Transmission process is ongoing      */ 
+  HAL_I2C_STATE_BUSY_RX           = 0x22,   /*!< Data Reception process is ongoing         */
+  HAL_I2C_STATE_LISTEN            = 0x28,   /*!< Address Listen Mode is ongoing            */
+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29,   /*!< Address Listen Mode and Data Transmission
+                                                 process is ongoing                        */
+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2A,   /*!< Address Listen Mode and Data Reception
+                                                 process is ongoing                        */
+  HAL_I2C_STATE_TIMEOUT           = 0xA0,   /*!< Timeout state                             */
+  HAL_I2C_STATE_ERROR             = 0xE0    /*!< Error                                     */ 
+
+}HAL_I2C_StateTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_mode_structure_definition HAL mode structure definition
+  * @brief  HAL Mode structure definition
+  * @{
+  */
+typedef enum
+{
+  HAL_I2C_MODE_NONE               = 0x00,   /*!< No I2C communication on going             */
+  HAL_I2C_MODE_MASTER             = 0x10,   /*!< I2C communication is in Master Mode       */
+  HAL_I2C_MODE_SLAVE              = 0x20,   /*!< I2C communication is in Slave Mode        */
+  HAL_I2C_MODE_MEM                = 0x40    /*!< I2C communication is in Memory Mode       */
+
+}HAL_I2C_ModeTypeDef;
+
+/** 
+  * @}
+  */
+
+/** @defgroup I2C_Error_Code_definition I2C Error Code definition
+  * @brief  I2C Error Code definition  
+  * @{
+  */
+#define HAL_I2C_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error              */
+#define HAL_I2C_ERROR_BERR      ((uint32_t)0x00000001)    /*!< BERR error            */
+#define HAL_I2C_ERROR_ARLO      ((uint32_t)0x00000002)    /*!< ARLO error            */
+#define HAL_I2C_ERROR_AF        ((uint32_t)0x00000004)    /*!< ACKF error            */
+#define HAL_I2C_ERROR_OVR       ((uint32_t)0x00000008)    /*!< OVR error             */
+#define HAL_I2C_ERROR_DMA       ((uint32_t)0x00000010)    /*!< DMA transfer error    */
+#define HAL_I2C_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error         */
+#define HAL_I2C_ERROR_SIZE      ((uint32_t)0x00000040)    /*!< Size Management error */
+/** 
+  * @}
+  */
+
+/** @defgroup I2C_XferOptions_definition  I2C XferOptions definition
+  * @{
+  */
+#define I2C_NO_OPTION_FRAME             ((uint32_t)0xFFFF0000)
+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)
+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
+  * @brief  I2C handle Structure definition  
+  * @{
+  */
+typedef struct
+{
+  I2C_TypeDef                *Instance;        /*!< I2C registers base address       */
+
+  I2C_InitTypeDef            Init;             /*!< I2C communication parameters     */
+
+  uint8_t                    *pBuffPtr;        /*!< Pointer to I2C transfer buffer   */
+
+  uint16_t                   XferSize;         /*!< I2C transfer size                */
+
+  __IO uint16_t              XferCount;        /*!< I2C transfer counter             */
+
+  __IO uint32_t              XferOptions;      /*!< I2C transfer options             */
+
+  __IO uint32_t              PreviousState;    /*!< I2C communication Previous state */
+
+  DMA_HandleTypeDef          *hdmatx;          /*!< I2C Tx DMA handle parameters     */
+
+  DMA_HandleTypeDef          *hdmarx;          /*!< I2C Rx DMA handle parameters     */
+
+  HAL_LockTypeDef            Lock;             /*!< I2C locking object               */
+
+  __IO HAL_I2C_StateTypeDef  State;            /*!< I2C communication state          */
+
+  __IO HAL_I2C_ModeTypeDef   Mode;             /*!< I2C communication mode           */
+
+  __IO uint32_t              ErrorCode;        /*!< I2C Error code                   */
+
+  __IO uint32_t              AddrEventCount;   /*!< I2C Address Event counter        */
+}I2C_HandleTypeDef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2C_Exported_Constants I2C Exported Constants
+  * @{
+  */
+
+/** @defgroup I2C_addressing_mode I2C addressing mode
+  * @{
+  */
+#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00000001)
+#define I2C_ADDRESSINGMODE_10BIT        ((uint32_t)0x00000002)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
+  * @{
+  */
+#define I2C_DUALADDRESS_DISABLE         ((uint32_t)0x00000000)
+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address2_masks I2C own address2 masks
+  * @{
+  */
+#define I2C_OA2_NOMASK                  ((uint8_t)0x00)
+#define I2C_OA2_MASK01                  ((uint8_t)0x01)
+#define I2C_OA2_MASK02                  ((uint8_t)0x02)
+#define I2C_OA2_MASK03                  ((uint8_t)0x03)
+#define I2C_OA2_MASK04                  ((uint8_t)0x04)
+#define I2C_OA2_MASK05                  ((uint8_t)0x05)
+#define I2C_OA2_MASK06                  ((uint8_t)0x06)
+#define I2C_OA2_MASK07                  ((uint8_t)0x07)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
+  * @{
+  */
+#define I2C_GENERALCALL_DISABLE         ((uint32_t)0x00000000)
+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN
+/**
+  * @}
+  */
+
+/** @defgroup I2C_nostretch_mode I2C nostretch mode
+  * @{
+  */
+#define I2C_NOSTRETCH_DISABLE           ((uint32_t)0x00000000)
+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
+  * @{
+  */
+#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
+#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000002)
+/**
+  * @}
+  */
+  
+/** @defgroup I2C_XferDirection_definition I2C XferDirection definition
+  * @{
+  */
+#define I2C_DIRECTION_TRANSMIT          ((uint32_t)0x00000000)
+#define I2C_DIRECTION_RECEIVE           ((uint32_t)0x00000001)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
+  * @{
+  */
+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD
+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND
+#define  I2C_SOFTEND_MODE               ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
+  * @{
+  */
+#define  I2C_NO_STARTSTOP               ((uint32_t)0x00000000)
+#define  I2C_GENERATE_STOP              I2C_CR2_STOP
+#define  I2C_GENERATE_START_READ        (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define  I2C_GENERATE_START_WRITE       I2C_CR2_START
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition
+  * @brief I2C Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define I2C_IT_ERRI                     I2C_CR1_ERRIE
+#define I2C_IT_TCI                      I2C_CR1_TCIE
+#define I2C_IT_STOPI                    I2C_CR1_STOPIE
+#define I2C_IT_NACKI                    I2C_CR1_NACKIE
+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE
+#define I2C_IT_RXI                      I2C_CR1_RXIE
+#define I2C_IT_TXI                      I2C_CR1_TXIE
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Flag_definition I2C Flag definition
+  * @{
+  */ 
+#define I2C_FLAG_TXE                    I2C_ISR_TXE
+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS
+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE
+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR
+#define I2C_FLAG_AF                     I2C_ISR_NACKF
+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF
+#define I2C_FLAG_TC                     I2C_ISR_TC
+#define I2C_FLAG_TCR                    I2C_ISR_TCR
+#define I2C_FLAG_BERR                   I2C_ISR_BERR
+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO
+#define I2C_FLAG_OVR                    I2C_ISR_OVR
+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT
+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY
+#define I2C_FLAG_DIR                    I2C_ISR_DIR
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+  
+/** @defgroup I2C_Exported_Macros I2C Exported Macros
+  * @{
+  */
+
+/** @brief Reset I2C handle state.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
+
+/** @brief  Enable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
+
+/** @brief  Disable the specified I2C interrupt.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to disable.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *   
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
+ 
+/** @brief  Check whether the specified I2C interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable
+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable
+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable
+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable
+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable
+  *            @arg @ref I2C_IT_RXI   RX interrupt enable
+  *            @arg @ref I2C_IT_TXI   TX interrupt enable
+  *
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified I2C flag is set or not.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status
+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)
+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *            @arg @ref I2C_FLAG_BUSY    Bus busy
+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)
+  *
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty
+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)
+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag
+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag
+  *            @arg @ref I2C_FLAG_BERR    Bus error
+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost
+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun            
+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception
+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag 
+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert
+  *
+  * @retval None
+  */
+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))
+ 
+/** @brief  Enable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))
+
+/** @brief  Disable the specified I2C peripheral.
+  * @param  __HANDLE__ specifies the I2C Handle.
+  * @retval None
+  */
+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
+
+/**
+  * @}
+  */
+
+/* Include I2C HAL Extended module */
+#include "stm32l4xx_hal_i2c_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup I2C_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions******************************/
+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* IO operation functions  ****************************************************/
+ /******* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
+
+ /******* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
+
+ /******* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
+/**
+  * @}
+  */
+
+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
+ * @{
+ */
+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
+/**
+  * @}
+  */ 
+
+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
+  * @{
+  */
+/* Peripheral State, Mode and Error functions  *********************************/
+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+
+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))
+
+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \
+                                         ((MASK) == I2C_OA2_MASK01) || \
+                                         ((MASK) == I2C_OA2_MASK02) || \
+                                         ((MASK) == I2C_OA2_MASK03) || \
+                                         ((MASK) == I2C_OA2_MASK04) || \
+                                         ((MASK) == I2C_OA2_MASK05) || \
+                                         ((MASK) == I2C_OA2_MASK06) || \
+                                         ((MASK) == I2C_OA2_MASK07))
+
+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \
+                                         ((CALL) == I2C_GENERALCALL_ENABLE))
+
+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))
+
+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))
+
+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \
+                                         ((MODE) == I2C_AUTOEND_MODE) || \
+                                         ((MODE) == I2C_SOFTEND_MODE))
+
+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \
+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \
+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \
+                                         ((REQUEST) == I2C_NO_STARTSTOP))
+
+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \
+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \
+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
+                                                   ((REQUEST) == I2C_LAST_FRAME))
+
+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
+
+#define I2C_GET_ADDR_MATCH(__HANDLE__)            (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
+#define I2C_GET_DIR(__HANDLE__)                   (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
+#define I2C_GET_ISR_REG(__HANDLE__)               ((__HANDLE__)->Instance->ISR)
+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         (((__ISR__) & (__FLAG__)) == (__FLAG__))
+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= (uint32_t)0x000003FF)
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FF)
+
+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
+
+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
+/**
+  * @}
+  */ 
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l4xx_hal_i2c.c file */
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_I2C_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_i2c_ex.h

@@ -0,0 +1,171 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of I2C HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_I2C_EX_H
+#define __STM32L4xx_HAL_I2C_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup I2CEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter
+  * @{
+  */
+#define I2C_ANALOGFILTER_ENABLE         ((uint32_t)0x00000000)
+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF
+/**
+  * @}
+  */
+
+/** @defgroup I2CEx_FastModePlus I2CEx FastModePlus
+  * @{
+  */
+#define I2C_FASTMODEPLUS_PB6            SYSCFG_CFGR1_I2C_PB6_FMP  /*!< Enable Fast Mode Plus on PB6       */
+#define I2C_FASTMODEPLUS_PB7            SYSCFG_CFGR1_I2C_PB7_FMP  /*!< Enable Fast Mode Plus on PB7       */
+#define I2C_FASTMODEPLUS_PB8            SYSCFG_CFGR1_I2C_PB8_FMP  /*!< Enable Fast Mode Plus on PB8       */
+#define I2C_FASTMODEPLUS_PB9            SYSCFG_CFGR1_I2C_PB9_FMP  /*!< Enable Fast Mode Plus on PB9       */
+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_CFGR1_I2C1_FMP     /*!< Enable Fast Mode Plus on I2C1 pins */
+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_CFGR1_I2C2_FMP     /*!< Enable Fast Mode Plus on I2C2 pins */
+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_CFGR1_I2C3_FMP     /*!< Enable Fast Mode Plus on I2C3 pins */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Constants I2C Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup I2C_Private_Macro I2C Private Macros
+  * @{
+  */
+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))
+
+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000F)
+
+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6)    || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7)   || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8)   || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9)   || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \
+                                          (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
+/**
+  * @}
+  */ 
+
+/* Private Functions ---------------------------------------------------------*/
+/** @defgroup I2C_Private_Functions I2C Private Functions
+  * @{
+  */
+/* Private functions are defined in stm32l4xx_hal_i2c_ex.c file */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_I2C_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd.h

@@ -0,0 +1,312 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PCD_H
+#define __STM32L4xx_HAL_PCD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_usb.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCD
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup PCD_Exported_Types PCD Exported Types
+  * @{
+  */
+
+   /** 
+  * @brief  PCD State structure definition  
+  */  
+typedef enum 
+{
+  HAL_PCD_STATE_RESET   = 0x00,
+  HAL_PCD_STATE_READY   = 0x01,
+  HAL_PCD_STATE_ERROR   = 0x02,
+  HAL_PCD_STATE_BUSY    = 0x03,
+  HAL_PCD_STATE_TIMEOUT = 0x04
+} PCD_StateTypeDef;
+
+/* Device LPM suspend state */
+typedef enum  
+{
+  LPM_L0 = 0x00, /* on */
+  LPM_L1 = 0x01, /* LPM L1 sleep */
+  LPM_L2 = 0x02, /* suspend */
+  LPM_L3 = 0x03, /* off */
+}PCD_LPM_StateTypeDef;
+
+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;
+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;
+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef ;                          
+
+/** 
+  * @brief  PCD Handle Structure definition  
+  */ 
+typedef struct
+{
+  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */
+  PCD_EPTypeDef           IN_ep[15];    /*!< IN endpoint parameters             */
+  PCD_EPTypeDef           OUT_ep[15];   /*!< OUT endpoint parameters            */ 
+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */
+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */
+  uint32_t                Setup[12];   /*!< Setup packet buffer                */
+  PCD_LPM_StateTypeDef    LPM_State;    /*!< LPM State                          */
+  uint32_t                BESL;
+  
+  
+  uint32_t lpm_active;                  /*!< Enable or disable the Link Power Management .                                  
+                                        This parameter can be set to ENABLE or DISABLE                      */
+
+  uint32_t battery_charging_active;     /*!< Enable or disable Battery charging.                                  
+                                        This parameter can be set to ENABLE or DISABLE                      */
+  void                    *pData;      /*!< Pointer to upper stack Handler     */    
+  
+} PCD_HandleTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup PCD_Speed PCD Speed
+  * @{
+  */
+#define PCD_SPEED_FULL               1
+/**
+  * @}
+  */
+  
+/** @defgroup PCD_PHY_Module PCD PHY Module
+  * @{
+  */
+#define PCD_PHY_EMBEDDED             1
+/**
+  * @}
+  */
+
+/** @defgroup PCD_Turnaround_Timeout Turnaround Timeout Value
+  * @{
+  */
+#ifndef USBD_FS_TRDT_VALUE
+ #define USBD_FS_TRDT_VALUE           5
+#endif /* USBD_FS_TRDT_VALUE */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PCD_Exported_Macros PCD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+#define __HAL_PCD_ENABLE(__HANDLE__)                       USB_EnableGlobalInt ((__HANDLE__)->Instance)
+#define __HAL_PCD_DISABLE(__HANDLE__)                      USB_DisableGlobalInt ((__HANDLE__)->Instance)
+   
+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))
+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
+
+
+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \
+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)
+
+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK
+                                                      
+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
+                                                         
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                ((uint32_t)0x08) 
+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE               ((uint32_t)0x0C) 
+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE        ((uint32_t)0x10) 
+
+#define USB_OTG_FS_WAKEUP_EXTI_LINE                       ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the USB FS EXTI Line */
+
+                                                      
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI->IMR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI->IMR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG()     EXTI->PR1 & (USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG()   EXTI->PR1 = USB_OTG_FS_WAKEUP_EXTI_LINE
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE()  do {\
+                                                             EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                             EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                           } while(0)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do {\
+                                                             EXTI->FTSR1 |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                             EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                           } while(0)
+
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do {\
+                                                                   EXTI->RTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                                   EXTI->FTSR1 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+                                                                   EXTI->RTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                                   EXTI->FTSR1 |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+                                                                  } while(0)                                                                   
+                                                         
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT()   (EXTI->SWIER1 |= USB_OTG_FS_WAKEUP_EXTI_LINE)                                                          
+
+/**
+  * @}
+  */
+
+/* Include PCD HAL Extended module */
+#include "stm32l4xx_hal_pcd_ex.h"
+
+/** @addtogroup PCD_Exported_Functions PCD Exported Functions
+  * @{
+  */
+
+/* Initialization/de-initialization functions  ********************************/
+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* I/O operation functions  ***************************************************/
+/* Non-Blocking mode: Interrupt */
+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+ /* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
+
+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  **********************************************/
+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
+uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  ************************************************/
+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup PCD_Private_Macros PCD Private Macros
+ * @{
+ */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PCD_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pcd_ex.h

@@ -0,0 +1,120 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of PCD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PCD_EX_H
+#define __STM32L4xx_HAL_PCD_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+   
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PCDEx
+  * @{
+  */
+/* Exported types ------------------------------------------------------------*/
+typedef enum  
+{
+  PCD_LPM_L0_ACTIVE = 0x00, /* on */
+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
+}PCD_LPM_MsgTypeDef;
+
+typedef enum  
+{
+  PCD_BCD_ERROR                     = 0xFF, 
+  PCD_BCD_CONTACT_DETECTION         = 0xFE,
+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,
+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,
+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,
+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,
+  
+}PCD_BCD_MsgTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);
+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);
+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PCD_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr.h

@@ -0,0 +1,427 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of PWR HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PWR_H
+#define __STM32L4xx_HAL_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** @defgroup PWR_Exported_Types PWR Exported Types
+  * @{
+  */
+
+/**
+  * @brief  PWR PVD configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
+                            This parameter can be a value of @ref PWR_PVD_detection_level. */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWR_PVD_Mode. */
+}PWR_PVDTypeDef;
+
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants PWR Exported Constants
+  * @{
+  */
+
+
+/** @defgroup PWR_PVD_detection_level Programmable Voltage Detection levels
+  * @{
+  */
+#define PWR_PVDLEVEL_0                  PWR_CR2_PLS_LEV0  /*!< PVD threshold around 2.0 V */
+#define PWR_PVDLEVEL_1                  PWR_CR2_PLS_LEV1  /*!< PVD threshold around 2.2 V */
+#define PWR_PVDLEVEL_2                  PWR_CR2_PLS_LEV2  /*!< PVD threshold around 2.4 V */
+#define PWR_PVDLEVEL_3                  PWR_CR2_PLS_LEV3  /*!< PVD threshold around 2.5 V */
+#define PWR_PVDLEVEL_4                  PWR_CR2_PLS_LEV4  /*!< PVD threshold around 2.6 V */
+#define PWR_PVDLEVEL_5                  PWR_CR2_PLS_LEV5  /*!< PVD threshold around 2.8 V */
+#define PWR_PVDLEVEL_6                  PWR_CR2_PLS_LEV6  /*!< PVD threshold around 2.9 V */
+#define PWR_PVDLEVEL_7                  PWR_CR2_PLS_LEV7  /*!< External input analog voltage (compared internally to VREFINT) */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_Mode  PWR PVD interrupt and event mode
+  * @{
+  */
+#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< Basic mode is used */
+#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */                               
+/**
+  * @}
+  */
+  
+  
+
+
+/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode  PWR regulator mode
+  * @{
+  */
+#define PWR_MAINREGULATOR_ON            ((uint32_t)0x00000000) /*!< Regulator in main mode      */
+#define PWR_LOWPOWERREGULATOR_ON        PWR_CR1_LPR            /*!< Regulator in low-power mode */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_SLEEP_mode_entry  PWR SLEEP mode entry
+  * @{
+  */
+#define PWR_SLEEPENTRY_WFI              ((uint8_t)0x01)        /*!< Wait For Interruption instruction to enter Sleep mode */
+#define PWR_SLEEPENTRY_WFE              ((uint8_t)0x02)        /*!< Wait For Event instruction to enter Sleep mode        */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry  PWR STOP mode entry
+  * @{
+  */
+#define PWR_STOPENTRY_WFI               ((uint8_t)0x01)       /*!< Wait For Interruption instruction to enter Stop mode */
+#define PWR_STOPENTRY_WFE               ((uint8_t)0x02)       /*!< Wait For Event instruction to enter Stop mode        */
+/**
+  * @}
+  */
+  
+
+/** @defgroup PWR_PVD_EXTI_LINE  PWR PVD external interrupt line
+  * @{
+  */
+#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)   /*!< External interrupt line 16 Connected to the PVD EXTI Line */
+/**
+  * @}
+  */
+
+/** @defgroup PWR_PVD_EVENT_LINE  PWR PVD event line
+  * @{
+  */  
+#define PWR_EVENT_LINE_PVD  ((uint32_t)0x00010000)  /*!< Event line 16 Connected to the PVD Event Line */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWR_Exported_Macros  PWR Exported Macros
+  * @{
+  */
+
+/** @brief  Check whether or not a specific PWR flag is set.
+  * @param  __FLAG__: specifies the flag to check.
+  *           This parameter can be one of the following values:
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3.
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5.          
+  *            @arg @ref PWR_FLAG_SB StandBy Flag. Indicates that the system
+  *                  entered StandBy mode.
+  *            @arg @ref PWR_FLAG_WUFI Wake-Up Flag Internal. Set when a wakeup is detected on
+  *                 the internal wakeup line.
+  *            @arg @ref PWR_FLAG_REGLPS Low Power Regulator Started. Indicates whether or not the 
+  *                 low-power regulator is ready.
+  *            @arg @ref PWR_FLAG_REGLPF Low Power Regulator Flag. Indicates whether the 
+  *                 regulator is ready in main mode or is in low-power mode. 
+  *            @arg @ref PWR_FLAG_VOSF Voltage Scaling Flag. Indicates whether the regulator is ready 
+  *                 in the selected voltage range or is still changing to the required voltage level.
+  *            @arg @ref PWR_FLAG_PVDO Power Voltage Detector Output. Indicates whether VDD voltage is
+  *                  below or above the selected PVD threshold.
+  *            @arg @ref PWR_FLAG_PVMO1 Peripheral Voltage Monitoring Output 1. Indicates whether VDDUSB voltage is
+  *                  is below or above PVM1 threshold (applicable when USB feature is supported).
+  *            @arg @ref PWR_FLAG_PVMO2 Peripheral Voltage Monitoring Output 2. Indicates whether VDDIO2 voltage is
+  *                  is below or above PVM2 threshold (applicable when VDDIO2 is present on device). 
+  *            @arg @ref PWR_FLAG_PVMO3 Peripheral Voltage Monitoring Output 3. Indicates whether VDDA voltage is
+  *                  is below or above PVM3 threshold. 
+  *            @arg @ref PWR_FLAG_PVMO4 Peripheral Voltage Monitoring Output 4. Indicates whether VDDA voltage is
+  *                  is below or above PVM4 threshold.                           
+  *    
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_FLAG(__FLAG__)  ( ((((uint8_t)(__FLAG__)) >> 5U) == 1)  ?\
+                                      (PWR->SR1 & (1U << ((__FLAG__) & 31U))) :\
+                                      (PWR->SR2 & (1U << ((__FLAG__) & 31U))) )
+
+/** @brief  Clear a specific PWR flag.
+  * @param  __FLAG__: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_FLAG_WUF1 Wake Up Flag 1. Indicates that a wakeup event
+  *                  was received from the WKUP pin 1.
+  *            @arg @ref PWR_FLAG_WUF2 Wake Up Flag 2. Indicates that a wakeup event
+  *                  was received from the WKUP pin 2.
+  *            @arg @ref PWR_FLAG_WUF3 Wake Up Flag 3. Indicates that a wakeup event
+  *                  was received from the WKUP pin 3.
+  *            @arg @ref PWR_FLAG_WUF4 Wake Up Flag 4. Indicates that a wakeup event
+  *                  was received from the WKUP pin 4.
+  *            @arg @ref PWR_FLAG_WUF5 Wake Up Flag 5. Indicates that a wakeup event
+  *                  was received from the WKUP pin 5.
+  *            @arg @ref PWR_FLAG_WU Encompasses all five Wake Up Flags.
+  *            @arg @ref PWR_FLAG_SB Standby Flag. Indicates that the system
+  *                  entered Standby mode.
+  * @retval None   
+  */
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)   ( (((uint8_t)(__FLAG__)) == PWR_FLAG_WU) ?\
+                                         (PWR->SCR  = (__FLAG__)) :\
+                                         (PWR->SCR = (1U << ((__FLAG__) & 31U))) )
+/**
+  * @brief Enable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
+
+
+/**
+  * @brief  Enable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                   \
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Check whether or not the PVD EXTI interrupt flag is set.
+  * @retval EXTI PVD Line Status.
+  */
+#define __HAL_PWR_PVD_EXTI_GET_FLAG()  (EXTI->PR1 & PWR_EXTI_LINE_PVD)
+
+/**
+  * @brief Clear the PVD EXTI interrupt flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR1, PWR_EXTI_LINE_PVD)
+
+/**
+  * @}
+  */
+  
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  PWR_Private_Macros   PWR Private Macros
+  * @{
+  */
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
+                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
+                                 
+#define IS_PWR_PVD_MODE(MODE)  (((MODE) == PWR_PVD_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVD_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVD_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) 
+                                
+#define IS_PWR_REGULATOR(REGULATOR)      (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+                                          ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
+                                          
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
+                                      
+/**
+  * @}
+  */  
+
+/* Include PWR HAL Extended module */
+#include "stm32l4xx_hal_pwr_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  * @{
+  */
+  
+/* Initialization and de-initialization functions *******************************/
+void HAL_PWR_DeInit(void);
+void HAL_PWR_EnableBkUpAccess(void);
+void HAL_PWR_DisableBkUpAccess(void);
+
+/**
+  * @}
+  */
+
+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
+void HAL_PWR_EnablePVD(void);
+void HAL_PWR_DisablePVD(void);
+
+
+/* WakeUp pins configuration functions ****************************************/
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
+void HAL_PWR_EnterSTANDBYMode(void);
+
+void HAL_PWR_EnableSleepOnExit(void);
+void HAL_PWR_DisableSleepOnExit(void);
+void HAL_PWR_EnableSEVOnPend(void);
+void HAL_PWR_DisableSEVOnPend(void);
+
+void HAL_PWR_PVDCallback(void);
+
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PWR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_pwr_ex.h

@@ -0,0 +1,825 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of PWR HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_PWR_EX_H
+#define __STM32L4xx_HAL_PWR_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup PWREx
+  * @{
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
+  * @{
+  */
+
+
+/**
+  * @brief  PWR PVM configuration structure definition
+  */
+typedef struct
+{
+  uint32_t PVMType;   /*!< PVMType: Specifies which voltage is monitored and against which threshold. 
+                           This parameter can be a value of @ref PWREx_PVM_Type. 
+                           @arg @ref PWR_PVM_1 Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported). 
+                           @arg @ref PWR_PVM_2 Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device). 
+                           @arg @ref PWR_PVM_3 Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V. 
+                           @arg @ref PWR_PVM_4 Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V. */
+
+  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
+                           This parameter can be a value of @ref PWREx_PVM_Mode. */
+}PWR_PVMTypeDef;
+
+/**
+  * @}
+  */ 
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWREx_Exported_Constants  PWR Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup PWREx_WUP_Polarity Shift to apply to retrieve polarity information from PWR_WAKEUP_PINy_xxx constants
+  * @{
+  */
+#define PWR_WUP_POLARITY_SHIFT                  0x05   /*!< Internal constant used to retrieve wakeup pin polariry */
+/**
+  * @}
+  */  
+
+
+/** @defgroup PWREx_WakeUp_Pins  PWR wake-up pins
+  * @{
+  */                                                      
+#define PWR_WAKEUP_PIN1                 PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2                 PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3                 PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4                 PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5                 PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_HIGH            PWR_CR3_EWUP1  /*!< Wakeup pin 1 (with high level polarity) */
+#define PWR_WAKEUP_PIN2_HIGH            PWR_CR3_EWUP2  /*!< Wakeup pin 2 (with high level polarity) */
+#define PWR_WAKEUP_PIN3_HIGH            PWR_CR3_EWUP3  /*!< Wakeup pin 3 (with high level polarity) */
+#define PWR_WAKEUP_PIN4_HIGH            PWR_CR3_EWUP4  /*!< Wakeup pin 4 (with high level polarity) */
+#define PWR_WAKEUP_PIN5_HIGH            PWR_CR3_EWUP5  /*!< Wakeup pin 5 (with high level polarity) */
+#define PWR_WAKEUP_PIN1_LOW             (uint32_t)((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
+#define PWR_WAKEUP_PIN2_LOW             (uint32_t)((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
+#define PWR_WAKEUP_PIN3_LOW             (uint32_t)((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
+#define PWR_WAKEUP_PIN4_LOW             (uint32_t)((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
+#define PWR_WAKEUP_PIN5_LOW             (uint32_t)((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
+/**
+  * @}
+  */
+
+/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
+  * @{
+  */
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define PWR_PVM_1                  PWR_CR2_PVME1  /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#define PWR_PVM_2                  PWR_CR2_PVME2  /*!< Peripheral Voltage Monitoring 2 enable: VDDIO2 versus 0.9 V (applicable when VDDIO2 is present on device) */
+#define PWR_PVM_3                  PWR_CR2_PVME3  /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
+#define PWR_PVM_4                  PWR_CR2_PVME4  /*!< Peripheral Voltage Monitoring 4 enable: VDDA versus 2.2 V  */
+/**
+  * @}
+  */  
+  
+/** @defgroup PWREx_PVM_Mode  PWR PVM interrupt and event mode
+  * @{
+  */
+#define PWR_PVM_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
+#define PWR_PVM_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
+#define PWR_PVM_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
+#define PWR_PVM_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
+/**
+  * @}
+  */
+  
+  
+
+/** @defgroup PWREx_Regulator_Voltage_Scale  PWR Regulator voltage scale
+  * @{
+  */
+#define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR1_VOS_0     /*!< Voltage scaling range 1 */
+#define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR1_VOS_1     /*!< Voltage scaling range 2 */
+/**
+  * @}
+  */
+
+  
+/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR battery charging resistor selection
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_RESISTOR_5          ((uint32_t)0x00000000) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5         PWR_CR4_VBRS          /*!< VBAT charging through a 1.5 kOhms resistor */
+/**
+  * @}
+  */
+  
+/** @defgroup PWREx_VBAT_Battery_Charging PWR battery charging
+  * @{
+  */
+#define PWR_BATTERY_CHARGING_DISABLE        ((uint32_t)0x00000000)
+#define PWR_BATTERY_CHARGING_ENABLE         PWR_CR4_VBE
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
+  * @{
+  */
+#define PWR_GPIO_BIT_0   PWR_PUCRA_PA0    /*!< GPIO port I/O pin 0  */
+#define PWR_GPIO_BIT_1   PWR_PUCRA_PA1    /*!< GPIO port I/O pin 1  */
+#define PWR_GPIO_BIT_2   PWR_PUCRA_PA2    /*!< GPIO port I/O pin 2  */
+#define PWR_GPIO_BIT_3   PWR_PUCRA_PA3    /*!< GPIO port I/O pin 3  */
+#define PWR_GPIO_BIT_4   PWR_PUCRA_PA4    /*!< GPIO port I/O pin 4  */
+#define PWR_GPIO_BIT_5   PWR_PUCRA_PA5    /*!< GPIO port I/O pin 5  */
+#define PWR_GPIO_BIT_6   PWR_PUCRA_PA6    /*!< GPIO port I/O pin 6  */
+#define PWR_GPIO_BIT_7   PWR_PUCRA_PA7    /*!< GPIO port I/O pin 7  */
+#define PWR_GPIO_BIT_8   PWR_PUCRA_PA8    /*!< GPIO port I/O pin 8  */
+#define PWR_GPIO_BIT_9   PWR_PUCRA_PA9    /*!< GPIO port I/O pin 9  */
+#define PWR_GPIO_BIT_10  PWR_PUCRA_PA10   /*!< GPIO port I/O pin 10 */
+#define PWR_GPIO_BIT_11  PWR_PUCRA_PA11   /*!< GPIO port I/O pin 11 */
+#define PWR_GPIO_BIT_12  PWR_PUCRA_PA12   /*!< GPIO port I/O pin 12 */
+#define PWR_GPIO_BIT_13  PWR_PUCRA_PA13   /*!< GPIO port I/O pin 13 */
+#define PWR_GPIO_BIT_14  PWR_PDCRA_PA14   /*!< GPIO port I/O pin 14 */
+#define PWR_GPIO_BIT_15  PWR_PUCRA_PA15   /*!< GPIO port I/O pin 15 */
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_GPIO GPIO port
+  * @{
+  */
+#define PWR_GPIO_A   0x00000000      /*!< GPIO port A */
+#define PWR_GPIO_B   0x00000001      /*!< GPIO port B */
+#define PWR_GPIO_C   0x00000002      /*!< GPIO port C */
+#define PWR_GPIO_D   0x00000003      /*!< GPIO port D */
+#define PWR_GPIO_E   0x00000004      /*!< GPIO port E */
+#define PWR_GPIO_F   0x00000005      /*!< GPIO port F */
+#define PWR_GPIO_G   0x00000006      /*!< GPIO port G */
+#define PWR_GPIO_H   0x00000007      /*!< GPIO port H */
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
+  * @{
+  */    
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define PWR_EXTI_LINE_PVM1  ((uint32_t)0x00000008)  /*!< External interrupt line 35 Connected to the PVM1 EXTI Line   */
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#define PWR_EXTI_LINE_PVM2  ((uint32_t)0x00000010)  /*!< External interrupt line 36 Connected to the PVM2 EXTI Line   */
+#define PWR_EXTI_LINE_PVM3  ((uint32_t)0x00000020)  /*!< External interrupt line 37 Connected to the PVM3 EXTI Line   */
+#define PWR_EXTI_LINE_PVM4  ((uint32_t)0x00000040)  /*!< External interrupt line 38 Connected to the PVM4 EXTI Line   */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_PVM_EVENT_LINE PWR PVM event lines
+  * @{
+  */    
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define PWR_EVENT_LINE_PVM1 ((uint32_t)0x00000008)  /*!< Event line 35 Connected to the PVM1 EXTI Line */
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#define PWR_EVENT_LINE_PVM2 ((uint32_t)0x00000010)  /*!< Event line 36 Connected to the PVM2 EXTI Line */
+#define PWR_EVENT_LINE_PVM3 ((uint32_t)0x00000020)  /*!< Event line 37 Connected to the PVM3 EXTI Line */
+#define PWR_EVENT_LINE_PVM4 ((uint32_t)0x00000040)  /*!< Event line 38 Connected to the PVM4 EXTI Line */ 
+/**
+  * @}
+  */ 
+  
+/** @defgroup PWREx_Flag  PWR Status Flags
+  *        Elements values convention: 0000 0000 0XXY YYYYb
+  *           - Y YYYY  : Flag position in the XX register (5 bits)
+  *           - XX  : Status register (2 bits)
+  *                 - 01: SR1 register
+  *                 - 10: SR2 register
+  *        The only exception is PWR_FLAG_WU, encompassing all
+  *        wake-up flags and set to PWR_SR1_WUF.    
+  * @{   
+  */  
+#define PWR_FLAG_WUF1                       ((uint32_t)0x0020)   /*!< Wakeup event on wakeup pin 1 */
+#define PWR_FLAG_WUF2                       ((uint32_t)0x0021)   /*!< Wakeup event on wakeup pin 2 */
+#define PWR_FLAG_WUF3                       ((uint32_t)0x0022)   /*!< Wakeup event on wakeup pin 3 */
+#define PWR_FLAG_WUF4                       ((uint32_t)0x0023)   /*!< Wakeup event on wakeup pin 4 */
+#define PWR_FLAG_WUF5                       ((uint32_t)0x0024)   /*!< Wakeup event on wakeup pin 5 */
+#define PWR_FLAG_WU                         PWR_SR1_WUF          /*!< Encompass wakeup event on all wakeup pins */
+#define PWR_FLAG_SB                         ((uint32_t)0x0028)   /*!< Standby flag */
+#define PWR_FLAG_WUFI                       ((uint32_t)0x002F)   /*!< Wakeup on internal wakeup line */
+
+#define PWR_FLAG_REGLPS                     ((uint32_t)0x0048)   /*!< Low-power regulator start flag */
+#define PWR_FLAG_REGLPF                     ((uint32_t)0x0049)   /*!< Low-power regulator flag */
+#define PWR_FLAG_VOSF                       ((uint32_t)0x004A)   /*!< Voltage scaling flag */
+#define PWR_FLAG_PVDO                       ((uint32_t)0x004B)   /*!< Power Voltage Detector output flag */
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define PWR_FLAG_PVMO1                      ((uint32_t)0x004C)   /*!< Power Voltage Monitoring 1 output flag */
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+#define PWR_FLAG_PVMO2                      ((uint32_t)0x004D)   /*!< Power Voltage Monitoring 2 output flag */
+#define PWR_FLAG_PVMO3                      ((uint32_t)0x004E)   /*!< Power Voltage Monitoring 3 output flag */
+#define PWR_FLAG_PVMO4                      ((uint32_t)0x004F)   /*!< Power Voltage Monitoring 4 output flag */
+/**
+  * @}
+  */        
+
+/**
+  * @}
+  */  
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
+ * @{
+ */
+
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+/**
+  * @brief Enable the PVM1 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Enable the PVM1 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
+
+
+/**
+  * @brief  PVM1 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief Disable the PVM1 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Check whether the specified PVM1 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM1 Line Status.
+  */
+#define __HAL_PWR_PVM1_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM1)
+
+/**
+  * @brief Clear the PVM1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM1)
+
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Enable the PVM2 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+
+/**
+  * @brief Disable the PVM2 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
+
+
+/**
+  * @brief  PVM2 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+  
+/**
+  * @brief Disable the PVM2 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Check whether the specified PVM2 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM2 Line Status.
+  */
+#define __HAL_PWR_PVM2_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM2)
+
+/**
+  * @brief Clear the PVM2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM2_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM2)
+
+
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Enable the PVM3 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+
+/**
+  * @brief Disable the PVM3 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM3)
+
+
+/**
+  * @brief  PVM3 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+  
+/**
+  * @brief Disable the PVM3 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Check whether the specified PVM3 EXTI interrupt flag is set or not.
+  * @retval EXTI PVM3 Line Status.
+  */
+#define __HAL_PWR_PVM3_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM3)
+
+/**
+  * @brief Clear the PVM3 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM3)
+
+
+
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Event Line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Rising Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Enable the PVM4 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief Disable the PVM4 Extended Interrupt Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief  PVM4 EXTI line configuration: set rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_ENABLE_RISING_FALLING_EDGE()  \
+  do {                                                    \
+    __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE();            \
+  } while(0)
+  
+/**
+  * @brief Disable the PVM4 Extended Interrupt Rising & Falling Trigger.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_DISABLE_RISING_FALLING_EDGE()  \
+  do {                                                     \
+    __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE();             \
+    __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE();            \
+  } while(0)
+
+/**
+  * @brief  Generate a Software interrupt on selected EXTI line.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Check whether or not the specified PVM4 EXTI interrupt flag is set.
+  * @retval EXTI PVM4 Line Status.
+  */
+#define __HAL_PWR_PVM4_EXTI_GET_FLAG()  (EXTI->PR2 & PWR_EXTI_LINE_PVM4)
+
+/**
+  * @brief Clear the PVM4 EXTI flag.
+  * @retval None
+  */
+#define __HAL_PWR_PVM4_EXTI_CLEAR_FLAG()  WRITE_REG(EXTI->PR2, PWR_EXTI_LINE_PVM4)
+
+
+/**
+  * @brief Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
+  *         a tradeoff between performance and power consumption.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1  Regulator voltage output range 1 mode,
+  *                                                typical output voltage at 1.2 V,  
+  *                                                system frequency up to 80 MHz.
+  *            @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2  Regulator voltage output range 2 mode,
+  *                                                typical output voltage at 1.0 V,                
+  *                                                system frequency up to 26 MHz.  
+  * @note  This macro is similar to HAL_PWREx_ControlVoltageScaling() API but doesn't check
+  *        whether or not VOSF flag is cleared when moving from range 2 to range 1. User
+  *        may resort to __HAL_PWR_GET_FLAG() macro to check VOSF bit resetting.   
+  * @retval None
+  */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do {                                                     \
+                                                            __IO uint32_t tmpreg;                               \
+                                                            MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
+                                                            /* Delay after an RCC peripheral clock enabling */  \
+                                                            tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS);           \
+                                                            UNUSED(tmpreg);                                     \
+                                                          } while(0)
+
+/**
+  * @}
+  */
+  
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup  PWREx_Private_Macros   PWR Extended Private Macros
+  * @{
+  */
+
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
+                                ((PIN) == PWR_WAKEUP_PIN2) || \
+                                ((PIN) == PWR_WAKEUP_PIN3) || \
+                                ((PIN) == PWR_WAKEUP_PIN4) || \
+                                ((PIN) == PWR_WAKEUP_PIN5) || \
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) || \
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW))
+                                
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
+                               ((TYPE) == PWR_PVM_2) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#elif defined (STM32L471xx)
+#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_2) ||\
+                               ((TYPE) == PWR_PVM_3) ||\
+                               ((TYPE) == PWR_PVM_4))
+#endif
+
+#define IS_PWR_PVM_MODE(MODE)  (((MODE) == PWR_PVM_MODE_NORMAL)              ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING)           ||\
+                                ((MODE) == PWR_PVM_MODE_IT_FALLING)          ||\
+                                ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING)   ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING)        ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_FALLING)       ||\
+                                ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING))  
+                                
+#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
+                                             
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))  
+                                                  
+#define IS_PWR_BATTERY_CHARGING(CHARGING) (((CHARGING) == PWR_BATTERY_CHARGING_DISABLE) ||\
+                                           ((CHARGING) == PWR_BATTERY_CHARGING_ENABLE)) 
+                                           
+#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
+                                           
+                             
+#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
+                           ((GPIO) == PWR_GPIO_B) ||\
+                           ((GPIO) == PWR_GPIO_C) ||\
+                           ((GPIO) == PWR_GPIO_D) ||\
+                           ((GPIO) == PWR_GPIO_E) ||\
+                           ((GPIO) == PWR_GPIO_F) ||\
+                           ((GPIO) == PWR_GPIO_G) ||\
+                           ((GPIO) == PWR_GPIO_H))
+
+
+/**
+  * @}
+  */  
+  
+
+/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions
+  * @{
+  */
+  
+/** @addtogroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 
+  * @{
+  */
+
+
+/* Peripheral Control functions  **********************************************/
+uint32_t HAL_PWREx_GetVoltageRange(void);
+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection);
+void HAL_PWREx_DisableBatteryCharging(void);
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+void HAL_PWREx_EnableVddUSB(void);
+void HAL_PWREx_DisableVddUSB(void);
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+void HAL_PWREx_EnableVddIO2(void);
+void HAL_PWREx_DisableVddIO2(void);
+void HAL_PWREx_EnableInternalWakeUpLine(void);
+void HAL_PWREx_DisableInternalWakeUpLine(void);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber);
+void HAL_PWREx_EnablePullUpPullDownConfig(void);
+void HAL_PWREx_DisablePullUpPullDownConfig(void);
+void HAL_PWREx_EnableSRAM2ContentRetention(void);
+void HAL_PWREx_DisableSRAM2ContentRetention(void);
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+void HAL_PWREx_EnablePVM1(void);
+void HAL_PWREx_DisablePVM1(void);
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+void HAL_PWREx_EnablePVM2(void);
+void HAL_PWREx_DisablePVM2(void);
+void HAL_PWREx_EnablePVM3(void);
+void HAL_PWREx_DisablePVM3(void);
+void HAL_PWREx_EnablePVM4(void);
+void HAL_PWREx_DisablePVM4(void);
+HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
+
+
+/* Low Power modes configuration functions ************************************/
+void HAL_PWREx_EnableLowPowerRunMode(void);
+HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void);
+void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry);
+void HAL_PWREx_EnterSHUTDOWNMode(void);
+
+void HAL_PWREx_PVD_PVM_IRQHandler(void);
+#if defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx)
+void HAL_PWREx_PVM1Callback(void);
+#endif /* defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */
+void HAL_PWREx_PVM2Callback(void);
+void HAL_PWREx_PVM3Callback(void);
+void HAL_PWREx_PVM4Callback(void);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_PWR_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_qspi.h

@@ -0,0 +1,648 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_qspi.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of QSPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************  
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_QSPI_H
+#define __STM32L4xx_HAL_QSPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup QSPI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup QSPI_Exported_Types QSPI Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  QSPI Init structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.
+                                  This parameter can be a number between 0 and 255 */ 
+  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
+                                  This parameter can be a value between 1 and 16 */
+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 
+                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
+                                  This parameter can be a value of @ref QSPI_SampleShifting */
+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 
+                                  required to address the flash memory. The flash capacity can be up to 4GB 
+                                  (addressed using 32 bits) in indirect mode, but the addressable space in 
+                                  memory-mapped mode is limited to 256MB
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 
+                                  of clock cycles which the chip select must remain high between commands.
+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */   
+  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
+                                  This parameter can be a value of @ref QSPI_ClockMode */
+}QSPI_InitTypeDef;
+
+/** 
+  * @brief HAL QSPI State structures definition  
+  */ 
+typedef enum
+{
+  HAL_QSPI_STATE_RESET             = 0x00,    /*!< Peripheral not initialized                            */
+  HAL_QSPI_STATE_READY             = 0x01,    /*!< Peripheral initialized and ready for use              */
+  HAL_QSPI_STATE_BUSY              = 0x02,    /*!< Peripheral in indirect mode and busy                  */ 
+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12,    /*!< Peripheral in indirect mode with transmission ongoing */ 
+  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22,    /*!< Peripheral in indirect mode with reception ongoing    */
+  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42,    /*!< Peripheral in auto polling mode ongoing               */
+  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82,    /*!< Peripheral in memory mapped mode ongoing              */
+  HAL_QSPI_STATE_ERROR             = 0x04     /*!< Peripheral in error                                   */
+}HAL_QSPI_StateTypeDef;
+
+/** 
+  * @brief  QSPI Handle Structure definition  
+  */  
+typedef struct
+{
+  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */
+  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */
+  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */
+  __IO uint16_t              TxXferSize;       /* QSPI Tx Transfer size              */
+  __IO uint16_t              TxXferCount;      /* QSPI Tx Transfer Counter           */
+  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */
+  __IO uint16_t              RxXferSize;       /* QSPI Rx Transfer size              */
+  __IO uint16_t              RxXferCount;      /* QSPI Rx Transfer Counter           */
+  DMA_HandleTypeDef          *hdma;            /* QSPI Rx/Tx DMA Handle parameters   */
+  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */
+  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */
+  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */
+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */ 
+}QSPI_HandleTypeDef;
+
+/** 
+  * @brief  QSPI Command structure definition  
+  */
+typedef struct
+{
+  uint32_t Instruction;        /* Specifies the Instruction to be sent
+                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */
+  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
+  uint32_t AddressSize;        /* Specifies the Address Size
+                                  This parameter can be a value of @ref QSPI_AddressSize */
+  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
+                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */
+  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.
+                                  This parameter can be a number between 0 and 31 */
+  uint32_t InstructionMode;    /* Specifies the Instruction Mode
+                                  This parameter can be a value of @ref QSPI_InstructionMode */
+  uint32_t AddressMode;        /* Specifies the Address Mode
+                                  This parameter can be a value of @ref QSPI_AddressMode */
+  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode
+                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */
+  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)
+                                  This parameter can be a value of @ref QSPI_DataMode */
+  uint32_t NbData;             /* Specifies the number of data to transfer. 
+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 
+                                  until end of memory)*/
+  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase
+                                  This parameter can be a value of @ref QSPI_DdrMode */
+  uint32_t DdrHoldHalfCycle;   /* Specifies the DDR hold half cycle. It delays the data output by one half of 
+                                  system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
+                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
+  uint32_t SIOOMode;           /* Specifies the send instruction only once mode
+                                  This parameter can be a value of @ref QSPI_SIOOMode */
+}QSPI_CommandTypeDef;
+
+/** 
+  * @brief  QSPI Auto Polling mode configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received. 
+                                  This parameter can be any value between 0 and 0xFFFFFFFF */
+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.
+                                  This parameter can be any value between 1 and 4 */
+  uint32_t MatchMode;          /* Specifies the method used for determining a match.
+                                  This parameter can be a value of @ref QSPI_MatchMode */
+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.
+                                  This parameter can be a value of @ref QSPI_AutomaticStop */
+}QSPI_AutoPollingTypeDef;
+                           
+/** 
+  * @brief  QSPI Memory Mapped mode configuration structure definition  
+  */
+typedef struct
+{
+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
+                                  This parameter can be any value between 0 and 0xFFFF */
+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select. 
+                                  This parameter can be a value of @ref QSPI_TimeOutActivation */
+}QSPI_MemoryMappedTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants
+  * @{
+  */
+
+/** @defgroup QSPI_ErrorCode QSPI Error Code
+  * @{
+  */ 
+#define HAL_QSPI_ERROR_NONE            ((uint32_t)0x00000000) /*!< No error           */
+#define HAL_QSPI_ERROR_TIMEOUT         ((uint32_t)0x00000001) /*!< Timeout error      */
+#define HAL_QSPI_ERROR_TRANSFER        ((uint32_t)0x00000002) /*!< Transfer error     */
+#define HAL_QSPI_ERROR_DMA             ((uint32_t)0x00000004) /*!< DMA transfer error */
+/**
+  * @}
+  */ 
+
+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
+  * @{
+  */
+#define QSPI_SAMPLE_SHIFTING_NONE      ((uint32_t)0x00000000)        /*!<No clock cycle shift to sample data*/
+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
+/**
+  * @}
+  */ 
+
+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
+  * @{
+  */
+#define QSPI_CS_HIGH_TIME_1_CYCLE      ((uint32_t)0x00000000)                              /*!<nCS stay high for at least 1 clock cycle between commands*/
+#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
+#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_ClockMode QSPI Clock Mode
+  * @{
+  */
+#define QSPI_CLOCK_MODE_0              ((uint32_t)0x00000000)         /*!<Clk stays low while nCS is released*/
+#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressSize QSPI Address Size
+  * @{
+  */
+#define QSPI_ADDRESS_8_BITS            ((uint32_t)0x00000000)           /*!<8-bit address*/
+#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
+#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
+#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
+  * @{
+  */
+#define QSPI_ALTERNATE_BYTES_8_BITS    ((uint32_t)0x00000000)           /*!<8-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
+* @{
+*/
+#define QSPI_INSTRUCTION_NONE          ((uint32_t)0x00000000)          /*!<No instruction*/
+#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
+#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
+#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_AddressMode QSPI Address Mode
+* @{
+*/
+#define QSPI_ADDRESS_NONE              ((uint32_t)0x00000000)           /*!<No address*/
+#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
+#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
+#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
+* @{
+*/
+#define QSPI_ALTERNATE_BYTES_NONE      ((uint32_t)0x00000000)           /*!<No alternate bytes*/
+#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
+#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
+#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_DataMode QSPI Data Mode
+  * @{
+  */
+#define QSPI_DATA_NONE                 ((uint32_t)0X00000000)           /*!<No data*/
+#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
+#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
+#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_DdrMode QSPI DDR Mode
+  * @{
+  */
+#define QSPI_DDR_MODE_DISABLE          ((uint32_t)0x00000000)       /*!<Double data rate mode disabled*/
+#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
+  * @{
+  */
+#define QSPI_DDR_HHC_ANALOG_DELAY      ((uint32_t)0x00000000)       /*!<Delay the data output using analog delay in DDR mode*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
+  * @{
+  */
+#define QSPI_SIOO_INST_EVERY_CMD       ((uint32_t)0x00000000)       /*!<Send instruction on every transaction*/
+#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_MatchMode QSPI Match Mode
+  * @{
+  */
+#define QSPI_MATCH_MODE_AND            ((uint32_t)0x00000000)     /*!<AND match mode between unmasked bits*/
+#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
+  * @{
+  */
+#define QSPI_AUTOMATIC_STOP_DISABLE    ((uint32_t)0x00000000)      /*!<AutoPolling stops only with abort or QSPI disabling*/
+#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
+  * @{
+  */
+#define QSPI_TIMEOUT_COUNTER_DISABLE   ((uint32_t)0x00000000)      /*!<Timeout counter disabled, nCS remains active*/
+#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
+/**
+  * @}
+  */  
+
+/** @defgroup QSPI_Flags QSPI Flags
+  * @{
+  */
+#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
+#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/
+#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/
+#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
+#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
+#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Interrupts QSPI Interrupts
+  * @{
+  */  
+#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
+#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
+#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
+#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
+#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
+/**
+  * @}
+  */
+
+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition
+  * @brief QSPI Timeout definition
+  * @{
+  */ 
+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
+/**
+  * @}
+  */  
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros
+  * @{
+  */
+/** @brief Reset QSPI handle state.
+  * @param  __HANDLE__: QSPI handle.
+  * @retval None
+  */
+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
+
+/** @brief  Enable the QSPI peripheral.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @retval None
+  */ 
+#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Disable the QSPI peripheral.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
+
+/** @brief  Enable the specified QSPI interrupt.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __INTERRUPT__: specifies the QSPI interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+
+/** @brief  Disable the specified QSPI interrupt.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __INTERRUPT__: specifies the QSPI interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval None
+  */
+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
+
+/** @brief  Check whether the specified QSPI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __INTERRUPT__: specifies the QSPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt
+  *            @arg QSPI_IT_SM: QSPI Status match interrupt
+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt
+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 
+
+/**
+  * @brief  Check whether the selected QSPI flag is set or not.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __FLAG__: specifies the QSPI flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag
+  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM:   QSPI Status match flag
+  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag
+  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
+
+/** @brief  Clears the specified QSPI's flag status.
+  * @param  __HANDLE__: specifies the QSPI Handle.
+  * @param  __FLAG__: specifies the QSPI clear register flag that needs to be set
+  *          This parameter can be one of the following values:
+  *            @arg QSPI_FLAG_TO: QSPI Timeout flag
+  *            @arg QSPI_FLAG_SM: QSPI Status match flag
+  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag
+  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag
+  * @retval None
+  */
+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/  
+/** @addtogroup QSPI_Exported_Functions
+  * @{
+  */
+/* Initialization/de-initialization functions  ********************************/
+HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
+
+/* IO operation functions *****************************************************/
+/* QSPI IRQ handler method */
+void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
+
+/* QSPI status flag polling mode */
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
+HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
+
+/* QSPI memory-mapped mode */
+HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
+
+/* Callback functions in non-blocking modes ***********************************/
+void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
+
+/* QSPI indirect mode */
+void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_RxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_TxHalfCpltCallback   (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI status flag polling mode */
+void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);
+
+/* QSPI memory-mapped mode */
+void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);
+
+/* Peripheral Control and State functions  ************************************/
+HAL_QSPI_StateTypeDef HAL_QSPI_GetState  (QSPI_HandleTypeDef *hqspi);
+uint32_t              HAL_QSPI_GetError  (QSPI_HandleTypeDef *hqspi);
+HAL_StatusTypeDef     HAL_QSPI_Abort     (QSPI_HandleTypeDef *hqspi);
+void                  HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/  
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup QSPI_Private_Macros QSPI Private Macros
+* @{
+*/
+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
+
+#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0) && ((THR) <= 16))
+
+#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
+                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
+
+#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31))
+
+#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
+
+#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
+                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))
+
+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFF) 
+
+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
+                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
+
+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
+
+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31) 
+
+#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \
+                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \
+                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
+                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))
+
+#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \
+                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \
+                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \
+                                            ((MODE) == QSPI_ADDRESS_4_LINES))
+
+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
+                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
+
+#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \
+                                            ((MODE) == QSPI_DATA_1_LINE)  || \
+                                            ((MODE) == QSPI_DATA_2_LINES) || \
+                                            ((MODE) == QSPI_DATA_4_LINES))
+
+#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
+                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
+
+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
+
+#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
+                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
+
+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 
+
+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1) && ((SIZE) <= 4)) 
+
+#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \
+                                            ((MODE) == QSPI_MATCH_MODE_OR)) 
+
+#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 
+
+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 
+
+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFF) 
+/**
+* @}
+*/ 
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+  
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_QSPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rng.h

@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rng.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of RNG HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RNG_H
+#define __STM32L4xx_HAL_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RNG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup RNG_Exported_Types RNG Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  RNG HAL State Structure definition  
+  */ 
+typedef enum
+{
+  HAL_RNG_STATE_RESET     = 0x00,  /*!< RNG not yet initialized or disabled */
+  HAL_RNG_STATE_READY     = 0x01,  /*!< RNG initialized and ready for use   */
+  HAL_RNG_STATE_BUSY      = 0x02,  /*!< RNG internal process is ongoing     */ 
+  HAL_RNG_STATE_TIMEOUT   = 0x03,  /*!< RNG timeout state                   */
+  HAL_RNG_STATE_ERROR     = 0x04   /*!< RNG error state                     */
+    
+}HAL_RNG_StateTypeDef;
+
+/** 
+  * @brief  RNG Handle Structure definition  
+  */ 
+typedef struct
+{
+  RNG_TypeDef                 *Instance;  /*!< Register base address   */ 
+  
+  HAL_LockTypeDef             Lock;       /*!< RNG locking object      */
+  
+  __IO HAL_RNG_StateTypeDef   State;      /*!< RNG communication state */
+  
+  uint32_t               RandomNumber;    /*!< Last Generated RNG Data */
+  
+}RNG_HandleTypeDef;
+
+/** 
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Constants RNG Exported Constants
+  * @{
+  */
+
+/** @defgroup RNG_Interrupt_definition  RNG Interrupts Definition
+  * @{
+  */
+#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */
+#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */
+#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Flag_definition  RNG Flags Definition
+  * @{
+  */ 
+#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */
+#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */
+#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+  
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RNG_Exported_Macros RNG Exported Macros
+  * @{
+  */
+
+/** @brief Reset RNG handle state.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
+
+/**
+  * @brief  Enable the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)
+
+/**
+  * @brief  Disable the RNG peripheral.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
+
+/**
+  * @brief  Check whether the specified RNG flag is set or not.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __FLAG__: RNG flag
+  *          This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY:  Data ready                
+  *            @arg RNG_FLAG_CECS:  Clock error current status
+  *            @arg RNG_FLAG_SECS:  Seed error current status 
+  * @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
+
+
+/**
+  * @brief  Clear the selected RNG flag status.
+  * @param  __HANDLE__: RNG handle
+  * @param  __FLAG__: RNG flag to clear  
+  * @note   WARNING: This is a dummy macro for HAL code alignment,
+  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */
+
+
+
+/**
+  * @brief  Enable the RNG interrupt.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)
+    
+/**
+  * @brief  Disable the RNG interrupt.
+  * @param  __HANDLE__: RNG Handle
+  * @retval None
+  */
+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
+
+/**
+  * @brief  Check whether the specified RNG interrupt has occurred or not.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to check.
+  *         This parameter can be one of the following values:
+  *            @arg RNG_IT_DRDY: Data ready interrupt              
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))   
+
+/**
+  * @brief  Clear the RNG interrupt status flags.
+  * @param  __HANDLE__: RNG Handle
+  * @param  __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+  *          This parameter can be one of the following values:            
+  *            @arg RNG_IT_CEI: Clock error interrupt
+  *            @arg RNG_IT_SEI: Seed error interrupt
+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.          
+  * @retval None
+  */
+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))
+
+/**
+  * @}
+  */ 
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNG_Exported_Functions RNG Exported Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ******************************/
+/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */  
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);
+HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);
+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */ 
+
+/* Peripheral Control functions  ************************************************/
+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions
+  * @{
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng);    /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead    */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);
+
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);
+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit);
+/**
+  * @}
+  */ 
+
+/* Peripheral State functions  **************************************************/
+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions
+  * @{
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions prototypes ----------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RNG_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_rtc.h

@@ -0,0 +1,863 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rtc.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of RTC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_RTC_H
+#define __STM32L4xx_HAL_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RTC_Exported_Types RTC Exported Types
+  * @{
+  */
+/** 
+  * @brief  HAL State structures definition  
+  */
+typedef enum
+{
+  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */
+  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */
+  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */
+
+}HAL_RTCStateTypeDef;
+
+/** 
+  * @brief  RTC Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
+                                 This parameter can be a value of @ref RTC_Hour_Formats */
+
+  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */
+                               
+  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */
+
+  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
+                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
+
+  uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
+                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
+
+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */
+
+  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */
+
+  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
+
+  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */
+  
+  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.
+                                 This parameter corresponds to a time unit range between [0-1] Second
+                                 with [1 Sec / SecondFraction +1] granularity */
+ 
+  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content
+                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)
+                                 This parameter corresponds to a time unit range between [0-1] Second
+                                 with [1 Sec / SecondFraction +1] granularity.
+                                 This field will be used only by HAL_RTC_GetTime function */
+  
+  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.
+                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
+
+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
+                                 in CR register to store the operation.
+                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
+}RTC_TimeTypeDef;
+
+/** 
+  * @brief  RTC Date structure definition
+  */
+typedef struct
+{
+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
+                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
+                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t Date;     /*!< Specifies the RTC Date.
+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+
+  uint8_t Year;     /*!< Specifies the RTC Date Year.
+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
+
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition
+  */
+typedef struct
+{
+  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
+
+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+  
+  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
+                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */
+
+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+
+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
+                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
+
+  uint32_t Alarm;                /*!< Specifies the alarm .
+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */
+}RTC_AlarmTypeDef;
+
+/** 
+  * @brief  Time Handle Structure definition
+  */
+typedef struct
+{
+  RTC_TypeDef               *Instance;  /*!< Register base address    */
+
+  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */
+
+  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */
+
+  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
+
+}RTC_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RTC_Exported_Constants RTC Exported Constants
+  * @{
+  */
+
+/** @defgroup RTC_Hour_Formats RTC Hour Formats
+  * @{
+  */
+#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
+#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
+  * @{
+  */
+#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
+#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
+  * @{
+  */
+#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
+#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)RTC_OR_ALARMOUTTYPE)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
+  * @{
+  */
+#define RTC_OUTPUT_REMAP_NONE          ((uint32_t)0x00000000)
+#define RTC_OUTPUT_REMAP_POS1          ((uint32_t)RTC_OR_OUT_RMP)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
+  * @{
+  */
+#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
+#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
+  * @{
+  */
+#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
+#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
+#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
+  * @{
+  */
+#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
+#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
+  * @{
+  */
+#define RTC_FORMAT_BIN                  ((uint32_t)0x000000000)
+#define RTC_FORMAT_BCD                  ((uint32_t)0x000000001)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions
+  * @{
+  */
+
+/* Coded in BCD format */
+#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
+#define RTC_MONTH_MARCH                ((uint8_t)0x03)
+#define RTC_MONTH_APRIL                ((uint8_t)0x04)
+#define RTC_MONTH_MAY                  ((uint8_t)0x05)
+#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
+#define RTC_MONTH_JULY                 ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
+  * @{
+  */
+#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
+#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
+#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
+#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
+#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
+#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
+#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
+  * @{
+  */
+#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
+  * @{
+  */
+#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
+#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
+#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
+#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
+#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
+#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions
+  * @{
+  */
+#define RTC_ALARM_A                       RTC_CR_ALRAE
+#define RTC_ALARM_B                       RTC_CR_ALRBE
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
+  * @{
+  */
+#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked.
+                                                                        There is no comparison on sub seconds
+                                                                        for Alarm */
+#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm
+                                                                        comparison. Only SS[0] is compared.    */
+#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm
+                                                                        comparison. Only SS[1:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm
+                                                                        comparison. Only SS[2:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm
+                                                                        comparison. Only SS[3:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm
+                                                                        comparison. Only SS[4:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm
+                                                                        comparison. Only SS[5:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm
+                                                                        comparison. Only SS[6:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm
+                                                                        comparison. Only SS[7:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm
+                                                                        comparison. Only SS[8:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm
+                                                                        comparison. Only SS[9:0] are compared  */
+#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm
+                                                                        comparison. Only SS[10:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm
+                                                                        comparison. Only SS[11:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm
+                                                                        comparison. Only SS[12:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm
+                                                                        comparison. Only SS[13:0] are compared */
+#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match
+                                                                        to activate alarm. */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions
+  * @{
+  */
+#define RTC_IT_TS                         ((uint32_t)RTC_CR_TSIE)        /*!< Enable Timestamp Interrupt    */
+#define RTC_IT_WUT                        ((uint32_t)RTC_CR_WUTIE)       /*!< Enable Wakeup timer Interrupt */
+#define RTC_IT_ALRA                       ((uint32_t)RTC_CR_ALRAIE)      /*!< Enable Alarm A Interrupt      */
+#define RTC_IT_ALRB                       ((uint32_t)RTC_CR_ALRBIE)      /*!< Enable Alarm B Interrupt      */
+#define RTC_IT_TAMP                       ((uint32_t)RTC_TAMPCR_TAMPIE)  /*!< Enable all Tamper Interrupt   */
+#define RTC_IT_TAMP1                      ((uint32_t)RTC_TAMPCR_TAMP1IE) /*!< Enable Tamper 1 Interrupt     */
+#define RTC_IT_TAMP2                      ((uint32_t)RTC_TAMPCR_TAMP2IE) /*!< Enable Tamper 2 Interrupt     */
+#define RTC_IT_TAMP3                      ((uint32_t)RTC_TAMPCR_TAMP3IE) /*!< Enable Tamper 3 Interrupt     */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+  * @{
+  */
+#define RTC_FLAG_RECALPF                  ((uint32_t)RTC_ISR_RECALPF)
+#define RTC_FLAG_TAMP3F                   ((uint32_t)RTC_ISR_TAMP3F)
+#define RTC_FLAG_TAMP2F                   ((uint32_t)RTC_ISR_TAMP2F)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)RTC_ISR_TAMP1F)
+#define RTC_FLAG_TSOVF                    ((uint32_t)RTC_ISR_TSOVF)
+#define RTC_FLAG_TSF                      ((uint32_t)RTC_ISR_TSF)
+#define RTC_FLAG_ITSF                     ((uint32_t)RTC_ISR_ITSF)
+#define RTC_FLAG_WUTF                     ((uint32_t)RTC_ISR_WUTF)
+#define RTC_FLAG_ALRBF                    ((uint32_t)RTC_ISR_ALRBF)
+#define RTC_FLAG_ALRAF                    ((uint32_t)RTC_ISR_ALRAF)
+#define RTC_FLAG_INITF                    ((uint32_t)RTC_ISR_INITF)
+#define RTC_FLAG_RSF                      ((uint32_t)RTC_ISR_RSF)
+#define RTC_FLAG_INITS                    ((uint32_t)RTC_ISR_INITS)
+#define RTC_FLAG_SHPF                     ((uint32_t)RTC_ISR_SHPF)
+#define RTC_FLAG_WUTWF                    ((uint32_t)RTC_ISR_WUTWF)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)RTC_ISR_ALRBWF)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)RTC_ISR_ALRAWF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup RTC_Exported_Macros RTC Exported Macros
+  * @{
+  */
+
+/** @brief Reset RTC handle state.
+  * @param  __HANDLE__: RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
+
+/**
+  * @brief  Disable the write protection for RTC registers.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
+                        do{                                       \
+                            (__HANDLE__)->Instance->WPR = 0xCA;   \
+                            (__HANDLE__)->Instance->WPR = 0x53;   \
+                          } while(0)
+
+/**
+  * @brief  Enable the write protection for RTC registers.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
+                        do{                                       \
+                            (__HANDLE__)->Instance->WPR = 0xFF;   \
+                          } while(0)
+
+
+/**
+  * @brief  Enable the RTC ALARMA peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
+
+/**
+  * @brief  Disable the RTC ALARMA peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
+
+/**
+  * @brief  Enable the RTC ALARMB peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
+
+/**
+  * @brief  Disable the RTC ALARMB peripheral.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @retval None
+  */
+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
+
+/**
+  * @brief  Enable the RTC Alarm interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *             @arg RTC_IT_ALRA: Alarm A interrupt
+  *             @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the RTC Alarm interrupt.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+  *         This parameter can be any combination of the following values:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Get the selected RTC Alarm's flag status.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to check.
+  *         This parameter can be:
+  *            @arg RTC_FLAG_ALRAF
+  *            @arg RTC_FLAG_ALRBF
+  *            @arg RTC_FLAG_ALRAWF
+  *            @arg RTC_FLAG_ALRBWF
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Clear the RTC Alarm's pending flags.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __FLAG__: specifies the RTC Alarm Flag sources to clear.
+  *          This parameter can be:
+  *             @arg RTC_FLAG_ALRAF
+  *             @arg RTC_FLAG_ALRBF
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt is enabled or not.
+  * @param  __HANDLE__: specifies the RTC handle.
+  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg RTC_IT_ALRA: Alarm A interrupt
+  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != RESET) ? SET : RESET)
+
+/**
+  * @brief  Enable interrupt on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable interrupt on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable event on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable event on the RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+
+/**
+  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
+                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
+                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
+                                                           } while(0)
+
+/**
+  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.  
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
+                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
+                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
+                                                           } while(0)
+
+/**
+  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
+  * @retval Line Status.
+  */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief Clear the RTC Alarm associated Exti line flag.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1 = RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)
+
+/**
+  * @}
+  */
+
+/* Include RTC HAL Extended module */
+#include "stm32l4xx_hal_rtc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup RTC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
+void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group2
+  * @{
+  */
+/* RTC Time and Date functions ************************************************/
+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group3
+  * @{
+  */
+/* RTC Alarm functions ********************************************************/
+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
+void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
+void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+/**
+  * @}
+  */
+
+/** @addtogroup RTC_Exported_Functions_Group5
+  * @{
+  */
+/* Peripheral State functions *************************************************/
+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/ 
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RTC_Private_Constants RTC Private Constants
+  * @{
+  */
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFFU)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5FU)
+
+#define RTC_TIMEOUT_VALUE  1000
+  
+#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the RTC Alarm event */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RTC_Private_Macros RTC Private Macros
+  * @{
+  */
+
+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters
+  * @{
+  */ 
+
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
+                                        ((FORMAT) == RTC_HOURFORMAT_24))
+
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
+                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
+
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
+                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
+
+#define IS_RTC_OUTPUT_REMAP(REMAP)   (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
+                                      ((REMAP) == RTC_OUTPUT_REMAP_POS1))
+
+#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
+                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
+
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
+                                           ((OPERATION) == RTC_STOREOPERATION_SET))
+
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
+
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
+
+#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
+                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
+                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
+
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
+
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
+                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
+
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
+
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
+
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
+
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
+
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup RTC_Private_Functions
+  * @{
+  */
+
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+uint8_t            RTC_ByteToBcd2(uint8_t Value);
+uint8_t            RTC_Bcd2ToByte(uint8_t Value);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_RTC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_sd.h

@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_sd.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of SD HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SD_H
+#define __STM32L4xx_HAL_SD_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_ll_sdmmc.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SD SD
+  * @brief SD HAL module driver
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SD_Exported_Types SD Exported Types
+  * @{
+  */
+
+/** @defgroup SD_Exported_Types_Group1 SD Handle Structure definition   
+  * @{
+  */
+#define SD_InitTypeDef      SDMMC_InitTypeDef 
+#define SD_TypeDef          SDMMC_TypeDef
+
+typedef struct
+{
+  SD_TypeDef                   *Instance;        /*!< SDMMC register base address                     */
+  
+  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
+  
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
+  
+  uint32_t                     CardType;         /*!< SD card type                                   */
+  
+  uint32_t                     RCA;              /*!< SD relative card address                       */
+  
+  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
+  
+  uint32_t                     CID[4];           /*!< SD card identification number table            */
+  
+  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
+  
+  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
+  
+  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
+  
+  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
+  
+  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
+  
+  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
+  
+}SD_HandleTypeDef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group2 Card Specific Data: CSD Register 
+  * @{
+  */ 
+typedef struct
+{
+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
+  __IO uint8_t  Reserved1;            /*!< Reserved                              */
+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
+  __IO uint8_t  Reserved2;            /*!< Reserved                              */
+  __IO uint32_t DeviceSize;           /*!< Device Size                           */
+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
+  __IO uint8_t  Reserved3;            /*!< Reserved                              */
+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
+  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
+  __IO uint8_t  FileFormat;           /*!< File format                           */
+  __IO uint8_t  ECC;                  /*!< ECC code                              */
+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
+  __IO uint8_t  Reserved4;            /*!< Always 1                              */
+
+}HAL_SD_CSDTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group3 Card Identification Data: CID Register
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
+  __IO uint32_t ProdName1;       /*!< Product Name part1    */
+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
+  __IO uint8_t  ProdRev;         /*!< Product Revision      */
+  __IO uint32_t ProdSN;          /*!< Product Serial Number */
+  __IO uint8_t  Reserved1;       /*!< Reserved1             */
+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
+  __IO uint8_t  Reserved2;       /*!< Always 1              */
+
+}HAL_SD_CIDTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group4 SD Card Status returned by ACMD13 
+  * @{
+  */
+typedef struct
+{
+  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
+  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
+  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
+  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
+  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
+  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
+  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
+  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
+  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
+  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
+
+}HAL_SD_CardStatusTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group5 SD Card information structure 
+  * @{
+  */
+typedef struct
+{
+  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
+  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
+  uint64_t            CardCapacity;   /*!< Card capacity                          */
+  uint32_t            CardBlockSize;  /*!< Card block size                        */
+  uint16_t            RCA;            /*!< SD relative card address               */
+  uint8_t             CardType;       /*!< SD card type                           */
+
+}HAL_SD_CardInfoTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group6 SD Error status enumeration Structure definition 
+  * @{
+  */
+typedef enum
+{
+/** 
+  * @brief  SD specific error defines  
+  */   
+  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
+  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
+  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
+  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
+  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
+  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
+  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
+  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
+  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
+  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
+  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
+  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
+  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
+  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
+  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
+  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
+  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
+  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
+  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
+  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
+  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
+  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
+  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
+  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
+  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
+  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
+  SD_INVALID_VOLTRANGE               = (27),
+  SD_ADDR_OUT_OF_RANGE               = (28),
+  SD_SWITCH_ERROR                    = (29),
+  SD_SDMMC_DISABLED                  = (30),
+  SD_SDMMC_FUNCTION_BUSY             = (31),
+  SD_SDMMC_FUNCTION_FAILED           = (32),
+  SD_SDMMC_UNKNOWN_FUNCTION          = (33),
+
+/** 
+  * @brief  Standard error defines   
+  */ 
+  SD_INTERNAL_ERROR                  = (34),
+  SD_NOT_CONFIGURED                  = (35),
+  SD_REQUEST_PENDING                 = (36),
+  SD_REQUEST_NOT_APPLICABLE          = (37),
+  SD_INVALID_PARAMETER               = (38),
+  SD_UNSUPPORTED_FEATURE             = (39),
+  SD_UNSUPPORTED_HW                  = (40),
+  SD_ERROR                           = (41),
+  SD_OK                              = (0) 
+
+}HAL_SD_ErrorTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group7 SD Transfer state enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
+  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
+  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
+
+}HAL_SD_TransferStateTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group8 SD Card State enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
+  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
+  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
+  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
+  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
+  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
+  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
+  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
+  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
+
+}HAL_SD_CardStateTypedef;
+/** 
+  * @}
+  */
+
+/** @defgroup SD_Exported_Types_Group9 SD Operation enumeration structure
+  * @{
+  */   
+typedef enum
+{
+  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
+  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
+  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
+  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
+
+}HAL_SD_OperationTypedef;
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SD_Exported_Constants SD Exported Constants
+  * @{
+  */
+
+/** 
+  * @brief SD Commands Index 
+  */
+#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
+#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
+#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
+#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
+#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
+#define SD_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
+                                                                       operating condition register (OCR) content in the response on the CMD line.              */
+#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
+#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
+#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
+                                                                       and asks the card whether card supports voltage.                                         */
+#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
+#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
+#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
+#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
+#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
+#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
+#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
+#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
+                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
+                                                                       for SDHS and SDXC.                                                                       */
+#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
+                                                                       STOP_TRANSMISSION command.                                                               */
+#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
+#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
+#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
+#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
+                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
+#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
+#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
+#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
+#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
+#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
+#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
+#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
+#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
+#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
+                                                                       system set by switch function command (CMD6).                                            */
+#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
+                                                                       Reserved for each command system set by switch function command (CMD6).                  */
+#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
+#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
+#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
+                                                                       the SET_BLOCK_LEN command.                                                               */
+#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
+                                                                       than a standard command.                                                                 */
+#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
+                                                                       for general purpose/application specific commands.                                       */
+#define SD_CMD_NO_CMD                              ((uint8_t)64) 
+
+/** 
+  * @brief Following commands are SD Card Specific commands.
+  *        SDMMC_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
+                                                                       widths are given in SCR register.                                                          */
+#define SD_CMD_SD_APP_STATUS                       ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
+#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
+                                                                       32bit+CRC data block.                                                                      */
+#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
+                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
+#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
+#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
+#define SD_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
+#define SD_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
+
+/** 
+  * @brief Following commands are SD Card Specific security commands.
+  *        SD_CMD_APP_CMD should be sent before sending these commands. 
+  */
+#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
+#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
+#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
+#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
+
+/** 
+  * @brief Supported SD Memory Cards 
+  */
+#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
+#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
+#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
+#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
+#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
+#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
+#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
+#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SD_Exported_macros SD Exported Macros
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SD device.
+  * @retval None
+  */ 
+#define __HAL_SD_SDMMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SD device.
+  * @retval None
+  */
+#define __HAL_SD_SDMMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @retval None
+  */ 
+#define __HAL_SD_SDMMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @retval None
+  */
+#define __HAL_SD_SDMMC_DMA_DISABLE(__HANDLE__)  __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
+ 
+/**
+  * @brief  Enable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_SD_SDMMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SD device interrupt.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
+  * @retval None
+  */
+#define __HAL_SD_SDMMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified SD flag is set or not. 
+  * @param  __HANDLE__: SD Handle   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  * @retval The new state of SD FLAG (SET or RESET).
+  */
+#define __HAL_SD_SDMMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Clear the SD's pending flags.
+  * @param  __HANDLE__: SD Handle  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDIOIT:   SD I/O interrupt received
+  * @retval None
+  */
+#define __HAL_SD_SDMMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+  * @brief  Check whether the specified SD interrupt has occurred or not.
+  * @param  __HANDLE__: SD Handle   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval The new state of SD IT (SET or RESET).
+  */
+#define __HAL_SD_SDMMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+  * @brief  Clear the SD's interrupt pending bits.
+  * @param  __HANDLE__: SD Handle
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval None
+  */
+#define __HAL_SD_SDMMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+/**
+  * @}
+  */
+  
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup SD_Exported_Functions SD Exported Functions
+  * @{
+  */
+  
+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
+HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
+void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
+void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions
+  * @{
+  */
+/* Blocking mode: Polling */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
+
+/* Non-Blocking mode: Interrupt */
+void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
+void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
+
+/* Non-Blocking mode: DMA */
+HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
+HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
+/**
+  * @}
+  */
+  
+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
+HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
+HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
+HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/* Peripheral State functions  ************************************************/
+/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions
+  * @{
+  */
+HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
+HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
+HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+    
+/* Private types -------------------------------------------------------------*/
+/** @defgroup SD_Private_Types SD Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SD_Private_Defines SD Private Defines
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+          
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup SD_Private_Variables SD Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup SD_Private_Constants SD Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup SD_Private_Macros SD Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup SD_Private_Functions SD Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_SD_H */ 
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi.h

@@ -0,0 +1,696 @@
+ /**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of SPI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SPI_H
+#define __STM32L4xx_HAL_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Types SPI Exported Types
+  * @{
+  */
+
+/**
+  * @brief  SPI Configuration Structure definition
+  */
+typedef struct
+{
+  uint32_t Mode;                /*!< Specifies the SPI operating mode.
+                                     This parameter can be a value of @ref SPI_Mode */
+
+  uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
+                                     This parameter can be a value of @ref SPI_Direction */
+
+  uint32_t DataSize;            /*!< Specifies the SPI data size.
+                                     This parameter can be a value of @ref SPI_Data_Size */
+
+  uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
+                                     This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
+                                     This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                     hardware (NSS pin) or by software using the SSI bit.
+                                     This parameter can be a value of @ref SPI_Slave_Select_management */
+
+  uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                     used to configure the transmit and receive SCK clock.
+                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                     @note The communication clock is derived from the master
+                                     clock. The slave clock does not need to be set. */
+
+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                     This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not .
+                                     This parameter can be a value of @ref SPI_TI_mode */
+
+  uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
+                                     This parameter can be a value of @ref SPI_CRC_Calculation */
+
+  uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
+
+  uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
+                                     CRC Length is only used with Data8 and Data16, not other data size
+                                     This parameter can be a value of @ref SPI_CRC_length */
+
+  uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
+                                     This parameter can be a value of @ref SPI_NSSP_Mode
+                                     This mode is activated by the NSSP bit in the SPIx_CR2 register and
+                                     it takes effect only if the SPI interface is configured as Motorola SPI
+                                     master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
+                                     CPOL setting is ignored).. */
+} SPI_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_SPI_STATE_RESET      = 0x00,    /*!< Peripheral not Initialized                         */
+  HAL_SPI_STATE_READY      = 0x01,    /*!< Peripheral Initialized and ready for use           */
+  HAL_SPI_STATE_BUSY       = 0x02,    /*!< an internal process is ongoing                     */
+  HAL_SPI_STATE_BUSY_TX    = 0x03,    /*!< Data Transmission process is ongoing               */
+  HAL_SPI_STATE_BUSY_RX    = 0x04,    /*!< Data Reception process is ongoing                  */
+  HAL_SPI_STATE_BUSY_TX_RX = 0x05,    /*!< Data Transmission and Reception process is ongoing*/
+  HAL_SPI_STATE_ERROR      = 0x06     /*!< SPI error state                                   */
+}HAL_SPI_StateTypeDef;
+
+/**
+  * @brief  SPI handle Structure definition
+  */
+typedef struct __SPI_HandleTypeDef
+{
+  SPI_TypeDef             *Instance;      /* SPI registers base address     */
+
+  SPI_InitTypeDef         Init;           /* SPI communication parameters   */
+
+  uint8_t                 *pTxBuffPtr;    /* Pointer to SPI Tx transfer Buffer */
+
+  uint16_t                TxXferSize;     /* SPI Tx Transfer size */
+
+  uint16_t                TxXferCount;    /* SPI Tx Transfer Counter */
+
+  uint8_t                 *pRxBuffPtr;    /* Pointer to SPI Rx transfer Buffer */
+
+  uint16_t                RxXferSize;     /* SPI Rx Transfer size */
+
+  uint16_t                RxXferCount;    /* SPI Rx Transfer Counter */
+
+  uint32_t                CRCSize;        /* SPI CRC size used for the transfer */
+
+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Rx IRQ handler   */
+
+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /* function pointer on Tx IRQ handler   */
+
+  DMA_HandleTypeDef       *hdmatx;        /* SPI Tx DMA Handle parameters   */
+
+  DMA_HandleTypeDef       *hdmarx;        /* SPI Rx DMA Handle parameters   */
+
+  HAL_LockTypeDef         Lock;           /* Locking object                 */
+
+  HAL_SPI_StateTypeDef    State;          /* SPI communication state        */
+
+  uint32_t                ErrorCode;      /* SPI Error code                 */
+
+}SPI_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants SPI Exported Constants
+  * @{
+  */
+
+/** @defgroup SPI_Error_Code SPI Error Code
+  * @{
+  */
+#define HAL_SPI_ERROR_NONE   (uint32_t)0x00000000  /*!< No error                          */
+#define HAL_SPI_ERROR_MODF   (uint32_t)0x00000001  /*!< MODF error                        */
+#define HAL_SPI_ERROR_CRC    (uint32_t)0x00000002  /*!< CRC error                         */
+#define HAL_SPI_ERROR_OVR    (uint32_t)0x00000004  /*!< OVR error                         */
+#define HAL_SPI_ERROR_FRE    (uint32_t)0x00000008  /*!< FRE error                         */
+#define HAL_SPI_ERROR_DMA    (uint32_t)0x00000010  /*!< DMA transfer error                */
+#define HAL_SPI_ERROR_FLAG   (uint32_t)0x00000020  /*!< Error on BSY/TXE/FTLVL/FRLVL Flag */
+#define HAL_SPI_ERROR_UNKNOW (uint32_t)0x00000040  /*!< Unknown error                     */
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_Mode SPI Mode
+  * @{
+  */
+#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
+#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Direction SPI Direction Mode
+  * @{
+  */
+#define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000)
+#define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
+#define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Data_Size SPI Data Size
+  * @{
+  */
+#define SPI_DATASIZE_4BIT               ((uint32_t)0x0300)
+#define SPI_DATASIZE_5BIT               ((uint32_t)0x0400)
+#define SPI_DATASIZE_6BIT               ((uint32_t)0x0500)
+#define SPI_DATASIZE_7BIT               ((uint32_t)0x0600)
+#define SPI_DATASIZE_8BIT               ((uint32_t)0x0700)
+#define SPI_DATASIZE_9BIT               ((uint32_t)0x0800)
+#define SPI_DATASIZE_10BIT              ((uint32_t)0x0900)
+#define SPI_DATASIZE_11BIT              ((uint32_t)0x0A00)
+#define SPI_DATASIZE_12BIT              ((uint32_t)0x0B00)
+#define SPI_DATASIZE_13BIT              ((uint32_t)0x0C00)
+#define SPI_DATASIZE_14BIT              ((uint32_t)0x0D00)
+#define SPI_DATASIZE_15BIT              ((uint32_t)0x0E00)
+#define SPI_DATASIZE_16BIT              ((uint32_t)0x0F00)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
+  * @{
+  */
+#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
+#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase SPI Clock Phase
+  * @{
+  */
+#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
+#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management SPI Slave Select management
+  * @{
+  */
+#define SPI_NSS_SOFT                    SPI_CR1_SSM
+#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
+#define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
+  * @{
+  */
+#define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
+#define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
+  * @{
+  */
+#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
+#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008)
+#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010)
+#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018)
+#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020)
+#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028)
+#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030)
+#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
+  * @{
+  */
+#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
+#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
+/**
+  * @}
+  */
+
+/** @defgroup SPI_TI_mode SPI TI mode
+  * @{
+  */
+#define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000)
+#define SPI_TIMODE_ENABLE               SPI_CR2_FRF
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
+  * @{
+  */
+#define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000)
+#define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_length SPI CRC Length
+  * @{
+  * This parameter can be one of the following values:
+  *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
+  *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
+  *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
+  */
+#define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000)
+#define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001)
+#define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
+  * @{
+  * This parameter can be one of the following values:
+  *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
+  *          RXNE event is generated if the FIFO
+  *          level is greater or equal to 1/2(16-bits).
+  *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
+  *          level is greater or equal to 1/4(8 bits). */
+#define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
+#define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
+  * @brief SPI Interrupt definition
+  *        Elements values convention: 0xXXXXXXXX
+  *           - XXXXXXXX  : Interrupt control mask
+  * @{
+  */
+#define SPI_IT_TXE                      SPI_CR2_TXEIE
+#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
+#define SPI_IT_ERR                      SPI_CR2_ERRIE
+/**
+  * @}
+  */
+
+
+/** @defgroup SPI_Flag_definition SPI Flag definition
+  * @brief Flag definition
+  *        Elements values convention: 0xXXXXYYYY
+  *           - XXXX  : Flag register Index
+  *           - YYYY  : Flag mask
+  * @{
+  */
+#define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag */
+#define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag */
+#define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag */
+#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag */
+#define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag */
+#define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag */
+#define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
+#define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level */
+#define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
+  * @{
+  */
+#define SPI_FTLVL_EMPTY           ((uint32_t)0x0000)
+#define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x0800)
+#define SPI_FTLVL_HALF_FULL       ((uint32_t)0x1000)
+#define SPI_FTLVL_FULL            ((uint32_t)0x1800)
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
+  * @{
+  */
+#define SPI_FRLVL_EMPTY           ((uint32_t)0x0000)
+#define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x0200)
+#define SPI_FRLVL_HALF_FULL       ((uint32_t)0x0400)
+#define SPI_FRLVL_FULL            ((uint32_t)0x0600)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup SPI_Exported_Macros SPI Exported Macros
+  * @{
+  */
+
+/** @brief  Reset SPI handle state.
+  * @param  __HANDLE__: SPI handle.
+  * @retval None
+  */
+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
+
+/** @brief  Enable or disable the specified SPI interrupts.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
+
+/** @brief  Check whether the specified SPI interrupt source is enabled or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
+  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
+  *            @arg SPI_IT_ERR: Error interrupt enable
+  * @retval The new state of __IT__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Check whether the specified SPI flag is set or not.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @param  __FLAG__: specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
+  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
+  *            @arg SPI_FLAG_CRCERR: CRC error flag
+  *            @arg SPI_FLAG_MODF: Mode fault flag
+  *            @arg SPI_FLAG_OVR: Overrun flag
+  *            @arg SPI_FLAG_BSY: Busy flag
+  *            @arg SPI_FLAG_FRE: Frame format error flag
+  *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
+  *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the SPI CRCERR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
+
+/** @brief  Clear the SPI MODF pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  *
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)        \
+   do{                                              \
+     __IO uint32_t tmpreg;                          \
+     tmpreg = (__HANDLE__)->Instance->SR;           \
+     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
+     UNUSED(tmpreg);                                \
+   } while(0)
+
+/** @brief  Clear the SPI OVR pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  *
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)         \
+   do{                                              \
+     __IO uint32_t tmpreg;                          \
+     tmpreg = (__HANDLE__)->Instance->DR;           \
+     tmpreg = (__HANDLE__)->Instance->SR;           \
+     UNUSED(tmpreg);                                \
+   } while(0)
+
+/** @brief  Clear the SPI FRE pending flag.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  *
+  * @retval None
+  */
+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)         \
+   do{                                              \
+     __IO uint32_t tmpreg;                          \
+     tmpreg = (__HANDLE__)->Instance->SR;           \
+     UNUSED(tmpreg);                                \
+   } while(0)
+
+/** @brief  Enable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
+
+/** @brief  Disable the SPI peripheral.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
+
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup SPI_Private_Macros   SPI Private Macros
+  * @{
+  */
+
+/** @brief  Set the SPI transmit-only mode.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
+
+/** @brief  Set the SPI receive-only mode.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
+
+/** @brief  Reset the CRC calculation of the SPI.
+  * @param  __HANDLE__: specifies the SPI Handle.
+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
+  * @retval None
+  */
+#define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
+                                     (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
+
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
+                           ((MODE) == SPI_MODE_MASTER))
+
+#define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES) || \
+                                  ((MODE) == SPI_DIRECTION_2LINES_RXONLY) ||\
+                                  ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
+
+#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \
+                                                 ((MODE) == SPI_DIRECTION_1LINE))
+
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_15BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_14BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_13BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_12BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_11BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_10BIT) || \
+                                   ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
+                                   ((DATASIZE) == SPI_DATASIZE_4BIT))
+
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
+                           ((CPOL) == SPI_POLARITY_HIGH))
+
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
+                           ((CPHA) == SPI_PHASE_2EDGE))
+
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
+                         ((NSS) == SPI_NSS_HARD_INPUT) || \
+                         ((NSS) == SPI_NSS_HARD_OUTPUT))
+
+#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
+                           ((NSSP) == SPI_NSS_PULSE_DISABLE))
+
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
+                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
+
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
+                               ((BIT) == SPI_FIRSTBIT_LSB))
+
+#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
+                             ((MODE) == SPI_TIMODE_ENABLE))
+
+#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
+                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
+
+#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
+                                   ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
+                                   ((LENGTH) == SPI_CRC_LENGTH_16BIT))
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
+
+
+/**
+  * @}
+  */
+
+/* Include SPI HAL Extended module */
+#include "stm32l4xx_hal_spi_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPI_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/** @addtogroup SPI_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+/** @addtogroup SPI_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
+
+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/* Peripheral State and Error functions ***************************************/
+/** @addtogroup SPI_Exported_Functions_Group3
+  * @{
+  */
+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
+uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SPI_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_spi_ex.h

@@ -0,0 +1,93 @@
+ /**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of SPI HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_SPI_EX_H
+#define __STM32L4xx_HAL_SPI_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup SPIEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SPIEx_Exported_Functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+/* IO operation functions *****************************************************/
+/** @addtogroup SPIEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_SPI_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_tim_ex.h

@@ -0,0 +1,396 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_tim_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of TIM HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_TIM_EX_H
+#define __STM32L4xx_HAL_TIM_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup TIMEx
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types
+  * @{
+  */
+
+/** 
+  * @brief  TIM Hall sensor Configuration Structure definition  
+  */
+
+typedef struct
+{
+                                  
+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+                                                                   
+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.
+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+                                  
+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.
+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */  
+
+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */                              
+} TIM_HallSensor_InitTypeDef;
+
+/** 
+  * @brief  TIM Break/Break2 input configuration   
+  */
+typedef struct {
+  uint32_t Source;         /*!< Specifies the source of the timer break input.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */
+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+  uint32_t Polarity;       /*!< Specifies the break input source polarity.
+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+                                Not relevant when analog watchdog output of the DFSDM used as break input source */
+} TIMEx_BreakInputConfigTypeDef;
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/ 
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup TIMEx_Remap TIM  Extended Remapping
+  * @{
+  */
+#define TIM_TIM1_ETR_ADC1_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ETR_ADC1_AWD1      (TIM1_OR1_ETR_ADC1_RMP_0)                             /* !< TIM1_ETR is connected to ADC1 AWD1 */
+#define TIM_TIM1_ETR_ADC1_AWD2      (TIM1_OR1_ETR_ADC1_RMP_1)                             /* !< TIM1_ETR is connected to ADC1 AWD2 */
+#define TIM_TIM1_ETR_ADC1_AWD3      (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_ETR_ADC1_RMP_0)   /* !< TIM1_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM1_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM1_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM1_ETR_ADC3_AWD1      (TIM1_OR1_ETR_ADC3_RMP_0)                             /* !< TIM1_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM1_ETR_ADC3_AWD2      (TIM1_OR1_ETR_ADC3_RMP_1)                             /* !< TIM1_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM1_ETR_ADC3_AWD3      (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_ETR_ADC3_RMP_0)   /* !< TIM1_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM1_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM1 TI1 is connected to GPIO */
+#define TIM_TIM1_TI1_COMP1          (TIM1_OR1_TI1_RMP)                                    /* !< TIM1 TI1 is connected to COMP1 */
+#define TIM_TIM1_ETR_COMP1          (TIM1_OR2_ETRSEL_0)                                   /* !< TIM1_ETR is connected to COMP1 output */
+#define TIM_TIM1_ETR_COMP2          (TIM1_OR2_ETRSEL_1)                                   /* !< TIM1_ETR is connected to COMP2 output */
+#define TIM_TIM2_ITR1_TIM8_TRGO     ((uint32_t)(0x00000000))                              /* !< TIM2_ITR1 is connected to TIM8_TRGO */
+#define TIM_TIM2_ITR1_OTG_FS_SOF    (TIM2_OR1_ITR1_RMP)                                   /* !< TIM2_ITR1 is connected to OTG_FS SOF */
+#define TIM_TIM2_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2_ETR is connected to GPIO */
+#define TIM_TIM2_ETR_LSE            (TIM2_OR1_ETR1_RMP)                                   /* !< TIM2_ETR is connected to LSE */
+#define TIM_TIM2_ETR_COMP1          (TIM2_OR2_ETRSEL_0)                                   /* !< TIM2_ETR is connected to COMP1 output */
+#define TIM_TIM2_ETR_COMP2          (TIM2_OR2_ETRSEL_1)                                   /* !< TIM2_ETR is connected to COMP2 output */
+#define TIM_TIM2_TI4_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM2 TI4 is connected to GPIO */
+#define TIM_TIM2_TI4_COMP1          (TIM2_OR1_TI4_RMP_0)                                  /* !< TIM2 TI4 is connected to COMP1 output */
+#define TIM_TIM2_TI4_COMP2          (TIM2_OR1_TI4_RMP_1)                                  /* !< TIM2 TI4 is connected to COMP2 output */
+#define TIM_TIM2_TI4_COMP1_COMP2    (TIM2_OR1_TI4_RMP_1| TIM2_OR1_TI4_RMP_0)              /* !< TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output2 */
+#define TIM_TIM3_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3 TI1 is connected to GPIO */
+#define TIM_TIM3_TI1_COMP1          (TIM3_OR1_TI1_RMP_0)                                  /* !< TIM3 TI1 is connected to COMP1 output */
+#define TIM_TIM3_TI1_COMP2          (TIM3_OR1_TI1_RMP_1)                                  /* !< TIM3 TI1 is connected to COMP2 output */
+#define TIM_TIM3_TI1_COMP1_COMP2    (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_TI1_RMP_0)             /* !< TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output2 */
+#define TIM_TIM3_ETR_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM3_ETR is connected to GPIO */
+#define TIM_TIM3_ETR_COMP1          (TIM3_OR2_ETRSEL_0)                                   /* !< TIM3_ETR is connected to COMP1 output */
+#define TIM_TIM8_ETR_ADC2_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM8_ETR_ADC2_AWD1      (TIM8_OR1_ETR_ADC2_RMP_0)                             /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2      (TIM8_OR1_ETR_ADC2_RMP_1)                             /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3      (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_ETR_ADC2_RMP_0)   /* !< TIM8_ETR is connected to ADC2 AWD3 */
+#define TIM_TIM8_ETR_ADC3_NONE      ((uint32_t)(0x00000000))                              /* !< TIM8_ETR is not connected to any AWD (analog watchdog)*/
+#define TIM_TIM8_ETR_ADC3_AWD1      (TIM8_OR1_ETR_ADC3_RMP_0)                             /* !< TIM8_ETR is connected to ADC3 AWD1 */
+#define TIM_TIM8_ETR_ADC3_AWD2      (TIM8_OR1_ETR_ADC3_RMP_1)                             /* !< TIM8_ETR is connected to ADC3 AWD2 */
+#define TIM_TIM8_ETR_ADC3_AWD3      (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_ETR_ADC3_RMP_0)   /* !< TIM8_ETR is connected to ADC3 AWD3 */
+#define TIM_TIM8_TI1_GPIO           ((uint32_t)(0x00000000))                              /* !< TIM8 TI1 is connected to GPIO */
+#define TIM_TIM8_TI1_COMP2          (TIM8_OR1_TI1_RMP)                                    /* !< TIM8 TI1 is connected to COMP1 */
+#define TIM_TIM8_ETR_COMP1          (TIM8_OR2_ETRSEL_0)                                   /* !< TIM8_ETR is connected to COMP1 output */
+#define TIM_TIM8_ETR_COMP2          (TIM8_OR2_ETRSEL_1)                                   /* !< TIM8_ETR is connected to COMP2 output */
+#define TIM_TIM15_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM15 TI1 is connected to GPIO */
+#define TIM_TIM15_TI1_LSE           (TIM15_OR1_TI1_RMP)                                   /* !< TIM15 TI1 is connected to LSE */
+#define TIM_TIM15_ENCODERMODE_NONE  ((uint32_t)(0x00000000))                              /* !< No redirection */
+#define TIM_TIM15_ENCODERMODE_TIM2  (TIM15_OR1_ENCODER_MODE_0)                            /* !< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#define TIM_TIM15_ENCODERMODE_TIM3  (TIM15_OR1_ENCODER_MODE_1)                            /* !< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#define TIM_TIM15_ENCODERMODE_TIM4  (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_ENCODER_MODE_0) /* !< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */
+#define TIM_TIM16_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM16 TI1 is connected to GPIO */
+#define TIM_TIM16_TI1_LSI           (TIM16_OR1_TI1_RMP_0)                                 /* !< TIM16 TI1 is connected to LSI */
+#define TIM_TIM16_TI1_LSE           (TIM16_OR1_TI1_RMP_1)                                 /* !< TIM16 TI1 is connected to LSE */
+#define TIM_TIM16_TI1_RTC           (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0)           /* !< TIM16 TI1 is connected to RTC wakeup interrupt */
+#define TIM_TIM17_TI1_GPIO          ((uint32_t)(0x00000000))                              /* !< TIM17 TI1 is connected to GPIO */
+#define TIM_TIM17_TI1_MSI           (TIM17_OR1_TI1_RMP_0)                                 /* !< TIM17 TI1 is connected to MSI */
+#define TIM_TIM17_TI1_HSE_32        (TIM17_OR1_TI1_RMP_1)                                 /* !< TIM17 TI1 is connected to HSE div 32 */
+#define TIM_TIM17_TI1_MCO           (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_TI1_RMP_0)           /* !< TIM17 TI1 is connected to MCO */
+/**
+  * @}
+  */ 
+
+/** @defgroup TIMEx_Break_Input TIM  Extended Break input
+  * @{
+  */
+#define TIM_BREAKINPUT_BRK     ((uint32_t)(0x00000001)) /* !< Timer break input  */
+#define TIM_BREAKINPUT_BRK2    ((uint32_t)(0x00000002)) /* !< Timer break2 input */
+/**
+  * @}
+  */ 
+
+/** @defgroup TIMEx_Break_Input_Source TIM  Extended Break input source
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_BKIN     ((uint32_t)(0x00000001)) /* !< An external source (GPIO) is connected to the BKIN pin  */
+#define TIM_BREAKINPUTSOURCE_COMP1    ((uint32_t)(0x00000002)) /* !< The COMP1 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_COMP2    ((uint32_t)(0x00000004)) /* !< The COMP2 output is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM    ((uint32_t)(0x00000008)) /* !< The analog watchdog output of the DFSDM peripheral is connected to the break input */
+/**
+  * @}
+  */ 
+
+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_DISABLE     ((uint32_t)(0x00000000)) /* !< Break input source is disabled */
+#define TIM_BREAKINPUTSOURCE_ENABLE      ((uint32_t)(0x00000001)) /* !< Break input source is enabled */
+/**
+  * @}
+  */ 
+
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM  Extended Break input polarity
+  * @{
+  */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     ((uint32_t)(0x00000001)) /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
+/**
+  * @}
+  */ 
+   
+/**
+  * @}
+  */ 
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros
+  * @{
+  */  
+
+/**
+  * @}
+  */ 
+/* End of exported macro -----------------------------------------------------*/
+
+/* Private macro -------------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros
+  * @{
+  */  
+#define IS_TIM_REMAP(__REMAP__)    (((__REMAP__) <= (uint32_t)0x0001C01F))
+
+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \
+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
+
+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \
+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM))
+
+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \
+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \
+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+/**
+  * @}
+  */ 
+/* End of private macro ------------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 
+ *  @brief    Timer Hall Sensor functions
+ * @{
+ */
+/*  Timer Hall Sensor functions  **********************************************/
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
+
+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);
+
+ /* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
+ *  @brief   Timer Complementary Output Compare functions
+ * @{
+ */
+/*  Timer Complementary Output Compare functions  *****************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
+ *  @brief    Timer Complementary PWM functions
+ * @{
+ */
+/*  Timer Complementary PWM functions  ****************************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
+ *  @brief    Timer Complementary One Pulse functions
+ * @{
+ */
+/*  Timer Complementary One Pulse functions  **********************************/
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+
+/* Non-Blocking mode: Interrupt */
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
+ *  @brief    Peripheral Control functions
+ * @{
+ */
+/* Extended Control functions  ************************************************/
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger, uint32_t  CommutationSource);
+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
+
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 
+  * @brief    Extended Callbacks functions
+  * @{
+  */
+/* Extended Callback **********************************************************/
+void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim);
+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 
+  * @brief    Extended Peripheral State functions
+  * @{
+  */
+/* Extended Peripheral State functions  ***************************************/
+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+/* End of exported functions -------------------------------------------------*/
+
+/* Private functions----------------------------------------------------------*/
+/** @defgroup TIMEx_Private_Functions TIMEx Private Functions
+* @{
+*/
+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);
+/**
+* @}
+*/ 
+/* End of private functions --------------------------------------------------*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_HAL_TIM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_hal_uart_ex.h

@@ -0,0 +1,372 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_UART_EX_H
+#define __STM32L4xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activat the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UART Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)     /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UART Extended WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B              ((uint32_t)0x00000000)       /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B              ((uint32_t)USART_CR2_ADDM7)  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/* IO operation functions *****************************************************/
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @param  __CLOCKSOURCE__: output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
+       {                                                      \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
+       {                                                      \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
+       {                                                      \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
+       {                                                      \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
+       {                                                      \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+       switch(__HAL_RCC_GET_LPUART1_SOURCE())                 \
+       {                                                      \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+       }                                                      \
+    }                                                         \
+  } while(0)
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__: specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x01FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x00FF ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+  }                                                                   \
+  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
+  {                                                                   \
+     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x007F ;                                 \
+     }                                                                \
+     else                                                             \
+     {                                                                \
+        (__HANDLE__)->Mask = 0x003F ;                                 \
+     }                                                                \
+  }                                                                   \
+} while(0)
+
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__: UART frame length. 
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__: UART wake-up address length. 
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_UART_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_sdmmc.h

@@ -0,0 +1,804 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_sdmmc.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of low layer SDMMC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_SDMMC_H
+#define __STM32L4xx_LL_SDMMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_Driver
+  * @{
+  */
+
+/** @addtogroup SDMMC_LL
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
+  * @{
+  */
+  
+/** 
+  * @brief  SDMMC Configuration Structure definition  
+  */
+typedef struct
+{
+  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
+
+  uint32_t ClockBypass;          /*!< Specifies whether the SDMMC Clock divider bypass is
+                                      enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
+
+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or
+                                      disabled when the bus is idle.
+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
+
+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.
+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
+
+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
+
+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.
+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
+  
+}SDMMC_InitTypeDef;
+  
+
+/** 
+  * @brief  SDMMC Command Control structure 
+  */
+typedef struct                                                                                            
+{
+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent
+                                     to a card as part of a command message. If a command
+                                     contains an argument, it must be loaded into this register
+                                     before writing the command to the command register.              */
+
+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 
+                                     Max_Data = 64                                                    */
+
+  uint32_t Response;            /*!< Specifies the SDMMC response type.
+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
+
+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is 
+                                     enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
+
+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
+}SDMMC_CmdInitTypeDef;
+
+
+/** 
+  * @brief  SDMMC Data Control structure 
+  */
+typedef struct
+{
+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
+
+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
+ 
+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
+ 
+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
+ 
+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
+ 
+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
+}SDMMC_DataInitTypeDef;
+
+/**
+  * @}
+  */
+  
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
+  * @{
+  */
+
+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
+  * @{
+  */
+#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
+#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE
+
+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
+                                  ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
+  * @{
+  */
+#define SDMMC_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
+#define SDMMC_CLOCK_BYPASS_ENABLE              SDMMC_CLKCR_BYPASS   
+
+#define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
+                                      ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
+  * @{
+  */
+#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
+#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV
+
+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
+                                        ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Bus_Wide Bus Width
+  * @{
+  */
+#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000)
+#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0
+#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1
+
+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
+                                ((WIDE) == SDMMC_BUS_WIDE_4B) || \
+                                ((WIDE) == SDMMC_BUS_WIDE_8B))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
+  * @{
+  */
+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN
+
+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
+                                                ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDMMC_LL_Clock_Division Clock Division
+  * @{
+  */
+#define IS_SDMMC_CLKDIV(DIV)   ((DIV) <= 0xFF)
+/**
+  * @}
+  */  
+    
+/** @defgroup SDMMC_LL_Command_Index Command Index
+  * @{
+  */
+#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Response_Type Response Type
+  * @{
+  */
+#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000)
+#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0
+#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP
+
+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \
+                                    ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
+                                    ((RESPONSE) == SDMMC_RESPONSE_LONG))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
+  * @{
+  */
+#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000)
+#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT 
+#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND
+
+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
+                            ((WAIT) == SDMMC_WAIT_IT) || \
+                            ((WAIT) == SDMMC_WAIT_PEND))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_CPSM_State CPSM State
+  * @{
+  */
+#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000)
+#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN
+
+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
+                            ((CPSM) == SDMMC_CPSM_ENABLE))
+/**
+  * @}
+  */  
+
+/** @defgroup SDMMC_LL_Response_Registers Response Register
+  * @{
+  */
+#define SDMMC_RESP1                          ((uint32_t)0x00000000)
+#define SDMMC_RESP2                          ((uint32_t)0x00000004)
+#define SDMMC_RESP3                          ((uint32_t)0x00000008)
+#define SDMMC_RESP4                          ((uint32_t)0x0000000C)
+
+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
+                            ((RESP) == SDMMC_RESP2) || \
+                            ((RESP) == SDMMC_RESP3) || \
+                            ((RESP) == SDMMC_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Length Data Lenght
+  * @{
+  */
+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
+  * @{
+  */
+#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
+#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0
+#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1
+#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
+#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2
+#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
+#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3
+#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 
+#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
+
+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
+                                  ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
+  * @{
+  */
+#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
+#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR
+
+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
+                                   ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
+  * @{
+  */
+#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
+#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE
+
+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
+                                     ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_DPSM_State DPSM State
+  * @{
+  */
+#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000)
+#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN
+
+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
+                            ((DPSM) == SDMMC_DPSM_ENABLE))
+/**
+  * @}
+  */
+  
+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
+  * @{
+  */
+#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000)
+#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)
+
+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
+                                     ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
+/**
+  * @}
+  */  
+
+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
+  * @{
+  */
+#define SDMMC_IT_CCRCFAIL                    SDMMC_STA_CCRCFAIL
+#define SDMMC_IT_DCRCFAIL                    SDMMC_STA_DCRCFAIL
+#define SDMMC_IT_CTIMEOUT                    SDMMC_STA_CTIMEOUT
+#define SDMMC_IT_DTIMEOUT                    SDMMC_STA_DTIMEOUT
+#define SDMMC_IT_TXUNDERR                    SDMMC_STA_TXUNDERR
+#define SDMMC_IT_RXOVERR                     SDMMC_STA_RXOVERR
+#define SDMMC_IT_CMDREND                     SDMMC_STA_CMDREND
+#define SDMMC_IT_CMDSENT                     SDMMC_STA_CMDSENT
+#define SDMMC_IT_DATAEND                     SDMMC_STA_DATAEND
+#define SDMMC_IT_DBCKEND                     SDMMC_STA_DBCKEND
+#define SDMMC_IT_CMDACT                      SDMMC_STA_CMDACT
+#define SDMMC_IT_TXACT                       SDMMC_STA_TXACT
+#define SDMMC_IT_RXACT                       SDMMC_STA_RXACT
+#define SDMMC_IT_TXFIFOHE                    SDMMC_STA_TXFIFOHE
+#define SDMMC_IT_RXFIFOHF                    SDMMC_STA_RXFIFOHF
+#define SDMMC_IT_TXFIFOF                     SDMMC_STA_TXFIFOF
+#define SDMMC_IT_RXFIFOF                     SDMMC_STA_RXFIFOF
+#define SDMMC_IT_TXFIFOE                     SDMMC_STA_TXFIFOE
+#define SDMMC_IT_RXFIFOE                     SDMMC_STA_RXFIFOE
+#define SDMMC_IT_TXDAVL                      SDMMC_STA_TXDAVL
+#define SDMMC_IT_RXDAVL                      SDMMC_STA_RXDAVL
+#define SDMMC_IT_SDIOIT                      SDMMC_STA_SDIOIT
+/**
+  * @}
+  */ 
+
+/** @defgroup SDMMC_LL_Flags Flags
+  * @{
+  */
+#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL
+#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL
+#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT
+#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT
+#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR
+#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR
+#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND
+#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT
+#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND
+#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND
+#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CMDACT
+#define SDMMC_FLAG_TXACT                     SDMMC_STA_TXACT
+#define SDMMC_FLAG_RXACT                     SDMMC_STA_RXACT
+#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE
+#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF
+#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF
+#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF
+#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE
+#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE
+#define SDMMC_FLAG_TXDAVL                    SDMMC_STA_TXDAVL
+#define SDMMC_FLAG_RXDAVL                    SDMMC_STA_RXDAVL
+#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
+  * @{
+  */
+  
+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
+  * @brief SDMMC_LL registers bit address in the alias region
+  * @{
+  */
+/* ---------------------- SDMMC registers bit mask --------------------------- */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */ 
+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\
+                                             SDMMC_CLKCR_BYPASS  | SDMMC_CLKCR_WIDBUS |\
+                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
+
+/* --- DCTRL Register ---*/
+/* SDMMC DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\
+                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
+                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\
+                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_SDIOSUSPEND))
+
+/* SDMMC Intialization Frequency (400KHz max) */
+#define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
+
+/* SDMMC Data Transfer Frequency (25MHz max) */
+#define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
+
+/**
+  * @}
+  */
+
+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
+ *  @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+ 
+/**
+  * @brief  Enable the SDMMC device.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */ 
+#define __SDMMC_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
+
+/**
+  * @brief  Disable the SDMMC device.
+  * @param  __INSTANCE__: SDMMC Instance  
+  * @retval None
+  */
+#define __SDMMC_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
+
+/**
+  * @brief  Enable the SDMMC DMA transfer.
+  * @param  None  
+  * @retval None
+  */ 
+#define __SDMMC_DMA_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
+/**
+  * @brief  Disable the SDMMC DMA transfer.
+  * @param  None   
+  * @retval None
+  */
+#define __SDMMC_DMA_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
+ 
+/**
+  * @brief  Enable the SDMMC device interrupt.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  *         This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
+  * @retval None
+  */
+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the SDMMC device interrupt.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt   
+  * @retval None
+  */
+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Checks whether the specified SDMMC flag is set or not. 
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @param  __FLAG__: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDMMC_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDMMC_FLAG_RXACT:    Data receive in progress
+  *            @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDMMC_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDMMC_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDMMC_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDMMC_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDMMC_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDMMC_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
+  * @retval The new state of SDMMC_FLAG (SET or RESET).
+  */
+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
+
+
+/**
+  * @brief  Clears the SDMMC pending flags.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @param  __FLAG__: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDMMC_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDMMC_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDMMC_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDMMC_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDMMC_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDMMC_FLAG_SDMMCIT:   SD I/O interrupt received
+  * @retval None
+  */
+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))
+
+/**
+  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDMMC_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDMMC_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDMMC_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDMMC_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDMMC_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval The new state of SDMMC_IT (SET or RESET).
+  */
+#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief  Clears the SDMMC's interrupt pending bits.
+  * @param  __INSTANCE__: Pointer to SDMMC register base 
+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDMMC_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDMMC_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDMMC_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDMMC_IT_DATAEND:  Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+  *            @arg SDMMC_IT_SDIOIT:   SD I/O interrupt received interrupt
+  * @retval None
+  */
+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Disable Start the SD I/O Read Wait operations.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @retval None
+  */  
+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
+
+/**
+  * @brief  Enable Start the SD I/O Read Wait operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @retval None
+  */  
+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Disable Stop the SD I/O Read Wait operations.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
+
+/**
+  * @brief  Enable the SD I/O Mode Operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base   
+  * @retval None
+  */  
+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 
+
+/**
+  * @brief  Disable the SD I/O Mode Operation.
+  * @param  __INSTANCE__: Pointer to SDMMC register base 
+  * @retval None
+  */  
+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 
+
+/**
+  * @brief  Enable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 
+
+/**
+  * @brief  Disable the SD I/O Suspend command sending.
+  * @param  __INSTANCE__: Pointer to SDMMC register base  
+  * @retval None
+  */  
+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 
+      
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */  
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup SDMMC_LL_Exported_Functions
+  * @{
+  */
+  
+/* Initialization/de-initialization functions  **********************************/
+/** @addtogroup HAL_SDMMC_LL_Group1
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
+/**
+  * @}
+  */
+  
+/* I/O operation functions  *****************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group2
+  * @{
+  */
+/* Blocking mode: Polling */
+uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
+/**
+  * @}
+  */
+  
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup HAL_SDMMC_LL_Group3
+  * @{
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
+
+/* Command path state machine (CPSM) management functions */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
+uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
+
+/* Data path state machine (DPSM) management functions */
+HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
+uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
+uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
+
+/* SDMMC Cards mode management functions */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_LL_SDMMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Inc/stm32l4xx_ll_usb.h

@@ -0,0 +1,468 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_usb.h
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Header file of USB Core HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_LL_USB_H
+#define __STM32L4xx_LL_USB_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal_def.h"
+
+/** @addtogroup STM32L4xx_HAL
+  * @{
+  */
+
+/** @addtogroup USB_Core
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  USB Mode definition  
+  */  
+typedef enum 
+{
+   USB_OTG_DEVICE_MODE  = 0,
+   USB_OTG_HOST_MODE    = 1,
+   USB_OTG_DRD_MODE     = 2
+   
+}USB_OTG_ModeTypeDef;
+
+/** 
+  * @brief  URB States definition  
+  */ 
+typedef enum {
+  URB_IDLE = 0,
+  URB_DONE,
+  URB_NOTREADY,
+  URB_NYET,
+  URB_ERROR,
+  URB_STALL
+    
+}USB_OTG_URBStateTypeDef;
+
+/** 
+  * @brief  Host channel States  definition  
+  */ 
+typedef enum {
+  HC_IDLE = 0,
+  HC_XFRC,
+  HC_HALTED,
+  HC_NAK,
+  HC_NYET,
+  HC_STALL,
+  HC_XACTERR,  
+  HC_BBLERR,   
+  HC_DATATGLERR
+    
+}USB_OTG_HCStateTypeDef;
+
+/** 
+  * @brief  PCD Initialization Structure definition  
+  */
+typedef struct
+{
+  uint32_t dev_endpoints;        /*!< Device Endpoints number.
+                                      This parameter depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
+  
+  uint32_t Host_channels;        /*!< Host Channels number.
+                                      This parameter Depends on the used USB core.   
+                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */       
+
+  uint32_t speed;                /*!< USB Core speed.
+                                      This parameter can be any value of @ref USB_Core_Speed_                */        
+                               
+  uint32_t dma_enable;           /*!< Enable or disable of the USB embedded DMA.                             */            
+
+  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
+                                      This parameter can be any value of @ref USB_EP0_MPS_                   */              
+                       
+  uint32_t phy_itface;           /*!< Select the used PHY interface.
+                                      This parameter can be any value of @ref USB_Core_PHY_                  */ 
+                                
+  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */     
+                               
+  uint32_t low_power_enable;     /*!< Enable or disable the low power mode.                                  */     
+                          
+  uint32_t lpm_enable;           /*!< Enable or disable Battery charging.                                    */    
+
+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                 */   
+  
+  uint32_t vbus_sensing_enable;  /*!< Enable or disable the VBUS Sensing feature.                            */ 
+
+  uint32_t use_dedicated_ep1;    /*!< Enable or disable the use of the dedicated EP1 interrupt.              */      
+  
+  uint32_t use_external_vbus;    /*!< Enable or disable the use of the external VBUS.                        */   
+  
+}USB_OTG_CfgTypeDef;
+
+typedef struct
+{
+  uint8_t   num;            /*!< Endpoint number
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
+                                
+  uint8_t   is_in;          /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   is_stall;       /*!< Endpoint stall condition
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
+  
+  uint8_t   type;           /*!< Endpoint type
+                                 This parameter can be any value of @ref USB_EP_Type_                     */ 
+                                
+  uint8_t   data_pid_start; /*!< Initial data PID
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */
+                                
+  uint8_t   even_odd_frame; /*!< IFrame parity
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 1    */
+                                
+  uint16_t  tx_fifo_num;    /*!< Transmission FIFO number
+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 15   */
+                                
+  uint32_t  maxpacket;      /*!< Endpoint Max packet size
+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
+
+  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
+                                
+  uint32_t  dma_addr;       /*!< 32 bits aligned transfer buffer address                                  */
+  
+  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
+  
+  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
+
+}USB_OTG_EPTypeDef;
+
+typedef struct
+{
+  uint8_t   dev_addr ;     /*!< USB device address.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 255    */ 
+
+  uint8_t   ch_num;        /*!< Host channel number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_num;        /*!< Endpoint number.
+                                This parameter must be a number between Min_Data = 1 and Max_Data = 15     */ 
+                                
+  uint8_t   ep_is_in;      /*!< Endpoint direction
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */ 
+                                
+  uint8_t   speed;         /*!< USB Host speed.
+                                This parameter can be any value of @ref USB_Core_Speed_                    */
+                                
+  uint8_t   do_ping;       /*!< Enable or disable the use of the PING protocol for HS mode.                */
+  
+  uint8_t   process_ping;  /*!< Execute the PING protocol for HS mode.                                     */
+
+  uint8_t   ep_type;       /*!< Endpoint Type.
+                                This parameter can be any value of @ref USB_EP_Type_                       */
+                                
+  uint16_t  max_packet;    /*!< Endpoint Max packet size.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */
+                                
+  uint8_t   data_pid;      /*!< Initial data PID.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   *xfer_buff;    /*!< Pointer to transfer buffer.                                                */
+  
+  uint32_t  xfer_len;      /*!< Current transfer length.                                                   */
+  
+  uint32_t  xfer_count;    /*!< Partial transfer length in case of multi packet transfer.                  */
+  
+  uint8_t   toggle_in;     /*!< IN transfer current toggle flag.
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+                                
+  uint8_t   toggle_out;    /*!< OUT transfer current toggle flag
+                                This parameter must be a number between Min_Data = 0 and Max_Data = 1      */
+  
+  uint32_t  dma_addr;      /*!< 32 bits aligned transfer buffer address.                                   */
+  
+  uint32_t  ErrCnt;        /*!< Host channel error count.*/
+  
+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state. 
+                                           This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ 
+  
+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state. 
+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef  */ 
+                                             
+}USB_OTG_HCTypeDef;
+  
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PCD_Exported_Constants PCD Exported Constants
+  * @{
+  */
+
+/** @defgroup USB_Core_Mode_ USB Core Mode
+  * @{
+  */
+#define USB_OTG_MODE_DEVICE                    0
+#define USB_OTG_MODE_HOST                      1
+#define USB_OTG_MODE_DRD                       2
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Speed_   USB Core Speed
+  * @{
+  */  
+#define USB_OTG_SPEED_HIGH                     0
+#define USB_OTG_SPEED_HIGH_IN_FULL             1
+#define USB_OTG_SPEED_LOW                      2  
+#define USB_OTG_SPEED_FULL                     3
+/**
+  * @}
+  */
+  
+/** @defgroup USB_Core_PHY_   USB Core PHY
+  * @{
+  */   
+#define USB_OTG_EMBEDDED_PHY                   1
+/**
+  * @}
+  */
+  
+/** @defgroup USB_Core_MPS_   USB Core MPS
+  * @{
+  */
+#define USB_OTG_FS_MAX_PACKET_SIZE           64
+#define USB_OTG_MAX_EP0_SIZE                 64
+/**
+  * @}
+  */
+
+/** @defgroup USB_Core_Phy_Frequency_   USB Core Phy Frequency
+  * @{
+  */
+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0 << 1)
+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1 << 1)
+#define DSTS_ENUMSPD_LS_PHY_6MHZ               (2 << 1)
+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3 << 1)
+/**
+  * @}
+  */
+  
+/** @defgroup USB_CORE_Frame_Interval_   USB CORE Frame Interval
+  * @{
+  */  
+#define DCFG_FRAME_INTERVAL_80                 0
+#define DCFG_FRAME_INTERVAL_85                 1
+#define DCFG_FRAME_INTERVAL_90                 2
+#define DCFG_FRAME_INTERVAL_95                 3
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP0_MPS_  USB EP0 MPS
+  * @{
+  */
+#define DEP0CTL_MPS_64                         0
+#define DEP0CTL_MPS_32                         1
+#define DEP0CTL_MPS_16                         2
+#define DEP0CTL_MPS_8                          3
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP_Speed_  USB EP Speed
+  * @{
+  */
+#define EP_SPEED_LOW                           0
+#define EP_SPEED_FULL                          1
+#define EP_SPEED_HIGH                          2
+/**
+  * @}
+  */
+
+/** @defgroup USB_EP_Type_  USB EP Type
+  * @{
+  */
+#define EP_TYPE_CTRL                           0
+#define EP_TYPE_ISOC                           1
+#define EP_TYPE_BULK                           2
+#define EP_TYPE_INTR                           3
+#define EP_TYPE_MSK                            3
+/**
+  * @}
+  */
+
+/** @defgroup USB_STS_Defines_   USB STS Defines
+  * @{
+  */
+#define STS_GOUT_NAK                           1
+#define STS_DATA_UPDT                          2
+#define STS_XFER_COMP                          3
+#define STS_SETUP_COMP                         4
+#define STS_SETUP_UPDT                         6
+/**
+  * @}
+  */
+
+/** @defgroup HCFG_SPEED_Defines_   HCFG SPEED Defines
+  * @{
+  */  
+#define HCFG_30_60_MHZ                         0
+#define HCFG_48_MHZ                            1
+#define HCFG_6_MHZ                             2
+/**
+  * @}
+  */
+    
+/** @defgroup HPRT0_PRTSPD_SPEED_Defines_  HPRT0 PRTSPD SPEED Defines
+  * @{
+  */    
+#define HPRT0_PRTSPD_HIGH_SPEED                0
+#define HPRT0_PRTSPD_FULL_SPEED                1
+#define HPRT0_PRTSPD_LOW_SPEED                 2
+/**
+  * @}
+  */  
+   
+#define HCCHAR_CTRL                            0
+#define HCCHAR_ISOC                            1
+#define HCCHAR_BULK                            2
+#define HCCHAR_INTR                            3
+       
+#define HC_PID_DATA0                           0
+#define HC_PID_DATA2                           1
+#define HC_PID_DATA1                           2
+#define HC_PID_SETUP                           3
+
+#define GRXSTS_PKTSTS_IN                       2
+#define GRXSTS_PKTSTS_IN_XFER_COMP             3
+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5
+#define GRXSTS_PKTSTS_CH_HALTED                7
+    
+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_PCGCCTL_BASE)
+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_HOST_PORT_BASE)
+
+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)((uint32_t )USBx + USB_OTG_DEVICE_BASE)) 
+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)((uint32_t)USBx + USB_OTG_IN_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)((uint32_t)USBx + USB_OTG_OUT_ENDPOINT_BASE + (i)*USB_OTG_EP_REG_SIZE))        
+#define USBx_DFIFO(i)   *(__IO uint32_t *)((uint32_t)USBx + USB_OTG_FIFO_BASE + (i) * USB_OTG_FIFO_SIZE)
+
+#define USBx_HOST       ((USB_OTG_HostTypeDef *)((uint32_t )USBx + USB_OTG_HOST_BASE))  
+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)((uint32_t)USBx + USB_OTG_HOST_CHANNEL_BASE + (i)*USB_OTG_HOST_CHANNEL_SIZE))
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))
+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))
+    
+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))
+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))  
+
+/* Exported functions --------------------------------------------------------*/
+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef Init);
+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode);
+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed);
+HAL_StatusTypeDef USB_FlushRxFifo (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num );
+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma);
+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);
+void *            USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);
+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep);
+HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address);
+HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);
+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+uint32_t          USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum);
+void              USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);
+
+HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);
+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq);
+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state);
+uint32_t          USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx);
+uint32_t          USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,  
+                                  uint8_t ch_num,
+                                  uint8_t epnum,
+                                  uint8_t dev_address,
+                                  uint8_t speed,
+                                  uint8_t ep_type,
+                                  uint16_t mps);
+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);
+uint32_t          USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx);
+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num);
+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num);
+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+  
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32L4xx_LL_USB_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal.c

@@ -0,0 +1,660 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   HAL module driver.
+  *          This is the common part of the HAL initialization
+  *
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+    The common HAL driver contains a set of generic and common APIs that can be
+    used by the PPP peripheral drivers and the user to start using the HAL.
+    [..]
+    The HAL contains two APIs' categories:
+         (+) Common HAL APIs
+         (+) Services HAL APIs
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup HAL HAL
+  * @brief HAL module driver
+  * @{
+  */
+
+#ifdef HAL_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/**
+ * @brief STM32L4xx HAL Driver version number V1.3.0
+   */
+#define __STM32L4xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
+#define __STM32L4xx_HAL_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
+#define __STM32L4xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32L4xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
+#define __STM32L4xx_HAL_VERSION         ((__STM32L4xx_HAL_VERSION_MAIN << 24)\
+                                        |(__STM32L4xx_HAL_VERSION_SUB1 << 16)\
+                                        |(__STM32L4xx_HAL_VERSION_SUB2 << 8 )\
+                                        |(__STM32L4xx_HAL_VERSION_RC))
+
+#if defined(VREFBUF)
+#define VREFBUF_TIMEOUT_VALUE     (uint32_t)10   /* 10 ms (to be confirmed) */
+#endif /* VREFBUF */
+
+/* ------------ SYSCFG registers bit address in the alias region ------------ */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  MEMRMP Register ---*/
+/* Alias word address of FB_MODE bit */
+#define MEMRMP_OFFSET             SYSCFG_OFFSET
+#define FB_MODE_BitNumber         ((uint8_t)0x8)
+#define FB_MODE_BB                (PERIPH_BB_BASE + (MEMRMP_OFFSET * 32) + (FB_MODE_BitNumber * 4))
+
+/* --- SCSR Register ---*/
+/* Alias word address of SRAM2ER bit */
+#define SCSR_OFFSET              (SYSCFG_OFFSET + 0x18)
+#define BRER_BitNumber           ((uint8_t)0x0)
+#define SCSR_SRAM2ER_BB          (PERIPH_BB_BASE + (SCSR_OFFSET * 32) + (BRER_BitNumber * 4))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+__IO uint32_t uwTick;
+
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup HAL_Exported_Functions HAL Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
+ *  @brief    Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the Flash interface the NVIC allocation and initial time base
+          clock configuration.
+      (+) De-initialize common part of the HAL.
+      (+) Configure the time base source to have 1ms time base with a dedicated
+          Tick interrupt priority.
+        (++) SysTick timer is used by default as source of time base, but user
+             can eventually implement his proper time base source (a general purpose
+             timer for example or other time source), keeping in mind that Time base
+             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
+             handled in milliseconds basis.
+        (++) Time base configuration function (HAL_InitTick ()) is called automatically
+             at the beginning of the program after reset by HAL_Init() or at any time
+             when clock is configured, by HAL_RCC_ClockConfig().
+        (++) Source of time base is configured  to generate interrupts at regular
+             time intervals. Care must be taken if HAL_Delay() is called from a
+             peripheral ISR process, the Tick interrupt line must have higher priority
+            (numerically lower) than the peripheral interrupt. Otherwise the caller
+            ISR process will be blocked.
+       (++) functions affecting time base configurations are declared as __weak
+             to make  override possible  in case of other  implementations in user file.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the Flash prefetch, the Instruction and Data caches,
+  *         the time base source, NVIC and any required global low level hardware 
+  *         by calling the HAL_MspInit() callback function to be optionally defined in user file 
+  *         stm32l4xx_hal_msp.c.
+  *
+  * @note   HAL_Init() function is called at the beginning of program after reset and before 
+  *         the clock configuration.
+  *             
+  * @note   In the default implementation the System Timer (Systick) is used as source of time base.
+  *         The Systick configuration is based on MSI clock, as MSI is the clock
+  *         used after a system Reset and the NVIC configuration is set to Priority group 4.
+  *         Once done, time base tick starts incrementing: the tick variable counter is incremented 
+  *         each 1ms in the SysTick_Handler() interrupt handler.
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_Init(void)
+{
+  /* Configure Flash prefetch, Instruction cache, Data cache */
+  /* Default configuration at reset is:                      */
+  /* - Prefetch disabled                                     */
+  /* - Instruction cache enabled                             */
+  /* - Data cache enabled                                    */
+#if (INSTRUCTION_CACHE_ENABLE == 0)
+   __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+#endif /* INSTRUCTION_CACHE_ENABLE */
+
+#if (DATA_CACHE_ENABLE == 0)
+   __HAL_FLASH_DATA_CACHE_DISABLE();
+#endif /* DATA_CACHE_ENABLE */
+
+#if (PREFETCH_ENABLE != 0)
+  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
+  /* Set Interrupt Group Priority */
+  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
+  HAL_InitTick(TICK_INT_PRIORITY);
+
+  /* Init the low level hardware */
+  HAL_MspInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief De-initialize common part of the HAL and stop the source of time base.
+  * @note This function is optional.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DeInit(void)
+{
+  /* Reset of all peripherals */
+  __HAL_RCC_APB1_FORCE_RESET();
+  __HAL_RCC_APB1_RELEASE_RESET();
+
+  __HAL_RCC_APB2_FORCE_RESET();
+  __HAL_RCC_APB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB1_FORCE_RESET();
+  __HAL_RCC_AHB1_RELEASE_RESET();
+
+  __HAL_RCC_AHB2_FORCE_RESET();
+  __HAL_RCC_AHB2_RELEASE_RESET();
+
+  __HAL_RCC_AHB3_FORCE_RESET();
+  __HAL_RCC_AHB3_RELEASE_RESET();
+
+  /* De-Init the low level hardware */
+  HAL_MspDeInit();
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the MSP.
+  * @retval None
+  */
+__weak void HAL_MspDeInit(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief This function configures the source of the time base:
+  *        The time source is configured to have 1ms time base with a dedicated
+  *        Tick interrupt priority.
+  * @note This function is called  automatically at the beginning of program after
+  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig().
+  * @note In the default implementation, SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals.
+  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process,
+  *       The SysTick interrupt must have higher priority (numerically lower)
+  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
+  *       The function is declared as __weak  to be overwritten  in case of other
+  *       implementation  in user file.
+  * @param TickPriority: Tick interrupt priority.
+  * @retval HAL status
+  */
+__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
+{
+  /*Configure the SysTick to have interrupt in 1ms time basis*/
+  HAL_SYSTICK_Config(SystemCoreClock/1000);
+
+  /*Configure the SysTick IRQ priority */
+  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions
+ *  @brief    HAL Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Provide a tick value in millisecond
+      (+) Provide a blocking delay in millisecond
+      (+) Suspend the time base source interrupt
+      (+) Resume the time base source interrupt
+      (+) Get the HAL API driver version
+      (+) Get the device identifier
+      (+) Get the device revision identifier
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief This function is called to increment a global variable "uwTick"
+  *        used as application time base.
+  * @note In the default implementation, this variable is incremented each 1ms
+  *       in SysTick ISR.
+ * @note This function is declared as __weak to be overwritten in case of other
+  *      implementations in user file.
+  * @retval None
+  */
+__weak void HAL_IncTick(void)
+{
+  uwTick++;
+}
+
+/**
+  * @brief Provide a tick value in millisecond.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval tick value
+  */
+__weak uint32_t HAL_GetTick(void)
+{
+  return uwTick;
+}
+
+/**
+  * @brief Provide accurate delay (in milliseconds) based on variable incremented.
+  * @note In the default implementation , SysTick timer is the source of time base.
+  *       It is used to generate interrupts at regular time intervals where uwTick
+  *       is incremented.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @param Delay: specifies the delay time length, in milliseconds.
+  * @retval None
+  */
+__weak void HAL_Delay(uint32_t Delay)
+{
+  uint32_t tickstart = 0;
+  tickstart = HAL_GetTick();
+  while((HAL_GetTick() - tickstart) < Delay)
+  {
+  }
+}
+
+/**
+  * @brief Suspend Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
+  *       is called, the SysTick interrupt will be disabled and so Tick increment
+  *       is suspended.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_SuspendTick(void)
+{
+  /* Disable SysTick Interrupt */
+  SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief Resume Tick increment.
+  * @note In the default implementation , SysTick timer is the source of time base. It is
+  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
+  *       is called, the SysTick interrupt will be enabled and so Tick increment
+  *       is resumed.
+  * @note This function is declared as __weak to be overwritten in case of other
+  *       implementations in user file.
+  * @retval None
+  */
+__weak void HAL_ResumeTick(void)
+{
+  /* Enable SysTick Interrupt */
+  SysTick->CTRL  |= SysTick_CTRL_TICKINT_Msk;
+}
+
+/**
+  * @brief  Return the HAL revision.
+  * @retval version : 0xXYZR (8bits for each decimal, R for RC)
+  */
+uint32_t HAL_GetHalVersion(void)
+{
+ return __STM32L4xx_HAL_VERSION;
+}
+
+/**
+  * @brief  Return the device revision identifier.
+  * @retval Device revision identifier
+  */
+uint32_t HAL_GetREVID(void)
+{
+   return((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16);
+}
+
+/**
+  * @brief  Return the device identifier.
+  * @retval Device identifier
+  */
+uint32_t HAL_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions
+ *  @brief    HAL Debug functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL Debug functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Enable/Disable Debug module during SLEEP mode
+      (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes
+      (+) Enable/Disable Debug module during STANDBY mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable the Debug Module during SLEEP mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGSleepMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Disable the Debug Module during SLEEP mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGSleepMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STOP0/STOP1/STOP2 modes.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStopMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Disable the Debug Module during STOP0/STOP1/STOP2 modes.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStopMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
+}
+
+/**
+  * @brief  Enable the Debug Module during STANDBY mode.
+  * @retval None
+  */
+void HAL_DBGMCU_EnableDBGStandbyMode(void)
+{
+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @brief  Disable the Debug Module during STANDBY mode.
+  * @retval None
+  */
+void HAL_DBGMCU_DisableDBGStandbyMode(void)
+{
+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions
+ *  @brief    HAL SYSCFG configuration functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### HAL SYSCFG configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start a hardware SRAM2 erase operation
+      (+) Enable/Disable the Internal FLASH Bank Swapping
+      (+) Configure the Voltage reference buffer
+      (+) Enable/Disable the Voltage reference buffer
+      (+) Enable/Disable the I/O analog switch voltage booster
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start a hardware SRAM2 erase operation.
+  * @note   As long as SRAM2 is not erased the SRAM2ER bit will be set.
+  *         This bit is automatically reset at the end of the SRAM2 erase operation.
+  * @retval None
+  */
+void HAL_SYSCFG_SRAM2Erase(void)
+{
+  /* unlock the write protection of the SRAM2ER bit */
+  SYSCFG->SKR = 0xCA;
+  SYSCFG->SKR = 0x53;
+  /* Starts a hardware SRAM2 erase operation*/
+  *(__IO uint32_t *) SCSR_SRAM2ER_BB = (uint8_t)0x00000001;
+}
+
+/**
+  * @brief  Enable the Internal FLASH Bank Swapping.
+  *
+  * @note   This function can be used only for STM32L4xx devices.
+  *
+  * @note   Flash Bank2 mapped at 0x08000000 (and aliased @0x00000000)
+  *         and Flash Bank1 mapped at 0x08100000 (and aliased at 0x00100000)
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableMemorySwappingBank(void)
+{
+  *(__IO uint32_t *)FB_MODE_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Disable the Internal FLASH Bank Swapping.
+  *
+  * @note   This function can be used only for STM32L4xx devices.
+  *
+  * @note   The default state : Flash Bank1 mapped at 0x08000000 (and aliased @0x0000 0000)
+  *         and Flash Bank2 mapped at 0x08100000 (and aliased at 0x00100000)
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableMemorySwappingBank(void)
+{
+
+  *(__IO uint32_t *)FB_MODE_BB = (uint32_t)DISABLE;
+}
+
+#if defined(VREFBUF)
+/**
+  * @brief Configure the internal voltage reference buffer voltage scale.
+  * @param  VoltageScaling: specifies the output voltage to achieve
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 2.048 V. 
+  *                                                This requires VDDA equal to or higher than 2.4 V.
+  *            @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 2.5 V. 
+  *                                                This requires VDDA equal to or higher than 2.8 V.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
+  
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
+}
+
+/**
+  * @brief Configure the internal voltage reference buffer high impedance mode.
+  * @param  Mode: specifies the high impedance mode
+  *          This parameter can be one of the following values:
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
+  *            @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
+  
+  MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
+}
+
+/**
+  * @brief  Tune the Internal Voltage Reference buffer (VREFBUF).
+  * @retval None
+  */
+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue));
+  
+  MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue);
+}
+
+/**
+  * @brief  Enable the Internal Voltage Reference buffer (VREFBUF).
+  * @retval HAL_OK/HAL_TIMEOUT
+  */
+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
+{
+  uint32_t  tickstart = 0;
+  
+  SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+  
+  /* Get Start Tick*/
+  tickstart = HAL_GetTick();
+
+  /* Wait for VRR bit  */
+  while(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == RESET)
+  {
+    if((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the Internal Voltage Reference buffer (VREFBUF).
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableVREFBUF(void)
+{
+  CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
+}
+#endif /* VREFBUF */
+
+/**
+  * @brief  Enable the I/O analog switch voltage booster
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void)
+{
+  SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @brief  Disable the I/O analog switch voltage booster
+  *
+  * @retval None
+  */
+void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void)
+{
+  CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_cortex.c

@@ -0,0 +1,492 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_cortex.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   CORTEX HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the CORTEX:
+  *           + Initialization and Configuration functions
+  *           + Peripheral Control functions
+  *
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+
+    [..]
+    *** How to configure Interrupts using CORTEX HAL driver ***
+    ===========================================================
+    [..]
+    This section provides functions allowing to configure the NVIC interrupts (IRQ).
+    The Cortex-M4 exceptions are managed by CMSIS functions.
+
+    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function.
+    (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority().
+    (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ().
+
+     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible.
+         The pending IRQ priority will be managed only by the sub priority.
+
+     -@- IRQ priority order (sorted by highest to lowest priority):
+        (+@) Lowest pre-emption priority
+        (+@) Lowest sub priority
+        (+@) Lowest hardware priority (IRQ number)
+
+    [..]
+    *** How to configure SysTick using CORTEX HAL driver ***
+    ========================================================
+    [..]
+    Setup SysTick Timer for time base.
+
+   (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which
+       is a CMSIS function that:
+        (++) Configures the SysTick Reload register with value passed as function parameter.
+        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
+        (++) Resets the SysTick Counter register.
+        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
+        (++) Enables the SysTick Interrupt.
+        (++) Starts the SysTick Counter.
+
+   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
+       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
+       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
+       inside the stm32l4xx_hal_cortex.h file.
+
+   (+) You can change the SysTick IRQ priority by calling the
+       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function
+       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
+
+   (+) To adjust the SysTick time base, use the following formula:
+
+       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
+       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
+       (++) Reload Value should not exceed 0xFFFFFF
+
+  @endverbatim
+  ******************************************************************************
+
+  The table below gives the allowed values of the pre-emption priority and subpriority according
+  to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
+  
+    ==========================================================================================================================
+      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+    ==========================================================================================================================
+     NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bit for pre-emption priority
+                           |                                   |                             | 4 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------
+     NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bit for pre-emption priority
+                           |                                   |                             | 3 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+                           |                                   |                             | 2 bits for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+                           |                                   |                             | 1 bit for subpriority
+    --------------------------------------------------------------------------------------------------------------------------    
+     NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
+                           |                                   |                             | 0 bit for subpriority                       
+    ==========================================================================================================================
+
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup CORTEX
+  * @{
+  */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup CORTEX_Exported_Functions
+  * @{
+  */
+
+
+/** @addtogroup CORTEX_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+  ==============================================================================
+              ##### Initialization and Configuration functions #####
+  ==============================================================================
+    [..]
+      This section provides the CORTEX HAL driver functions allowing to configure Interrupts
+      SysTick functionalities
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Set the priority grouping field (pre-emption priority and subpriority)
+  *         using the required unlock sequence.
+  * @param  PriorityGroup: The priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *         @arg NVIC_PRIORITYGROUP_0: 0 bit  for pre-emption priority,
+  *                                    4 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_1: 1 bit  for pre-emption priority,
+  *                                    3 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+  *                                    2 bits for subpriority
+  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+  *                                    1 bit  for subpriority
+  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+  *                                    0 bit  for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
+  *         The pending IRQ priority will be managed only by the subpriority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+
+  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
+  NVIC_SetPriorityGrouping(PriorityGroup);
+}
+
+/**
+  * @brief  Set the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority
+  * @param  SubPriority: the subpriority level for the IRQ channel.
+  *         This parameter can be a value between 0 and 15
+  *         A lower priority value indicates a higher priority.
+  * @retval None
+  */
+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t prioritygroup = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
+
+  prioritygroup = NVIC_GetPriorityGrouping();
+
+  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
+}
+
+/**
+  * @brief  Enable a device specific interrupt in the NVIC interrupt controller.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Enable interrupt */
+  NVIC_EnableIRQ(IRQn);
+}
+
+/**
+  * @brief  Disable a device specific interrupt in the NVIC interrupt controller.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
+  
+  /* Disable interrupt */
+  NVIC_DisableIRQ(IRQn);
+}
+
+/**
+  * @brief  Initiate a system reset request to reset the MCU.
+  * @retval None
+  */
+void HAL_NVIC_SystemReset(void)
+{
+  /* System Reset */
+  NVIC_SystemReset();
+}
+
+/**
+  * @brief  Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): 
+  *         Counter is in free running mode to generate periodic interrupts.
+  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @retval status:  - 0  Function succeeded.
+  *                  - 1  Function failed.
+  */
+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
+{
+   return SysTick_Config(TicksNumb);
+}
+/**
+  * @}
+  */
+
+/** @addtogroup CORTEX_Exported_Functions_Group2
+ *  @brief   Cortex control functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]
+      This subsection provides a set of functions allowing to control the CORTEX
+      (NVIC, SYSTICK, MPU) functionalities.
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the priority grouping field from the NVIC Interrupt Controller.
+  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
+  */
+uint32_t HAL_NVIC_GetPriorityGrouping(void)
+{
+  /* Get the PRIGROUP[10:8] field value */
+  return NVIC_GetPriorityGrouping();
+}
+
+/**
+  * @brief  Get the priority of an interrupt.
+  * @param  IRQn: External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @param   PriorityGroup: the priority grouping bits length.
+  *         This parameter can be one of the following values:
+  *           @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority,
+  *                                      4 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority,
+  *                                      3 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority,
+  *                                      2 bits for subpriority
+  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority,
+  *                                      1 bit for subpriority
+  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority,
+  *                                      0 bit for subpriority
+  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+  * @retval None
+  */
+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
+ /* Get priority for Cortex-M system or device specific interrupts */
+  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
+}
+
+/**
+  * @brief  Set Pending bit of an external interrupt.
+  * @param  IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Set interrupt pending */
+  NVIC_SetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Get Pending Interrupt (read the pending register in the NVIC
+  *         and return the pending bit for the specified interrupt).
+  * @param  IRQn External interrupt number.
+  *          This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  /* Return 1 if pending else 0 */
+  return NVIC_GetPendingIRQ(IRQn);
+}
+
+/**
+  * @brief  Clear the pending bit of an external interrupt.
+  * @param  IRQn External interrupt number.
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval None
+  */
+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  /* Clear pending interrupt */
+  NVIC_ClearPendingIRQ(IRQn);
+}
+
+/**
+  * @brief Get active interrupt (read the active register in NVIC and return the active bit).
+  * @param IRQn External interrupt number
+  *         This parameter can be an enumerator of IRQn_Type enumeration
+  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
+  * @retval status: - 0  Interrupt status is not pending.
+  *                 - 1  Interrupt status is pending.
+  */
+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
+{
+  /* Return 1 if active else 0 */
+  return NVIC_GetActive(IRQn);
+}
+
+/**
+  * @brief  Configure the SysTick clock source.
+  * @param  CLKSource: specifies the SysTick clock source.
+  *          This parameter can be one of the following values:
+  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
+  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
+  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
+  {
+    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
+  }
+}
+
+/**
+  * @brief  Handle SYSTICK interrupt request.
+  * @retval None
+  */
+void HAL_SYSTICK_IRQHandler(void)
+{
+  HAL_SYSTICK_Callback();
+}
+
+/**
+  * @brief  SYSTICK callback.
+  * @retval None
+  */
+__weak void HAL_SYSTICK_Callback(void)
+{
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_SYSTICK_Callback could be implemented in the user file
+   */
+}
+
+#if (__MPU_PRESENT == 1)
+/**
+  * @brief  Initialize and configure the Region and the memory to be protected.
+  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+  *                the initialization and configuration information.
+  * @retval None
+  */
+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
+{
+  /* Check the parameters */
+  assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
+  assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
+
+  /* Set the Region number */
+  MPU->RNR = MPU_Init->Number;
+
+  if ((MPU_Init->Enable) != RESET)
+  {
+    /* Check the parameters */
+    assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
+    assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
+    assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
+    assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
+    assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
+    assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
+    assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
+    assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
+
+    MPU->RBAR = MPU_Init->BaseAddress;
+    MPU->RASR = ((uint32_t)MPU_Init->DisableExec        << MPU_RASR_XN_Pos)   |
+                ((uint32_t)MPU_Init->AccessPermission   << MPU_RASR_AP_Pos)   |
+                ((uint32_t)MPU_Init->TypeExtField       << MPU_RASR_TEX_Pos)  |
+                ((uint32_t)MPU_Init->IsShareable        << MPU_RASR_S_Pos)    |
+                ((uint32_t)MPU_Init->IsCacheable        << MPU_RASR_C_Pos)    |
+                ((uint32_t)MPU_Init->IsBufferable       << MPU_RASR_B_Pos)    |
+                ((uint32_t)MPU_Init->SubRegionDisable   << MPU_RASR_SRD_Pos)  |
+                ((uint32_t)MPU_Init->Size               << MPU_RASR_SIZE_Pos) |
+                ((uint32_t)MPU_Init->Enable             << MPU_RASR_ENABLE_Pos);
+  }
+  else
+  {
+    MPU->RBAR = 0x00;
+    MPU->RASR = 0x00;
+  }
+}
+#endif /* __MPU_PRESENT */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dac_ex.c

@@ -0,0 +1,620 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dac_ex.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   DAC HAL module driver.
+  *          This file provides firmware functions to manage the extended 
+  *          functionalities of the DAC peripheral.  
+  *     
+  *
+  @verbatim      
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]          
+      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
+      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
+      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
+      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting 
+          after reset, user setting if HAL_DACEx_SetUserTrimming have been used 
+          at least one time after reset).
+
+ @endverbatim    
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DACEx DACEx
+  * @brief DAC Extended HAL module driver
+  * @{
+  */ 
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+  
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
+ *  @brief    Extended IO operation functions 
+ *
+@verbatim   
+  ==============================================================================
+                 ##### Extended features functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+      (+) Get result of dual mode conversion.
+                     
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Select max triangle amplitude. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+  
+  /* Enable the triangle wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_1 | Amplitude) << Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC. 
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
+  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
+  *          This parameter can be one of the following values: 
+  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
+  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
+{   
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+     
+  /* Enable the noise wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<<Channel, (DAC_CR_WAVE1_0 | Amplitude) << Channel);
+  
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+
+
+/**
+  * @brief  Set the specified data holding register value for dual DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{  
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (Alignment == DAC_ALIGN_8B_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)hdac->Instance;
+  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2. 
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for Channel2.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Run the self calibration of one DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC channel configuration structure.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
+  * @retval HAL status
+  * @note   Calibration runs about 7 ms.
+  */
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+   
+  __IO uint32_t tmp = 0;
+  uint32_t trimmingvalue = 0;
+  uint32_t delta;
+  
+  /* store/restore channel configuration structure purpose */
+  uint32_t oldmodeconfiguration = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+    
+ /* Check the DAC handle allocation */
+ /* Check if DAC running */
+  if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_BUSY))
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Store configuration */
+  oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << Channel));
+  
+  /* Disable the selected DAC channel */
+  CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_EN1 << Channel));
+  
+  /* Set mode in MCR  for calibration */
+   MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), 0);
+   
+  /* Set DAC Channel1 DHR register to the middle value */
+  /* HAL_DAC_SetValue(hdac, Channel, DAC_ALIGN_12B_R, 0x0800); */
+  tmp = (uint32_t)hdac->Instance; 
+  if(Channel == DAC_CHANNEL_1)
+  {
+    tmp += DAC_DHR12R1_ALIGNMENT(DAC_ALIGN_12B_R);
+  }
+  else
+  {
+    tmp += DAC_DHR12R2_ALIGNMENT(DAC_ALIGN_12B_R);
+  }
+  *(__IO uint32_t *) tmp = 0x0800;
+     
+  /* Enable the selected DAC channel calibration */
+  /* i.e. set DAC_CR_CENx bit */
+  SET_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
+  
+  /* Init trimming counter */    
+  /* Medium value */
+  trimmingvalue = 16; 
+  delta = 8;
+  while (delta != 0) 
+    {
+    /* Set candidate trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
+  
+    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ 
+    /* i.e. minimum time needed between two calibration steps */
+    HAL_Delay(1);
+  
+    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
+      { 
+        /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
+        trimmingvalue += delta;
+      }
+      else
+      {
+        /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
+        trimmingvalue -= delta;
+       }                   
+     delta >>= 1;
+    }
+  
+    /* Still need to check if right calibration is current value or one step below */
+    /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
+    /* Set candidate trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
+  
+    /* tOFFTRIMmax delay x ms as per datasheet (electrical characteristics */ 
+    /* i.e. minimum time needed between two calibration steps */
+    HAL_Delay(1);
+    
+    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1<<Channel)) == RESET)
+      { 
+      /* OPAMP_CSR_OUTCAL is actually one value more */
+      trimmingvalue++;
+      /* Set right trimming */
+        MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (trimmingvalue<<Channel));
+      }
+    
+  /* Disable the selected DAC channel calibration */
+  /* i.e. clear DAC_CR_CENx bit */
+  CLEAR_BIT ((hdac->Instance->CR), (DAC_CR_CEN1 << Channel));
+  
+  sConfig->DAC_TrimmingValue = trimmingvalue;
+  sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+  
+  /* Restore configuration */
+  MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << Channel), oldmodeconfiguration);
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+  
+  return status;
+}
+
+/**
+  * @brief  Set the trimming mode and trimming value (user trimming mode applied).
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig: DAC configuration structure updated with new DAC trimming value.
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  NewTrimmingValue: DAC new trimming value
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue)
+{ 
+  HAL_StatusTypeDef status = HAL_OK;
+     
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(Channel));
+  assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
+  
+ /* Check the DAC handle allocation */
+  if(hdac == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Process locked */
+  __HAL_LOCK(hdac);
+  
+  /* Set new trimming */
+  MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1<<Channel), (NewTrimmingValue<<Channel));
+  
+  /* Update trimming mode */
+  sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+  sConfig->DAC_TrimmingValue = NewTrimmingValue;
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+    
+  return status;
+}
+
+/**
+  * @brief  Return the DAC trimming value.
+  * @param  hdac : DAC handle
+  * @param  Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval Trimming value : range: 0->31
+  *         
+ */
+
+uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  uint32_t trimmingvalue = 0;
+  
+  /* Check the DAC handle allocation */
+  /* And not in Reset state */
+  if((hdac == NULL) || (hdac->State == HAL_DAC_STATE_RESET))
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_DAC_CHANNEL(Channel));
+
+    /* Retrieve trimming  */
+    trimmingvalue = ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << Channel)) >> Channel);
+  }  
+  return trimmingvalue;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
+ *  @brief    Extended Peripheral Control functions 
+ *
+@verbatim   
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Configure channels. 
+      (+) Set the specified data holding register value for DAC channel.
+      
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the last data output value of the selected DAC channel.
+  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
+{
+  uint32_t tmp = 0;
+  
+  tmp |= hdac->Instance->DOR1;
+
+  tmp |= hdac->Instance->DOR2 << 16;
+  
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx private functions
+ *  @brief    Extended private functions
+   * @{
+  */
+
+/**
+  * @brief  DMA conversion complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+  
+  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
+  
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback. 
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
+{
+    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    /* Conversion complete callback */
+    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
+{
+  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+    
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+    
+  HAL_DACEx_ErrorCallbackCh2(hdac); 
+    
+  hdac->State= HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_dma.c

@@ -0,0 +1,899 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_dma.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   DMA HAL module driver.
+  *    
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the Direct Memory Access (DMA) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral State and errors functions
+  @verbatim
+  ==============================================================================
+                        ##### How to use this driver #####
+  ==============================================================================
+  [..]
+   (#) Enable and configure the peripheral to be connected to the DMA Channel
+       (except for internal SRAM / FLASH memories: no initialization is 
+       necessary). Please refer to the Reference manual for connection between peripherals
+       and DMA requests.
+
+   (#) For a given Channel, program the required configuration through the following parameters:
+       Channel request, Transfer Direction, Source and Destination data formats,
+       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
+       using HAL_DMA_Init() function.
+
+   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
+       detection.
+                    
+   (#) Use HAL_DMA_Abort() function to abort the current transfer
+                   
+     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
+     *** Polling mode IO operation ***
+     =================================
+    [..]
+          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
+              address and destination address and the Length of data to be transferred
+          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
+              case a fixed Timeout can be configured by User depending from his application.
+
+     *** Interrupt mode IO operation ***
+     ===================================
+    [..]
+          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
+          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
+              Source address and destination address and the Length of data to be transferred.
+              In this case the DMA interrupt is configured
+          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
+          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
+              add his own function by customization of function pointer XferCpltCallback and
+              XferErrorCallback (i.e. a member of DMA handle structure).
+
+     *** DMA HAL driver macros list ***
+     ============================================= 
+      [..]
+       Below the list of most used macros in DMA HAL driver.
+
+       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
+       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
+       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
+       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
+       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
+       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. 
+
+     [..] 
+      (@) You can refer to the DMA HAL driver header file for more useful macros  
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup DMA DMA
+  * @brief DMA HAL module driver
+  * @{
+  */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup DMA_Private_Constants DMA Private Constants
+  * @{
+  */
+#define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000)  /* 1s  */
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup DMA_Private_Functions DMA Private Functions
+  * @{
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Functions DMA Exported Functions
+  * @{
+  */
+
+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
+ *  @brief   Initialization and de-initialization functions 
+ *
+@verbatim
+ ===============================================================================
+             ##### Initialization and de-initialization functions  #####
+ ===============================================================================
+    [..]
+    This section provides functions allowing to initialize the DMA Channel source
+    and destination addresses, incrementation and data sizes, transfer direction, 
+    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
+    [..]
+    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
+    reference manual.  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DMA according to the specified
+  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
+  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tmp = 0;
+
+  /* Check the DMA handle allocation */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
+  assert_param(IS_DMA_MODE(hdma->Init.Mode));
+  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
+  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
+  {
+    assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
+  }
+  
+  if(hdma->State == HAL_DMA_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hdma->Lock = HAL_UNLOCKED;
+  }
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+  /* Get the CR register value */
+  tmp = hdma->Instance->CCR;
+
+  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
+  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
+                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
+                      DMA_CCR_DIR));
+
+  /* Prepare the DMA Channel configuration */
+  tmp |=  hdma->Init.Direction        |
+          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
+          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
+          hdma->Init.Mode                | hdma->Init.Priority;
+
+  /* Write to DMA Channel CR register */
+  hdma->Instance->CCR = tmp;
+
+  /* Set request selection */
+  if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY)
+  {
+    /* Write to DMA channel selection register */
+    if (hdma->Instance == DMA1_Channel1)
+    {
+      /*Reset request selection for DMA1 Channel1*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
+
+      /* Configure request selection for DMA1 Channel1 */
+      DMA1_CSELR->CSELR |= hdma->Init.Request;
+    }
+    else if (hdma->Instance == DMA1_Channel2)
+    {
+      /*Reset request selection for DMA1 Channel2*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
+
+      /* Configure request selection for DMA1 Channel2 */
+      DMA1_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
+    }
+    else if (hdma->Instance == DMA1_Channel3)
+    {
+      /*Reset request selection for DMA1 Channel3*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
+
+      /* Configure request selection for DMA1 Channel3 */
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
+    }
+    else if (hdma->Instance == DMA1_Channel4)
+    {
+      /*Reset request selection for DMA1 Channel4*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
+
+      /* Configure request selection for DMA1 Channel4 */
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
+    }
+    else if (hdma->Instance == DMA1_Channel5)
+    {
+      /*Reset request selection for DMA1 Channel5*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
+
+      /* Configure request selection for DMA1 Channel5 */
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
+    }
+    else if (hdma->Instance == DMA1_Channel6)
+    {
+      /*Reset request selection for DMA1 Channel6*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
+
+      /* Configure request selection for DMA1 Channel6 */
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
+    }
+    else if (hdma->Instance == DMA1_Channel7)
+    {
+      /*Reset request selection for DMA1 Channel7*/
+      DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
+
+      /* Configure request selection for DMA1 Channel7 */
+      DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
+    }
+    else if (hdma->Instance == DMA2_Channel1)
+    {
+      /*Reset request selection for DMA2 Channel1*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S;
+
+      /* Configure request selection for DMA2 Channel1 */
+      DMA2_CSELR->CSELR |= hdma->Init.Request;
+    }
+    else if (hdma->Instance == DMA2_Channel2)
+    {
+      /*Reset request selection for DMA2 Channel2*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S;
+
+      /* Configure request selection for DMA2 Channel2 */
+      DMA2_CSELR->CSELR |= (uint32_t)(hdma->Init.Request << 4);
+    }
+    else if (hdma->Instance == DMA2_Channel3)
+    {
+      /*Reset request selection for DMA2 Channel3*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S;
+
+      /* Configure request selection for DMA2 Channel3 */
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 8);
+    }
+    else if (hdma->Instance == DMA2_Channel4)
+    {
+      /*Reset request selection for DMA2 Channel4*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S;
+
+      /* Configure request selection for DMA2 Channel4 */
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 12);
+    }
+    else if (hdma->Instance == DMA2_Channel5)
+    {
+      /*Reset request selection for DMA2 Channel5*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S;
+
+      /* Configure request selection for DMA2 Channel5 */
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 16);
+    }
+    else if (hdma->Instance == DMA2_Channel6)
+    {
+      /*Reset request selection for DMA2 Channel6*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S;
+
+      /* Configure request selection for DMA2 Channel6 */
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 20);
+    }
+    else if (hdma->Instance == DMA2_Channel7)
+    {
+      /*Reset request selection for DMA2 Channel7*/
+      DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S;
+
+      /* Configure request selection for DMA2 Channel7 */
+      DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << 24);
+    }
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state*/
+  hdma->State  = HAL_DMA_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the DMA peripheral.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
+{
+  /* Check the DMA handle allocation */
+  if(hdma == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
+
+  /* Check the DMA peripheral state */
+  if(hdma->State == HAL_DMA_STATE_BUSY)
+  {
+     return HAL_ERROR;
+  }
+
+  /* Disable the selected DMA Channelx */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Reset DMA Channel control register */
+  hdma->Instance->CCR  = 0;
+
+  /* Reset DMA Channel Number of Data to Transfer register */
+  hdma->Instance->CNDTR = 0;
+
+  /* Reset DMA Channel peripheral address register */
+  hdma->Instance->CPAR  = 0;
+
+  /* Reset DMA Channel memory address register */
+  hdma->Instance->CMAR = 0;
+
+  /* Clear all flags */
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_GI_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+  /* Reset DMA channel selection register */
+  if (hdma->Instance == DMA1_Channel1)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C1S;
+  }
+  else if (hdma->Instance == DMA1_Channel2)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C2S;
+  }
+  else if (hdma->Instance == DMA1_Channel3)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C3S;
+  }
+  else if (hdma->Instance == DMA1_Channel4)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C4S;
+  }
+  else if (hdma->Instance == DMA1_Channel5)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C5S;
+  }
+  else if (hdma->Instance == DMA1_Channel6)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C6S;
+  }
+  else if (hdma->Instance == DMA1_Channel7)
+  {
+    /*Reset DMA request*/
+    DMA1_CSELR->CSELR &= ~DMA_CSELR_C7S;
+  }
+  else if (hdma->Instance == DMA2_Channel1)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C1S;
+  }
+  else if (hdma->Instance == DMA2_Channel2)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C2S;
+  }
+  else if (hdma->Instance == DMA2_Channel3)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C3S;
+  }
+  else if (hdma->Instance == DMA2_Channel4)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C4S;
+  }
+  else if (hdma->Instance == DMA2_Channel5)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C5S;
+  }
+  else if (hdma->Instance == DMA2_Channel6)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C6S;
+  }
+  else if (hdma->Instance == DMA2_Channel7)
+  {
+    /*Reset DMA request*/
+    DMA2_CSELR->CSELR &= ~DMA_CSELR_C7S;
+  }
+
+  /* Initialize the error code */
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+
+  /* Initialize the DMA state */
+  hdma->State = HAL_DMA_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
+ *  @brief   Input and Output operation functions
+ *
+@verbatim
+ ===============================================================================
+                      #####  IO operation functions  #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure the source, destination address and data length and Start DMA transfer
+      (+) Configure the source, destination address and data length and
+          Start DMA transfer with interrupt
+      (+) Abort DMA transfer
+      (+) Poll for transfer complete
+      (+) Handle DMA interrupt request
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the DMA Transfer.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+   /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Configure the source, destination address and the data length */
+  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+  /* Enable the Peripheral */
+  __HAL_DMA_ENABLE(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DMA Transfer with interrupt enabled.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Process locked */
+  __HAL_LOCK(hdma);
+
+  /* Change DMA peripheral state */
+  hdma->State = HAL_DMA_STATE_BUSY;
+
+   /* Check the parameters */
+  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
+
+  /* Disable the peripheral */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Configure the source, destination address and the data length */
+  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+
+  /* Enable the transfer complete interrupt */
+  /* Enable the Half transfer complete interrupt */
+  /* Enable the transfer Error interrupt */
+  __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+
+   /* Enable the Peripheral */
+  __HAL_DMA_ENABLE(hdma);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort the DMA Transfer.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  *                   
+  * @note  After disabling a DMA Channel, a check for wait until the DMA Channel is 
+  *        effectively disabled is added. If a Channel is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Channel will be effectively disabled only after the transfer of
+  *        this single data is finished.  
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
+{
+  uint32_t tickstart = 0;
+
+  /* Disable the channel */
+  __HAL_DMA_DISABLE(hdma);
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  /* Check if the DMA Channel is effectively disabled */
+  while((hdma->Instance->CCR & DMA_CCR_EN) != 0)
+  {
+    /* Check for the Timeout */
+    if((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT)
+    {
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_TIMEOUT;
+    }
+  }
+  /* Change the DMA state */
+  hdma->State = HAL_DMA_STATE_READY;
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdma);
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Polling for transfer complete.
+  * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
+  *                  the configuration information for the specified DMA Channel.
+  * @param  CompleteLevel: Specifies the DMA level complete.
+  * @param  Timeout:       Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
+{
+  uint32_t temp;
+  uint32_t tickstart = 0;
+
+  /* Get the level transfer complete flag */
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Transfer Complete flag */
+    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
+  }
+  else
+  {
+    /* Half Transfer Complete flag */
+    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
+  }
+
+  /* Get tick */
+  tickstart = HAL_GetTick();
+
+  while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
+  {
+    if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
+    {
+      /* Clear the transfer error flags */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+      /* Update error code */
+      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
+
+      /* Change the DMA state */
+      hdma->State= HAL_DMA_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      return HAL_ERROR;
+    }
+    /* Check for the Timeout */
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
+      {
+        /* Update error code */
+        hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT;
+
+        /* Change the DMA state */
+        hdma->State = HAL_DMA_STATE_TIMEOUT;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hdma);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
+  {
+    /* Clear the transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+    /* The selected Channelx EN bit is cleared (DMA is disabled and
+    all transfers are complete) */
+    hdma->State = HAL_DMA_STATE_READY;
+
+  }
+  else
+  {
+    /* Clear the half transfer complete flag */
+    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+    hdma->State = HAL_DMA_STATE_READY_HALF;
+  }
+  
+  /* Process unlocked */
+  __HAL_UNLOCK(hdma);  
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle DMA interrupt request.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval None
+  */
+void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
+{
+  /* Transfer Error Interrupt management ***************************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
+    {
+      /* Disable the transfer error interrupt */
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
+
+      /* Clear the transfer error flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_TE;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      if (hdma->XferErrorCallback != NULL)
+      {
+        /* Transfer error callback */
+        hdma->XferErrorCallback(hdma);
+      }
+    }
+  }
+
+  /* Half Transfer Complete Interrupt management ******************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
+    {
+      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
+      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+      {
+        /* Disable the half transfer interrupt */
+        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+      }
+      /* Clear the half transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
+
+      /* Change DMA peripheral state */
+      hdma->State = HAL_DMA_STATE_READY_HALF;
+
+      if(hdma->XferHalfCpltCallback != NULL)
+      {
+        /* Half transfer callback */
+        hdma->XferHalfCpltCallback(hdma);
+      }
+    }
+  }
+
+  /* Transfer Complete Interrupt management ***********************************/
+  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
+  {
+    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
+    {
+      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
+      {
+        /* Disable the transfer complete interrupt */
+        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
+      }
+      /* Clear the transfer complete flag */
+      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
+
+      /* Update error code */
+      hdma->ErrorCode |= HAL_DMA_ERROR_NONE;
+
+      /* Change the DMA state */
+      hdma->State = HAL_DMA_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hdma);
+
+      if(hdma->XferCpltCallback != NULL)
+      {
+        /* Transfer complete callback */
+        hdma->XferCpltCallback(hdma);
+      }
+    }
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
+ *  @brief    Peripheral State and Errors functions
+ *
+@verbatim
+ ===============================================================================
+            ##### Peripheral State and Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DMA state
+      (+) Get error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the DMA hande state.
+  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  *               the configuration information for the specified DMA Channel.
+  * @retval HAL state
+  */
+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
+{
+  /* Return DMA handle state */
+  return hdma->State;
+}
+
+/**
+  * @brief  Return the DMA error code.
+  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  *              the configuration information for the specified DMA Channel.
+  * @retval DMA Error Code
+  */
+uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
+{
+  return hdma->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DMA_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Sets the DMA Transfer parameter.
+  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  *                     the configuration information for the specified DMA Channel.
+  * @param  SrcAddress: The source memory Buffer address
+  * @param  DstAddress: The destination memory Buffer address
+  * @param  DataLength: The length of data to be transferred from source to destination
+  * @retval HAL status
+  */
+static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
+{
+  /* Configure DMA Channel data length */
+  hdma->Instance->CNDTR = DataLength;
+
+  /* Peripheral to Memory */
+  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
+  {
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CPAR = DstAddress;
+
+    /* Configure DMA Channel source address */
+    hdma->Instance->CMAR = SrcAddress;
+  }
+  /* Memory to Peripheral */
+  else
+  {
+    /* Configure DMA Channel source address */
+    hdma->Instance->CPAR = SrcAddress;
+
+    /* Configure DMA Channel destination address */
+    hdma->Instance->CMAR = DstAddress;
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_DMA_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash.c

@@ -0,0 +1,773 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash.c
+  * @author  MCD Application Team
+  * @version V1.3.0 
+  * @date    29-January-2016
+  * @brief   FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the internal FLASH memory:
+  *           + Program operations functions
+  *           + Memory Control functions 
+  *           + Peripheral Errors functions
+  *  
+ @verbatim    
+  ==============================================================================
+                        ##### FLASH peripheral features #####
+  ==============================================================================
+           
+  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
+       to the Flash memory. It implements the erase and program Flash memory operations 
+       and the read and write protection mechanisms.
+      
+  [..] The Flash memory interface accelerates code execution with a system of instruction
+       prefetch and cache lines. 
+
+  [..] The FLASH main features are:
+      (+) Flash memory read operations
+      (+) Flash memory program/erase operations
+      (+) Read / write protections
+      (+) Option bytes programming
+      (+) Prefetch on I-Code
+      (+) 32 cache lines of 4*64 bits on I-Code
+      (+) 8 cache lines of 4*64 bits on D-Code
+      (+) Error code correction (ECC) : Data in flash are 72-bits word
+          (8 bits added per double word)
+      
+      
+                        ##### How to use this driver #####
+ ==============================================================================
+    [..]                             
+      This driver provides functions and macros to configure and program the FLASH  
+      memory of all STM32L4xx devices. 
+   
+      (#) Flash Memory IO Programming functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Program functions: double word and fast program (full row programming)
+           (++) There Two modes of programming :
+            (+++) Polling mode using HAL_FLASH_Program() function
+            (+++) Interrupt mode using HAL_FLASH_Program_IT() function
+    
+      (#) Interrupts and flags management functions : 
+           (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
+           (++) Callback functions are called when the flash operations are finished :
+                HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise
+                HAL_FLASH_OperationErrorCallback()
+           (++) Get error flag status by calling HAL_GetError()    
+           
+      (#) Option bytes management functions :
+           (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and
+                HAL_FLASH_OB_Lock() functions
+           (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function.
+                In this case, a reset is generated
+                         
+    [..] 
+      In addition to these functions, this driver includes a set of macros allowing
+      to handle the following operations:
+       (+) Set the latency
+       (+) Enable/Disable the prefetch buffer
+       (+) Enable/Disable the Instruction cache and the Data cache
+       (+) Reset the Instruction cache and the Data cache
+       (+) Enable/Disable the Flash power-down during low-power run and sleep modes
+       (+) Enable/Disable the Flash interrupts
+       (+) Monitor the Flash flags status
+    
+ @endverbatim                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH FLASH
+  * @brief FLASH HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/ 
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASH_Private_Variables FLASH Private Variables
+ * @{
+ */
+/**
+  * @brief  Variable used for Program/Erase sectors under interruption 
+  */
+FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASH_Private_Functions FLASH Private Functions
+ * @{
+ */
+HAL_StatusTypeDef    FLASH_WaitForLastOperation(uint32_t Timeout);
+extern void          FLASH_PageErase(uint32_t Page, uint32_t Banks);
+extern void          FLASH_FlushCaches(void);
+static void          FLASH_SetErrorCode(void);
+static void          FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data);
+static void          FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup FLASH_Exported_Functions FLASH Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
+ *  @brief   Programming operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                  ##### Programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the FLASH 
+    program operations.
+ 
+@endverbatim
+  * @{
+  */
+ 
+/**
+  * @brief  Program double word or fast program of a row at a specified address.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
+  *                This parameter is the data for the double word program and the address where 
+  *                are stored the data for the row fast program
+  * 
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t prog_bit = 0;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+  
+  if(status == HAL_OK)
+  {
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+    if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+    {
+      /* Program double-word (64-bit) at a specified address */
+      FLASH_Program_DoubleWord(Address, Data);
+      prog_bit = FLASH_CR_PG;
+    }
+    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+    {
+      /* Fast program a 32 row double-word (64-bit) at a specified address */
+      FLASH_Program_Fast(Address, (uint32_t)Data);
+      
+      /* If it is the last row, the bit will be cleared at the end of the operation */
+      if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+      {
+        prog_bit = FLASH_CR_FSTPG;
+      }
+    }
+
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+    
+    /* If the program operation is completed, disable the PG or FSTPG Bit */
+    if (prog_bit != 0)
+    {
+      CLEAR_BIT(FLASH->CR, prog_bit);
+    }
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;  
+}
+
+/**
+  * @brief  Program double word or fast program of a row at a specified address with interrupt enabled.
+  * @param  TypeProgram:  Indicate the way to program at a specified address.
+  *                           This parameter can be a value of @ref FLASH_Type_Program
+  * @param  Address:  specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed
+  *                This parameter is the data for the double word program and the address where 
+  *                are stored the data for the row fast program
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram));
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Set internal variables used by the IRQ handler */
+  if(TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST)
+  {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM_LAST;
+  }
+  else
+  {
+    pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
+  }
+  pFlash.Address = Address;
+    
+  /* Enable End of Operation and Error interrupts */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+  if(TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
+  {
+    /* Program double-word (64-bit) at a specified address */
+    FLASH_Program_DoubleWord(Address, Data);
+  }
+    else if((TypeProgram == FLASH_TYPEPROGRAM_FAST) || (TypeProgram == FLASH_TYPEPROGRAM_FAST_AND_LAST))
+  {
+    /* Fast program a 32 row double-word (64-bit) at a specified address */
+    FLASH_Program_Fast(Address, (uint32_t)Data);
+  }
+
+  return status;  
+}
+
+/**
+  * @brief Handle FLASH interrupt request.
+  * @retval None
+  */
+void HAL_FLASH_IRQHandler(void)
+{
+  uint32_t tmp_page;
+
+  /* If the operation is completed, disable the PG, PNB, MER1, MER2 and PER Bit */
+  CLEAR_BIT(FLASH->CR, (FLASH_CR_PG | FLASH_CR_MER1 | FLASH_CR_PER | FLASH_CR_PNB));
+  CLEAR_BIT(FLASH->CR, FLASH_CR_MER2);
+  
+  /* Disable the FSTPG Bit only if it is the last row programmed */
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST)
+  {
+    CLEAR_BIT(FLASH->CR, FLASH_CR_FSTPG);
+  }
+
+  /* Check FLASH operation error flags */
+  if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    
+    /* FLASH error interrupt user callback */
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
+    {
+       HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+    }
+    else if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
+    {
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+    }
+    else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || 
+            (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
+    {
+       HAL_FLASH_OperationErrorCallback(pFlash.Address);
+    }
+
+    HAL_FLASH_OperationErrorCallback(pFlash.Address);
+
+    /*Stop the procedure ongoing*/
+    pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+
+    if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGE_ERASE)
+    {
+      /* Nb of pages to erased can be decreased */
+      pFlash.NbPagesToErase--;
+
+      /* Check if there are still pages to erase*/
+      if(pFlash.NbPagesToErase != 0)
+      {
+        /* Indicate user which page has been erased*/
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+
+        /* Increment page number */
+        pFlash.Page++;
+        tmp_page = pFlash.Page;
+        FLASH_PageErase(tmp_page, pFlash.Bank);
+      }
+      else
+      {
+        /* No more pages to Erase */
+        /* Reset Address and stop Erase pages procedure */
+        pFlash.Page = 0xFFFFFFFF;
+        pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+        
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Page);
+      }
+    }
+    else
+    {
+      if(pFlash.ProcedureOnGoing == FLASH_PROC_MASS_ERASE)
+      {
+        /* MassErase ended. Return the selected bank */
+        /* Flush the caches to be sure of the data consistency */
+        FLASH_FlushCaches() ;
+
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Bank);
+      }
+      else if((pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) || 
+              (pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM_LAST))
+      {
+        /* Program ended. Return the selected address */
+        /* FLASH EOP interrupt user callback */
+        HAL_FLASH_EndOfOperationCallback(pFlash.Address);
+      }
+
+      /*Clear the procedure ongoing*/
+      pFlash.ProcedureOnGoing = FLASH_PROC_NONE;
+    }
+  }
+
+  if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
+  {
+    /* Disable End of Operation and Error interrupts */
+    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(&pFlash);
+  }
+}
+
+/**
+  * @brief  FLASH end of operation interrupt callback.
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  *                  Mass Erase: Bank number which has been requested to erase
+  *                  Page Erase: Page which has been erased 
+  *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
+  *                  Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  FLASH operation error interrupt callback.
+  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  *                 Mass Erase: Bank number which has been requested to erase
+  *                 Page Erase: Page number which returned an error
+  *                 Program: Address which was selected for data program
+  * @retval None
+  */
+__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(ReturnValue);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
+ *  @brief   Management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the FLASH 
+    memory operations.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlock the FLASH control register access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+    WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Lock the FLASH control register access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_LOCK);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Unlock the FLASH Option Bytes Registers access.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
+{
+  if(READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1);
+    WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }  
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Lock the FLASH Option Bytes Registers access.
+  * @retval HAL Status 
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
+{
+  /* Set the bit to force the option byte reloading */
+  SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH); 
+
+  /* Wait for last operation to be completed */
+  return(FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE)); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
+ *  @brief   Peripheral Errors functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Peripheral Errors functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time Errors of the FLASH peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Get the specific FLASH error flag.
+  * @retval FLASH_ErrorCode: The returned value can be:
+  *            @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP)
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming Sequence error flag 
+  *            @arg HAL_FLASH_ERROR_PGP: FLASH Programming Parallelism error flag  
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag
+  *            @arg HAL_FLASH_ERROR_OPERATION: FLASH operation Error flag 
+  *            @arg HAL_FLASH_ERROR_NONE: No error set 
+  *            @arg HAL_FLASH_ERROR_OP: FLASH Operation error
+  *            @arg HAL_FLASH_ERROR_PROG: FLASH Programming error
+  *            @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error
+  *            @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error
+  *            @arg HAL_FLASH_ERROR_SIZ: FLASH Size error
+  *            @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error
+  *            @arg HAL_FLASH_ERROR_MIS: FLASH Fast programming data miss error
+  *            @arg HAL_FLASH_ERROR_FAST: FLASH Fast programming error
+  *            @arg HAL_FLASH_ERROR_RD: FLASH PCROP read error
+  *            @arg HAL_FLASH_ERROR_OPTV: FLASH Option validity error
+  *            @arg HAL_FLASH_ERROR_ECCD: FLASH two ECC errors have been detected
+  */
+uint32_t HAL_FLASH_GetError(void)
+{ 
+   return pFlash.ErrorCode;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASH_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Wait for a FLASH operation to complete.
+  * @param  Timeout: maximum flash operation timeout
+  * @retval HAL_StatusTypeDef HAL Status
+  */
+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+    
+  uint32_t timeout = HAL_GetTick() + Timeout;
+     
+  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) 
+  { 
+    if(Timeout != HAL_MAX_DELAY)
+    {
+      if(HAL_GetTick() >= timeout)
+      {
+        return HAL_TIMEOUT;
+      }
+    } 
+  }
+  
+  if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))  || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))  ||
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR)) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR)) || 
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))  || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) ||
+     (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD)))
+  {
+    /*Save the error code*/
+    FLASH_SetErrorCode();
+    
+    return HAL_ERROR;
+  }
+
+  /* Check FLASH End of Operation flag  */
+  if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP))
+  {
+    /* Clear FLASH End of Operation pending bit */
+    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
+  }
+  
+  /* If there is an error flag set */
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Set the specific FLASH error flag.
+  * @retval None
+  */
+static void FLASH_SetErrorCode(void)
+{  
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPERR))
+  {
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_OP;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PROGERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PROG;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_WRP;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGA;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_SIZ;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGSERR))
+  { 
+    pFlash.ErrorCode |= HAL_FLASH_ERROR_PGS;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_MISERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_MIS;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FASTERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_FAST;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_RD;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV;
+  }
+
+  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ECCD))
+  { 
+   pFlash.ErrorCode |= HAL_FLASH_ERROR_ECCD;
+  }
+
+  /* Clear error programming flags */
+  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ALL_ERRORS);
+} 
+
+/**
+  * @brief  Program double-word (64-bit) at a specified address.
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval None
+  */
+static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+  /* Set PG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_PG);
+  
+  /* Program the double word */
+  *(__IO uint32_t*)Address = (uint32_t)Data;
+  *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+}
+
+/**
+  * @brief  Fast program a 32 row double-word (64-bit) at a specified address.
+  * @param  Address: specifies the address to be programmed.
+  * @param  DataAddress: specifies the address where the data are stored.
+  * @retval None
+  */
+static void FLASH_Program_Fast(uint32_t Address, uint32_t DataAddress)
+{
+  uint8_t row_index = 32;
+  __IO uint64_t *dest_addr = (__IO uint64_t*)Address;
+  __IO uint64_t *src_addr = (__IO uint64_t*)DataAddress;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address));
+
+  /* Set FSTPG bit */
+  SET_BIT(FLASH->CR, FLASH_CR_FSTPG);
+  
+  /* Disable interrupts to avoid any interruption during the loop */
+  __disable_irq();
+  
+  /* Program the 32 double word */
+  do
+  {
+    *dest_addr++ = *src_addr++;
+  } while (--row_index != 0);
+
+  /* Re-enable the interrupts */
+  __enable_irq();
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ex.c

@@ -0,0 +1,980 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ex.c
+  * @author  MCD Application Team
+  * @version V1.3.0 
+  * @date    29-January-2016
+  * @brief   Extended FLASH HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH extended peripheral:
+  *           + Extended programming operations functions
+  *  
+ @verbatim    
+ ==============================================================================
+                   ##### Flash Extended features #####
+  ==============================================================================
+           
+  [..] Comparing to other previous devices, the FLASH interface for STM32L4xx 
+       devices contains the following additional features 
+       
+       (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
+           capability (RWW)
+       (+) Dual bank memory organization       
+       (+) PCROP protection for all banks
+   
+                        ##### How to use this driver #####
+ ==============================================================================
+  [..] This driver provides functions to configure and program the FLASH memory 
+       of all STM32L4xx devices. It includes
+      (#) Flash Memory Erase functions: 
+           (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and 
+                HAL_FLASH_Lock() functions
+           (++) Erase function: Erase page, erase all sectors
+           (++) There are two modes of erase :
+             (+++) Polling Mode using HAL_FLASHEx_Erase()
+             (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT()
+                         
+      (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to :
+        (++) Set/Reset the write protection
+        (++) Set the Read protection Level
+        (++) Program the user Option Bytes
+        (++) Configure the PCROP protection
+        
+      (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to :
+        (++) Get the value of a write protection area
+        (++) Know if the read protection is activated
+        (++) Get the value of the user Option Bytes
+        (++) Get the value of a PCROP area
+    
+ @endverbatim                      
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASHEx FLASHEx
+  * @brief FALSH Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup FLASHEx_Private_Variables FLASHEx Private Variables
+ * @{
+ */
+extern FLASH_ProcessTypeDef pFlash;
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions
+ * @{
+ */
+extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
+void                     FLASH_PageErase(uint32_t Page, uint32_t Banks);
+static void              FLASH_MassErase(uint32_t Banks);
+void                     FLASH_FlushCaches(void);
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel);
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig);
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr);
+static void              FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset);
+static uint32_t          FLASH_OB_GetRDP(void);
+static uint32_t          FLASH_OB_GetUser(void);
+static void              FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr);
+/**
+  * @}
+  */
+
+/* Exported functions -------------------------------------------------------*/
+/** @defgroup FLASHEx_Exported_Functions FLASH Extended Exported Functions
+  * @{
+  */ 
+
+/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions
+ *  @brief   Extended IO operation functions 
+ *
+@verbatim   
+ ===============================================================================
+                ##### Extended programming operation functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the Extended FLASH 
+    programming operations Operations.
+ 
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages.
+  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @param[out]  PageError  : pointer to variable that contains the configuration 
+  *         information on faulty page in case of error (0xFFFFFFFF means that all 
+  *         the pages have been correctly erased)
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  uint32_t page_index = 0;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if (status == HAL_OK)
+  {
+    pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+    if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+    {
+      /* Mass erase to be done */
+      FLASH_MassErase(pEraseInit->Banks);
+
+      /* Wait for last operation to be completed */
+      status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+      /* If the erase operation is completed, disable the MER1 and MER2 Bits */
+      CLEAR_BIT(FLASH->CR, (FLASH_CR_MER1 | FLASH_CR_MER2));
+    }
+    else
+    {
+      /*Initialization of PageError variable*/
+      *PageError = 0xFFFFFFFF;
+      
+      for(page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++)
+      {
+        FLASH_PageErase(page_index, pEraseInit->Banks);
+
+        /* Wait for last operation to be completed */
+        status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+        /* If the erase operation is completed, disable the PER Bit */
+        CLEAR_BIT(FLASH->CR, (FLASH_CR_PER | FLASH_CR_PNB));
+
+        if (status != HAL_OK)
+        {
+          /* In case of error, stop erase procedure and return the faulty address */
+          *PageError = page_index;
+          break;
+        }
+      }
+    }
+    
+    /* Flush the caches to be sure of the data consistency */
+    FLASH_FlushCaches();
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled.
+  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+  *         contains the configuration information for the erasing.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase));
+
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Enable End of Operation and Error interrupts */
+  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
+
+  pFlash.Bank = pEraseInit->Banks;
+
+  if (pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
+  {
+    /* Mass erase to be done */
+    pFlash.ProcedureOnGoing = FLASH_PROC_MASS_ERASE;
+    FLASH_MassErase(pEraseInit->Banks);
+  }
+  else
+  {
+    /* Erase by page to be done */
+    pFlash.ProcedureOnGoing = FLASH_PROC_PAGE_ERASE;
+    pFlash.NbPagesToErase = pEraseInit->NbPages;
+    pFlash.Page = pEraseInit->Page;
+
+    /*Erase 1st page and wait for IT */
+    FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Program Option bytes.
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
+  *         contains the configuration information for the programming.
+  * 
+  * @retval HAL Status
+  */
+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  HAL_StatusTypeDef status = HAL_ERROR;
+  
+  /* Process Locked */
+  __HAL_LOCK(&pFlash);
+
+  /* Check the parameters */
+  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
+  
+  pFlash.ErrorCode = HAL_FLASH_ERROR_NONE;
+
+  /* Write protection configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_WRP) != RESET)
+  {
+    /* Configure of Write protection on the selected area */
+    status = FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
+  }
+  
+  /* Read protection configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_RDP) != RESET)
+  {
+    /* Configure the Read protection level */
+    status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
+  }
+  
+  /* User Configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_USER) != RESET)
+  {
+    /* Configure the user option bytes */
+    status = FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig);
+  }
+  
+  /* PCROP Configuration */
+  if((pOBInit->OptionType & OPTIONBYTE_PCROP) != RESET)
+  {
+    /* Configure the Proprietary code readout protection */
+    status = FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROPStartAddr, pOBInit->PCROPEndAddr);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(&pFlash);
+
+  return status;
+}
+
+/**
+  * @brief  Get the Option bytes configuration.
+  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that contains the 
+  *                  configuration information. The fields pOBInit->WRPArea and 
+  *                  pOBInit->PCROPConfig should indicate which area is requested
+  *                  for the WRP and PCROP 
+  * 
+  * @retval None
+  */
+void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
+{
+  pOBInit->OptionType = (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP);
+
+  /* Get write protection on the selected area */
+  FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
+  
+  /* Get Read protection level */
+  pOBInit->RDPLevel = FLASH_OB_GetRDP();
+  
+  /* Get the user option bytes */
+  pOBInit->USERConfig = FLASH_OB_GetUser();
+  
+  /* Get the Proprietary code readout protection */
+  FLASH_OB_GetPCROP(&(pOBInit->PCROPConfig), &(pOBInit->PCROPStartAddr), &(pOBInit->PCROPEndAddr));
+  
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @addtogroup FLASHEx_Private_Functions
+  * @{
+  */
+/**
+  * @brief  Mass erase of FLASH memory.
+  * @param  Banks: Banks to be erased
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_BANK_1: Bank1 to be erased
+  *            @arg FLASH_BANK_2: Bank2 to be erased
+  *            @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
+  * @retval None
+  */
+static void FLASH_MassErase(uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK(Banks));
+
+  /* Set the Mass Erase Bit for the bank 1 if requested */
+  if((Banks & FLASH_BANK_1) != RESET)
+  {
+    SET_BIT(FLASH->CR, FLASH_CR_MER1);
+  }
+  
+  /* Set the Mass Erase Bit for the bank 2 if requested */
+  if((Banks & FLASH_BANK_2) != RESET)
+  {
+    SET_BIT(FLASH->CR, FLASH_CR_MER2);
+  }
+
+  /* Proceed to erase all sectors */
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+  * @brief  Erase the specified FLASH memory page.
+  * @param  Page: FLASH page to erase
+  *         This parameter must be a value between 0 and (max number of pages in the bank - 1)      
+  * @param  Banks: Bank(s) where the page will be erased
+  *          This parameter can be one or a combination of the following values:
+  *            @arg FLASH_BANK_1: Page in bank 1 to be erased
+  *            @arg FLASH_BANK_2: Page in bank 2 to be erased
+  * @retval None
+  */
+void FLASH_PageErase(uint32_t Page, uint32_t Banks)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_PAGE(Page));
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks));
+
+  if((Banks & FLASH_BANK_1) != RESET)
+  {
+    CLEAR_BIT(FLASH->CR, FLASH_CR_BKER);
+  }
+  else
+  {
+    SET_BIT(FLASH->CR, FLASH_CR_BKER);
+  }
+
+  /* Proceed to erase the page */
+  MODIFY_REG(FLASH->CR, FLASH_CR_PNB, (Page << 3));
+  SET_BIT(FLASH->CR, FLASH_CR_PER);
+  SET_BIT(FLASH->CR, FLASH_CR_STRT);
+}
+
+/**
+  * @brief  Flush the instruction and data caches.
+  * @retval None
+  */
+void FLASH_FlushCaches(void)
+{
+  /* Flush instruction cache  */
+  if(READ_BIT(FLASH->ACR, FLASH_ACR_ICEN) != RESET)
+  {
+    /* Disable instruction cache  */
+    __HAL_FLASH_INSTRUCTION_CACHE_DISABLE();
+    /* Reset instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_RESET();
+    /* Enable instruction cache */
+    __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+  }
+  
+  /* Flush data cache */
+  if(READ_BIT(FLASH->ACR, FLASH_ACR_DCEN) != RESET)
+  {
+    /* Disable data cache  */
+    __HAL_FLASH_DATA_CACHE_DISABLE();
+    /* Reset data cache */
+    __HAL_FLASH_DATA_CACHE_RESET();
+    /* Enable data cache */
+    __HAL_FLASH_DATA_CACHE_ENABLE();
+  }
+}
+
+/**
+  * @brief  Configure the write protection of the desired pages.
+  *
+  * @note   When the memory read protection level is selected (RDP level = 1), 
+  *         it is not possible to program or erase Flash memory if the CPU debug 
+  *         features are connected (JTAG or single wire) or boot code is being 
+  *         executed from RAM or System flash, even if WRP is not activated. 
+  * @note   To configure the WRP options, the option lock bit OPTLOCK must be 
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the WRP options, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  WRPArea: specifies the area to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A                      
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B                      
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A                      
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B                      
+  *
+  * @param  WRPStartOffset: specifies the start page of the write protected area
+  *          This parameter can be page number between 0 and (max number of pages in the bank - 1) 
+  *
+  * @param  WRDPEndOffset: specifies the end page of the write protected area
+  *          This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) 
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_WRPAREA(WRPArea));
+  assert_param(IS_FLASH_PAGE(WRPStartOffset));
+  assert_param(IS_FLASH_PAGE(WRDPEndOffset));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    /* Configure the write protected area */
+    if(WRPArea == OB_WRPAREA_BANK1_AREAA)
+    {
+      MODIFY_REG(FLASH->WRP1AR, (FLASH_WRP1AR_WRP1A_STRT | FLASH_WRP1AR_WRP1A_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+    else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
+    {
+      MODIFY_REG(FLASH->WRP1BR, (FLASH_WRP1BR_WRP1B_STRT | FLASH_WRP1BR_WRP1B_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+    else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
+    {
+      MODIFY_REG(FLASH->WRP2AR, (FLASH_WRP2AR_WRP2A_STRT | FLASH_WRP2AR_WRP2A_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+    else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
+    {
+      MODIFY_REG(FLASH->WRP2BR, (FLASH_WRP2BR_WRP2B_STRT | FLASH_WRP2BR_WRP2B_END), 
+                 (WRPStartOffset | (WRDPEndOffset << 16)));
+    }
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Set the read protection level.
+  *    
+  * @note   To configure the RDP level, the option lock bit OPTLOCK must be 
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the RDP level, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  * @note   !!! Warning : When enabling OB_RDP level 2 it's no more possible 
+  *         to go back to level 1 or 0 !!!
+  *    
+  * @param  RDPLevel: specifies the read protection level.
+  *         This parameter can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  *   
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint32_t RDPLevel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP_LEVEL(RDPLevel));
+    
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    /* Configure the RDP level in the option bytes register */
+    MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel);
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+
+  return status;            
+}
+
+/**
+  * @brief  Program the FLASH User Option Byte.    
+  *   
+  * @note   To configure the user option bytes, the option lock bit OPTLOCK must
+  *         be cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the user option bytes, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *   
+  * @param  UserType: The FLASH User Option Bytes to be modified 
+  * @param  UserConfig: The FLASH User Option Bytes values: 
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), IWDG_SW(Bit16),
+  *         IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19), BFB2(Bit20), 
+  *         DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 
+  *   
+  * @retval HAL status
+  */
+static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig)
+{
+  uint32_t optr_reg_val = 0;
+  uint32_t optr_reg_mask = 0;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_OB_USER_TYPE(UserType));
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  { 
+    if((UserType & OB_USER_BOR_LEV) != RESET)
+    {
+      /* BOR level option byte should be modified */
+      assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV));
+    
+      /* Set value and mask for BOR level option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV);
+      optr_reg_mask |= FLASH_OPTR_BOR_LEV;
+    }
+
+    if((UserType & OB_USER_nRST_STOP) != RESET)
+    {
+      /* nRST_STOP option byte should be modified */
+      assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP));
+    
+      /* Set value and mask for nRST_STOP option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP);
+      optr_reg_mask |= FLASH_OPTR_nRST_STOP;
+    }
+
+    if((UserType & OB_USER_nRST_STDBY) != RESET)
+    {
+      /* nRST_STDBY option byte should be modified */
+      assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY));
+    
+      /* Set value and mask for nRST_STDBY option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY);
+      optr_reg_mask |= FLASH_OPTR_nRST_STDBY;
+    }
+
+    if((UserType & OB_USER_nRST_SHDW) != RESET)
+    {
+      /* nRST_SHDW option byte should be modified */
+      assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW));
+    
+      /* Set value and mask for nRST_SHDW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW);
+      optr_reg_mask |= FLASH_OPTR_nRST_SHDW;
+    }
+
+    if((UserType & OB_USER_IWDG_SW) != RESET)
+    {
+      /* IWDG_SW option byte should be modified */
+      assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW));
+    
+      /* Set value and mask for IWDG_SW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW);
+      optr_reg_mask |= FLASH_OPTR_IWDG_SW;
+    }
+
+    if((UserType & OB_USER_IWDG_STOP) != RESET)
+    {
+      /* IWDG_STOP option byte should be modified */
+      assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP));
+    
+      /* Set value and mask for IWDG_STOP option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP);
+      optr_reg_mask |= FLASH_OPTR_IWDG_STOP;
+    }
+
+    if((UserType & OB_USER_IWDG_STDBY) != RESET)
+    {
+      /* IWDG_STDBY option byte should be modified */
+      assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY));
+    
+      /* Set value and mask for IWDG_STDBY option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY);
+      optr_reg_mask |= FLASH_OPTR_IWDG_STDBY;
+    }
+
+    if((UserType & OB_USER_WWDG_SW) != RESET)
+    {
+      /* WWDG_SW option byte should be modified */
+      assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW));
+    
+      /* Set value and mask for WWDG_SW option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW);
+      optr_reg_mask |= FLASH_OPTR_WWDG_SW;
+    }
+
+    if((UserType & OB_USER_BFB2) != RESET)
+    {
+      /* BFB2 option byte should be modified */
+      assert_param(IS_OB_USER_BFB2(UserConfig & FLASH_OPTR_BFB2));
+    
+      /* Set value and mask for BFB2 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_BFB2);
+      optr_reg_mask |= FLASH_OPTR_BFB2;
+    }
+
+    if((UserType & OB_USER_DUALBANK) != RESET)
+    {
+      /* DUALBANK option byte should be modified */
+      assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK));
+    
+      /* Set value and mask for DUALBANK option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK);
+      optr_reg_mask |= FLASH_OPTR_DUALBANK;
+    }
+
+    if((UserType & OB_USER_nBOOT1) != RESET)
+    {
+      /* nBOOT1 option byte should be modified */
+      assert_param(IS_OB_USER_BOOT1(UserConfig & FLASH_OPTR_nBOOT1));
+    
+      /* Set value and mask for nBOOT1 option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT1);
+      optr_reg_mask |= FLASH_OPTR_nBOOT1;
+    }
+
+    if((UserType & OB_USER_SRAM2_PE) != RESET)
+    {
+      /* SRAM2_PE option byte should be modified */
+      assert_param(IS_OB_USER_SRAM2_PARITY(UserConfig & FLASH_OPTR_SRAM2_PE));
+    
+      /* Set value and mask for SRAM2_PE option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_PE);
+      optr_reg_mask |= FLASH_OPTR_SRAM2_PE;
+    }
+
+    if((UserType & OB_USER_SRAM2_RST) != RESET)
+    {
+      /* SRAM2_RST option byte should be modified */
+      assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST));
+    
+      /* Set value and mask for SRAM2_RST option byte */
+      optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST);
+      optr_reg_mask |= FLASH_OPTR_SRAM2_RST;
+    }
+
+    /* Configure the option bytes register */
+    MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val);
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+
+  return status;            
+}
+
+/**
+  * @brief  Configure the Proprietary code readout protection of the desired addresses.
+  *
+  * @note   To configure the PCROP options, the option lock bit OPTLOCK must be 
+  *         cleared with the call of the HAL_FLASH_OB_Unlock() function.
+  * @note   To validate the PCROP options, the option bytes must be reloaded 
+  *         through the call of the HAL_FLASH_OB_Launch() function.
+  *
+  * @param  PCROPConfig: specifies the configuration (Bank to be configured and PCROP_RDP option).
+  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 
+  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
+  *
+  * @param  PCROPStartAddr: specifies the start address of the Proprietary code readout protection
+  *          This parameter can be an address between begin and end of the bank 
+  *
+  * @param  PCROPEndAddr: specifies the end address of the Proprietary code readout protection
+  *          This parameter can be an address between PCROPStartAddr and end of the bank 
+  *
+  * @retval HAL Status
+  */
+static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROPStartAddr, uint32_t PCROPEndAddr)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t reg_value = 0;
+  uint32_t bank1_addr, bank2_addr;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE(PCROPConfig & FLASH_BANK_BOTH));
+  assert_param(IS_OB_PCROP_RDP(PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPStartAddr));
+  assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROPEndAddr));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+  if(status == HAL_OK)
+  {
+    /* Get the information about the bank swapping */
+    if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
+    {
+      bank1_addr = FLASH_BASE;
+      bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+    }
+    else
+    {
+      bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+      bank2_addr = FLASH_BASE;
+    }
+  
+    /* Configure the Proprietary code readout protection */
+    if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_1)
+    {
+      reg_value = ((PCROPStartAddr - bank1_addr) >> 3);
+      MODIFY_REG(FLASH->PCROP1SR, FLASH_PCROP1SR_PCROP1_STRT, reg_value);
+
+      reg_value = ((PCROPEndAddr - bank1_addr) >> 3);
+      MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP1_END, reg_value);
+    }
+    else if((PCROPConfig & FLASH_BANK_BOTH) == FLASH_BANK_2)
+    {
+      reg_value = ((PCROPStartAddr - bank2_addr) >> 3);
+      MODIFY_REG(FLASH->PCROP2SR, FLASH_PCROP2SR_PCROP2_STRT, reg_value);
+
+      reg_value = ((PCROPEndAddr - bank2_addr) >> 3);
+      MODIFY_REG(FLASH->PCROP2ER, FLASH_PCROP2ER_PCROP2_END, reg_value);
+    }
+
+    MODIFY_REG(FLASH->PCROP1ER, FLASH_PCROP1ER_PCROP_RDP, (PCROPConfig & FLASH_PCROP1ER_PCROP_RDP));
+    
+    /* Set OPTSTRT Bit */
+    SET_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
+
+    /* If the option byte program operation is completed, disable the OPTSTRT Bit */
+    CLEAR_BIT(FLASH->CR, FLASH_CR_OPTSTRT);
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  *
+  * @param[in]  WRPArea: specifies the area to be returned.
+  *          This parameter can be one of the following values:
+  *            @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A                      
+  *            @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B                      
+  *            @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A                      
+  *            @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B                      
+  *
+  * @param[out]  WRPStartOffset: specifies the address where to copied the start page 
+  *                         of the write protected area
+  *
+  * @param[out]  WRDPEndOffset: specifies the address where to copied the end page of 
+  *                        the write protected area
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t * WRPStartOffset, uint32_t * WRDPEndOffset)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_WRPAREA(WRPArea));
+
+  /* Get the configuration of the write protected area */
+  if(WRPArea == OB_WRPAREA_BANK1_AREAA)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_END) >> 16);
+  }
+  else if(WRPArea == OB_WRPAREA_BANK1_AREAB)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_END) >> 16);
+  }
+  else if(WRPArea == OB_WRPAREA_BANK2_AREAA)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_END) >> 16);
+  }
+  else if(WRPArea == OB_WRPAREA_BANK2_AREAB)
+  {
+    *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_STRT);
+    *WRDPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_END) >> 16);
+  }
+}
+
+/**
+  * @brief  Return the FLASH Read Protection level.
+  * @retval FLASH ReadOut Protection Status:
+  *         This return value can be one of the following values:
+  *            @arg OB_RDP_LEVEL_0: No protection
+  *            @arg OB_RDP_LEVEL_1: Read protection of the memory
+  *            @arg OB_RDP_LEVEL_2: Full chip protection
+  */
+static uint32_t FLASH_OB_GetRDP(void)
+{
+  if ((READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_0) && 
+      (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP) != OB_RDP_LEVEL_2))
+  {
+    return (OB_RDP_LEVEL_1);
+  }
+  else
+  {
+    return (READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP));
+  }
+}
+
+/**
+  * @brief  Return the FLASH User Option Byte value.
+  * @retval The FLASH User Option Bytes values: 
+  *         BOR_LEV(Bit8-10), nRST_STOP(Bit12), nRST_STDBY(Bit13), nRST_SHDW(Bit14), 
+  *         IWDG_SW(Bit16), IWDG_STOP(Bit17), IWDG_STDBY(Bit18), WWDG_SW(Bit19),  
+  *         BFB2(Bit20), DUALBANK(Bit21), nBOOT1(Bit23), SRAM2_PE(Bit24) and SRAM2_RST(Bit25). 
+  */
+static uint32_t FLASH_OB_GetUser(void)
+{
+  uint32_t user_config = READ_REG(FLASH->OPTR);
+  CLEAR_BIT(user_config, FLASH_OPTR_RDP);
+  
+  return user_config;
+}
+
+/**
+  * @brief  Return the FLASH Write Protection Option Bytes value.
+  *
+  * @param PCROPConfig [inout]: specifies the configuration (Bank to be configured and PCROP_RDP option).
+  *          This parameter must be a combination of FLASH_BANK_1 or FLASH_BANK_2 
+  *          with OB_PCROP_RDP_NOT_ERASE or OB_PCROP_RDP_ERASE
+  *
+  * @param PCROPStartAddr [out]: specifies the address where to copied the start address 
+  *                         of the Proprietary code readout protection
+  *
+  * @param PCROPEndAddr [out]: specifies the address where to copied the end address of 
+  *                       the Proprietary code readout protection
+  *
+  * @retval None
+  */
+static void FLASH_OB_GetPCROP(uint32_t * PCROPConfig, uint32_t * PCROPStartAddr, uint32_t * PCROPEndAddr)
+{
+  uint32_t reg_value = 0;
+  uint32_t bank1_addr, bank2_addr;
+  
+  /* Check the parameters */
+  assert_param(IS_FLASH_BANK_EXCLUSIVE((*PCROPConfig) & FLASH_BANK_BOTH));
+
+  /* Get the information about the bank swapping */
+  if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0)
+  {
+    bank1_addr = FLASH_BASE;
+    bank2_addr = FLASH_BASE + FLASH_BANK_SIZE;
+  }
+  else
+  {
+    bank1_addr = FLASH_BASE + FLASH_BANK_SIZE;
+    bank2_addr = FLASH_BASE;
+  }
+
+  if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_1)
+  {
+    reg_value       = (READ_REG(FLASH->PCROP1SR) & FLASH_PCROP1SR_PCROP1_STRT);
+    *PCROPStartAddr = (reg_value << 3) + bank1_addr;
+    
+    reg_value     = (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP1_END);
+    *PCROPEndAddr = (reg_value << 3) + bank1_addr;
+  }
+  else if(((*PCROPConfig) & FLASH_BANK_BOTH) == FLASH_BANK_2)
+  {
+    reg_value       = (READ_REG(FLASH->PCROP2SR) & FLASH_PCROP2SR_PCROP2_STRT);
+    *PCROPStartAddr = (reg_value << 3) + bank2_addr;
+
+    reg_value     = (READ_REG(FLASH->PCROP2ER) & FLASH_PCROP2ER_PCROP2_END);
+    *PCROPEndAddr = (reg_value << 3) + bank2_addr;
+  }
+
+  *PCROPConfig |= (READ_REG(FLASH->PCROP1ER) & FLASH_PCROP1ER_PCROP_RDP);
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_flash_ramfunc.c

@@ -0,0 +1,155 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_flash_ramfunc.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   FLASH RAMFUNC driver.
+  *          This file provides a Flash firmware functions which should be 
+  *          executed from internal SRAM
+  *            + FLASH HalfPage Programming
+  *            + FLASH Power Down in Run mode
+  *
+  *  @verbatim
+  ==============================================================================
+                   ##### Flash RAM functions #####
+  ==============================================================================    
+
+    *** ARM Compiler ***
+    --------------------
+    [..] RAM functions are defined using the toolchain options. 
+         Functions that are executed in RAM should reside in a separate
+         source module. Using the 'Options for File' dialog you can simply change
+         the 'Code / Const' area of a module to a memory space in physical RAM.
+         Available memory areas are declared in the 'Target' tab of the 
+         Options for Target' dialog.
+
+    *** ICCARM Compiler ***
+    -----------------------
+    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
+
+    *** GNU Compiler ***
+    --------------------
+    [..] RAM functions are defined using a specific toolchain attribute
+         "__attribute__((section(".RamFunc")))".
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC FLASH_RAMFUNC
+  * @brief FLASH functions executed from RAM
+  * @{
+  */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions FLASH in RAM function Exported Functions
+  * @{
+  */
+
+/** @defgroup FLASH_RAMFUNC_Exported_Functions_Group1 Peripheral features functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### ramfunc functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions that should be executed from RAM.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief   Enable the Power down in Run Mode
+  * @note    This function should be called and executed from SRAM memory
+  * @retval None
+  */
+__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
+{
+  /* Enable the Power Down in Run mode*/
+  __HAL_FLASH_POWER_DOWN_ENABLE();
+  
+  return HAL_OK;
+  
+}
+
+/**
+  * @brief   Disable the Power down in Run Mode
+  * @note    This function should be called and executed from SRAM memory
+  * @retval None
+  */
+__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
+{
+  /* Disable the Power Down in Run mode*/
+  __HAL_FLASH_POWER_DOWN_DISABLE();
+
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */   
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+
+  
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+     
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_gpio.c

@@ -0,0 +1,562 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_gpio.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   GPIO HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *
+  @verbatim
+  ==============================================================================
+                    ##### GPIO Peripheral features #####
+  ==============================================================================
+  [..]
+    (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually
+        configured by software in several modes:
+        (++) Input mode
+        (++) Analog mode
+        (++) Output mode
+        (++) Alternate function mode
+        (++) External interrupt/event lines
+
+    (+) During and just after reset, the alternate functions and external interrupt
+        lines are not active and the I/O ports are configured in input floating mode.
+
+    (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be
+        activated or not.
+
+    (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull
+        type and the IO speed can be selected depending on the VDD value.
+
+    (+) The microcontroller IO pins are connected to onboard peripherals/modules through a
+        multiplexer that allows only one peripheral alternate function (AF) connected
+       to an IO pin at a time. In this way, there can be no conflict between peripherals
+       sharing the same IO pin.
+
+    (+) All ports have external interrupt/event capability. To use external interrupt
+        lines, the port must be configured in input mode. All available GPIO pins are
+        connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
+
+    (+) The external interrupt/event controller consists of up to 39 edge detectors
+        (16 lines are connected to GPIO) for generating event/interrupt requests (each
+        input line can be independently configured to select the type (interrupt or event)
+        and the corresponding trigger event (rising or falling or both). Each line can
+        also be masked independently.
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+    (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE().
+
+    (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
+        (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
+        (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef
+             structure.
+        (++) In case of Output or alternate function mode selection: the speed is
+             configured through "Speed" member from GPIO_InitTypeDef structure.
+        (++) In alternate mode is selection, the alternate function connected to the IO
+             is configured through "Alternate" member from GPIO_InitTypeDef structure.
+        (++) Analog mode is required when a pin is to be used as ADC channel
+             or DAC output.
+        (++) In case of external interrupt/event selection the "Mode" member from
+             GPIO_InitTypeDef structure select the type (interrupt or event) and
+             the corresponding trigger event (rising or falling or both).
+
+    (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority
+        mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
+        HAL_NVIC_EnableIRQ().
+
+    (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
+
+    (#) To set/reset the level of a pin configured in output mode use
+        HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
+
+   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
+  
+    (#) During and just after reset, the alternate functions are not
+        active and the GPIO pins are configured in input floating mode (except JTAG
+        pins).
+
+    (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose
+        (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has
+        priority over the GPIO function.
+
+    (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
+        general purpose PH0 and PH1, respectively, when the HSE oscillator is off.
+        The HSE has priority over the GPIO function.
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup GPIO GPIO
+  * @brief GPIO HAL module driver
+  * @{
+  */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup GPIO_Private_Defines GPIO Private Defines
+  * @{
+  */
+#define GPIO_MODE             ((uint32_t)0x00000003)
+#define ANALOG_MODE           ((uint32_t)0x00000008)
+#define EXTI_MODE             ((uint32_t)0x10000000)
+#define GPIO_MODE_IT          ((uint32_t)0x00010000)
+#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
+#define RISING_EDGE           ((uint32_t)0x00100000)
+#define FALLING_EDGE          ((uint32_t)0x00200000)
+#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010)
+
+#define GPIO_NUMBER           ((uint32_t)16)
+/**
+  * @}
+  */
+  
+/* Private macros ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GPIO_Private_Macros GPIO Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
+  * @{
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
+ *  @brief    Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
+{
+  uint32_t position = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t temp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
+  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
+  assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
+
+  /* Configure the port pins */
+  while (((GPIO_Init->Pin) >> position) != RESET)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Init->Pin) & (1U << position);
+
+    if(iocurrent)
+    {
+      /*--------------------- GPIO Mode Configuration ------------------------*/
+      /* In case of Alternate function mode selection */
+      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Alternate function parameters */
+        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
+        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
+        
+        /* Configure Alternate function mapped with the current IO */
+        temp = GPIOx->AFR[position >> 3];
+        temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+        temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));
+        GPIOx->AFR[position >> 3] = temp;
+      }
+
+      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
+      temp = GPIOx->MODER;
+      temp &= ~(GPIO_MODER_MODE0 << (position * 2));
+      temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2));
+      GPIOx->MODER = temp;
+
+      /* In case of Output or Alternate function mode selection */
+      if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+         (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
+      {
+        /* Check the Speed parameter */
+        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
+        /* Configure the IO Speed */
+        temp = GPIOx->OSPEEDR;
+        temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
+        temp |= (GPIO_Init->Speed << (position * 2));
+        GPIOx->OSPEEDR = temp;
+
+        /* Configure the IO Output Type */
+        temp = GPIOx->OTYPER;
+        temp &= ~(GPIO_OTYPER_OT0 << position) ;
+        temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
+        GPIOx->OTYPER = temp;
+      }
+
+      /* In case of Analog mode, check if ADC control mode is selected */
+      if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
+      {
+        /* Configure the IO Output Type */
+        temp = GPIOx->ASCR;
+        temp &= ~(GPIO_ASCR_ASC0 << position) ;
+        temp |= (((GPIO_Init->Mode & ANALOG_MODE) >> 3) << position);
+        GPIOx->ASCR = temp;
+      }
+
+      /* Activate the Pull-up or Pull down resistor for the current IO */
+      temp = GPIOx->PUPDR;
+      temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
+      temp |= ((GPIO_Init->Pull) << (position * 2));
+      GPIOx->PUPDR = temp;
+
+      /*--------------------- EXTI Mode Configuration ------------------------*/
+      /* Configure the External Interrupt or event for the current IO */
+      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+      {
+        /* Enable SYSCFG Clock */
+        __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+        temp = SYSCFG->EXTICR[position >> 2];
+        temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03)));
+        temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03)));
+        SYSCFG->EXTICR[position >> 2] = temp;
+
+        /* Clear EXTI line configuration */
+        temp = EXTI->IMR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->IMR1 = temp;
+
+        temp = EXTI->EMR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->EMR1 = temp;
+
+        /* Clear Rising Falling edge configuration */
+        temp = EXTI->RTSR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->RTSR1 = temp;
+
+        temp = EXTI->FTSR1;
+        temp &= ~((uint32_t)iocurrent);
+        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+        {
+          temp |= iocurrent;
+        }
+        EXTI->FTSR1 = temp;
+      }
+    }
+    
+    position++;
+  }
+}
+
+/**
+  * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @retval None
+  */
+void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
+{
+  uint32_t position = 0x00;
+  uint32_t iocurrent = 0x00;
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Configure the port pins */
+  while ((GPIO_Pin >> position) != RESET)
+  {
+    /* Get current io position */
+    iocurrent = (GPIO_Pin) & (1U << position);
+
+    if (iocurrent)
+    {
+      /*------------------------- GPIO Mode Configuration --------------------*/
+      /* Configure IO in Analog Mode */
+      GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2));
+
+      /* Configure the default Alternate Function in current IO */
+      GPIOx->AFR[position >> 3] &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
+
+      /* Configure the default value for IO Speed */
+      GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2));
+
+      /* Configure the default value IO Output Type */
+      GPIOx->OTYPER  &= ~(GPIO_OTYPER_OT0 << position) ;
+
+      /* Deactivate the Pull-up and Pull-down resistor for the current IO */
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2));
+
+      /* Deactivate the Control bit of Analog mode for the current IO */
+      GPIOx->ASCR &= ~(GPIO_ASCR_ASC0<< position);
+
+      /*------------------------- EXTI Mode Configuration --------------------*/
+      /* Clear the External Interrupt or Event for the current IO */
+      
+      tmp = SYSCFG->EXTICR[position >> 2];
+      tmp &= (((uint32_t)0x0F) << (4 * (position & 0x03)));
+      if(tmp == (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))))
+      {
+        tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
+        SYSCFG->EXTICR[position >> 2] &= ~tmp;
+
+        /* Clear EXTI line configuration */
+        EXTI->IMR1 &= ~((uint32_t)iocurrent);
+        EXTI->EMR1 &= ~((uint32_t)iocurrent);
+
+        /* Clear Rising Falling edge configuration */
+        EXTI->RTSR1 &= ~((uint32_t)iocurrent);
+        EXTI->FTSR1 &= ~((uint32_t)iocurrent);
+      }
+    }
+    
+    position++;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
+ *  @brief GPIO Read, Write, Toggle, Lock and EXTI management functions.
+ *
+@verbatim
+ ===============================================================================
+                       ##### IO operation functions #####
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read the specified input port pin.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_PIN_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  GPIO_PinState bitstatus;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
+  {
+    bitstatus = GPIO_PIN_SET;
+  }
+  else
+  {
+    bitstatus = GPIO_PIN_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Set or clear the selected data port bit.
+  *
+  * @note   This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  *
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
+  * @param  PinState: specifies the value to be written to the selected bit.
+  *         This parameter can be one of the GPIO_PinState enum values:
+  *            @arg GPIO_PIN_RESET: to clear the port pin
+  *            @arg GPIO_PIN_SET: to set the port pin
+  * @retval None
+  */
+void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_PIN_ACTION(PinState));
+
+  if(PinState != GPIO_PIN_RESET)
+  {
+    GPIOx->BSRR = (uint32_t)GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BRR = (uint32_t)GPIO_Pin;
+  }
+}
+
+/**
+  * @brief  Toggle the specified GPIO pin.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the pin to be toggled.
+  * @retval None
+  */
+void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+* @brief  Lock GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..H) to select the GPIO peripheral for STM32L4 family
+  * @param  GPIO_Pin: specifies the port bits to be locked.
+  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = GPIO_LCKR_LCKK;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  /* Apply lock key write sequence */
+  tmp |= GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
+  GPIOx->LCKR = GPIO_Pin;
+  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+
+  if((GPIOx->LCKR & GPIO_LCKR_LCKK) != RESET)
+  {
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Handle EXTI interrupt request.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
+{
+  /* EXTI line interrupt detected */
+  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET)
+  {
+    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
+    HAL_GPIO_EXTI_Callback(GPIO_Pin);
+  }
+}
+
+/**
+  * @brief  EXTI line detection callback.
+  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @retval None
+  */
+__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(GPIO_Pin);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_GPIO_EXTI_Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+
+#endif /* HAL_GPIO_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_i2c_ex.c

@@ -0,0 +1,350 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_i2c_ex.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   I2C Extended HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of I2C Extended peripheral:
+  *           + Extended features functions
+  *
+  @verbatim
+  ==============================================================================
+               ##### I2C peripheral Extended features  #####
+  ==============================================================================
+
+  [..] Comparing to other previous devices, the I2C interface for STM32L4xx
+       devices contains the following additional features
+
+       (+) Possibility to disable or enable Analog Noise Filter
+       (+) Use of a configured Digital Noise Filter
+       (+) Disable or enable wakeup from Stop modes
+
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..] This driver provides functions to configure Noise Filter and Wake Up Feature
+    (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
+    (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
+    (#) Configure the enable or disable of I2C Wake Up Mode using the functions :
+          (++) HAL_I2CEx_EnableWakeUp()
+          (++) HAL_I2CEx_DisableWakeUp()
+    (#) Configure the enable or disable of fast mode plus driving capability using the functions :
+          (++) HAL_I2CEx_EnableFastModePlus()
+          (++) HAL_I2CEx_DisbleFastModePlus()
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup I2CEx I2CEx
+  * @brief I2C Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
+  * @brief    Extended features functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Extended features functions #####
+ ===============================================================================
+    [..] This section provides functions allowing to:
+      (+) Configure Noise Filters 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure I2C Analog noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  AnalogFilter New state of the Analog filter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Reset I2Cx ANOFF bit */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+    /* Set analog filter bit*/
+    hi2c->Instance->CR1 |= AnalogFilter;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief  Configure I2C Digital noise filter.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @param  DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+  assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Get the old register value */
+    tmpreg = hi2c->Instance->CR1;
+
+    /* Reset I2Cx DNF bits [11:8] */
+    tmpreg &= ~(I2C_CR1_DNF);
+
+    /* Set I2Cx DNF coefficient */
+    tmpreg |= DigitalFilter << 8;
+
+    /* Store the new register value */
+    hi2c->Instance->CR1 = tmpreg;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+/**
+  * @brief  Enable I2C wakeup from stop mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 |= I2C_CR1_WUPEN;
+
+    __HAL_I2C_ENABLE(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+
+/**
+  * @brief  Disable I2C wakeup from stop mode.
+  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
+  *                the configuration information for the specified I2Cx peripheral.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
+
+  if(hi2c->State == HAL_I2C_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hi2c);
+
+    hi2c->State = HAL_I2C_STATE_BUSY;
+
+    /* Disable the selected I2C peripheral */
+    __HAL_I2C_DISABLE(hi2c);
+
+    /* Enable wakeup from stop mode */
+    hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN);
+
+    __HAL_I2C_ENABLE(hi2c); 
+
+    hi2c->State = HAL_I2C_STATE_READY;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hi2c);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Enable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be enabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be enabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Enable fast mode plus driving capability for selected pin */
+  SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @brief Disable the I2C fast mode plus driving capability.
+  * @param ConfigFastModePlus Selects the pin.
+  *   This parameter can be one of the @ref I2CEx_FastModePlus values
+  * @note  For I2C1, fast mode plus driving capability can be disabled on all selected
+  *        I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently
+  *        on each one of the following pins PB6, PB7, PB8 and PB9.
+  * @note  For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability
+  *        can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter.
+  * @note  For all I2C2 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C2 parameter.
+  * @note  For all I2C3 pins fast mode plus driving capability can be disabled
+  *        only by using I2C_FASTMODEPLUS_I2C3 parameter.
+  * @retval None
+  */
+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
+{
+  /* Check the parameter */
+  assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
+
+  /* Enable SYSCFG clock */
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+
+  /* Disable fast mode plus driving capability for selected pin */
+  CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_I2C_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pcd_ex.c

@@ -0,0 +1,323 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pcd_ex.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   PCD Extended HAL module driver.  
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the USB Peripheral Controller:
+  *           + Extended features functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+#if defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PCDEx PCDEx
+  * @brief PCD Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_PCD_MODULE_ENABLED
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
+  * @{
+  */
+  
+/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions
+  * @brief    PCDEx control functions 
+ *
+@verbatim   
+ ===============================================================================
+                 ##### Extended features functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Update FIFO configuration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set Tx FIFO
+  * @param  hpcd: PCD handle
+  * @param  fifo: The number of Tx fifo
+  * @param  size: Fifo size
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
+{
+  uint8_t i = 0;
+  uint32_t Tx_Offset = 0;
+
+  /*  TXn min size = 16 words. (n  : Transmit FIFO index)
+      When a TxFIFO is not used, the Configuration should be as follows: 
+          case 1 :  n > m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txm can use the space allocated for Txn.
+         case2  :  n < m    and Txn is not used    (n,m  : Transmit FIFO indexes)
+         --> Txn should be configured with the minimum space of 16 words
+     The FIFO is used optimally when used TxFIFOs are allocated in the top 
+         of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
+     When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */
+  
+  Tx_Offset = hpcd->Instance->GRXFSIZ;
+  
+  if(fifo == 0)
+  {
+    hpcd->Instance->DIEPTXF0_HNPTXFSIZ = (size << 16) | Tx_Offset;
+  }
+  else
+  {
+    Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16;
+    for (i = 0; i < (fifo - 1); i++)
+    {
+      Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16);
+    }
+    
+    /* Multiply Tx_Size by 2 to get higher performance */
+    hpcd->Instance->DIEPTXF[fifo - 1] = (size << 16) | Tx_Offset;
+  }
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set Rx FIFO
+  * @param  hpcd: PCD handle
+  * @param  size: Size of Rx fifo
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
+{
+  hpcd->Instance->GRXFSIZ = size;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Activate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  
+  hpcd->lpm_active = ENABLE;
+  hpcd->LPM_State = LPM_L0;
+  USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate LPM feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  
+  hpcd->lpm_active = DISABLE;
+  USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM;
+  USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Handle BatteryCharging Process.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  uint32_t tickstart = HAL_GetTick();
+  
+  /* Start BCD When device is connected */
+  if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS)
+  { 
+    /* Enable DCD : Data Contact Detect */
+    USBx->GCCFG |= USB_OTG_GCCFG_DCDEN;
+    
+    /* Wait Detect flag or a timeout is happen*/
+    while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0)
+    {
+      /* Check for the Timeout */
+      if((HAL_GetTick() - tickstart ) > 1000)
+      {
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR);
+        return;
+      }
+    }
+    
+    /* Right response got */
+    HAL_Delay(100); 
+    
+    /* Check Detect flag*/
+    if (USBx->GCCFG & USB_OTG_GCCFG_DCDET)
+    {
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION);
+    }
+    
+    /*Primary detection: checks if connected to Standard Downstream Port  
+    (without charging capability) */
+    USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN;
+    USBx->GCCFG |=  USB_OTG_GCCFG_PDEN;
+    HAL_Delay(100); 
+    
+    if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET))
+    {
+      /* Case of Standard Downstream Port */
+      HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT);
+    }
+    else  
+    {
+      /* start secondary detection to check connection to Charging Downstream 
+      Port or Dedicated Charging Port */
+      USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN;
+      USBx->GCCFG |=  USB_OTG_GCCFG_SDEN;
+      HAL_Delay(100); 
+      
+      if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET)
+      { 
+        /* case Dedicated Charging Port  */
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT);
+      }
+      else
+      {
+        /* case Charging Downstream Port  */
+        HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT);
+      }
+    }
+    /* Battery Charging capability discovery finished */
+    HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED);
+  }
+}
+
+/**
+  * @brief  Activate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+
+  hpcd->battery_charging_active = ENABLE; 
+  USBx->GCCFG |= (USB_OTG_GCCFG_BCDEN);
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Deactivate BatteryCharging feature.
+  * @param  hpcd: PCD handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
+{
+  USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;  
+  hpcd->battery_charging_active = DISABLE; 
+  USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN);
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Send LPM message to user layer callback.
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
+{ 
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_LPM_Callback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @brief  Send BatteryCharging message to user layer callback.
+  * @param  hpcd: PCD handle
+  * @param  msg: LPM message
+  * @retval HAL status
+  */
+__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hpcd);
+  UNUSED(msg);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_PCDEx_BCD_Callback could be implemented in the user file
+   */ 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PCD_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_pwr.c

@@ -0,0 +1,676 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_pwr.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   PWR HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Power Controller (PWR) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup PWR PWR
+  * @brief PWR HAL module driver
+  * @{
+  */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+
+/** @defgroup PWR_Private_Defines PWR Private Defines
+  * @{
+  */
+  
+/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
+  * @{
+  */ 
+#define PVD_MODE_IT               ((uint32_t)0x00010000)  /*!< Mask for interruption yielded by PVD threshold crossing */ 
+#define PVD_MODE_EVT              ((uint32_t)0x00020000)  /*!< Mask for event yielded by PVD threshold crossing        */ 
+#define PVD_RISING_EDGE           ((uint32_t)0x00000001)  /*!< Mask for rising edge set as PVD trigger                 */ 
+#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)  /*!< Mask for falling edge set as PVD trigger                */ 
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Functions PWR Exported Functions
+  * @{
+  */
+
+/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
+  *  @brief    Initialization and de-initialization functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Deinitialize the HAL PWR peripheral registers to their default reset values.
+  * @retval None
+  */
+void HAL_PWR_DeInit(void)
+{
+  __HAL_RCC_PWR_FORCE_RESET();
+  __HAL_RCC_PWR_RELEASE_RESET();
+}
+
+/**
+  * @brief Enable access to the backup domain 
+  *        (RTC registers, RTC backup data registers).
+  * @note  After reset, the backup domain is protected against 
+  *        possible unwanted write accesses.
+  * @note  RTCSEL that sets the RTC clock source selection is in the RTC back-up domain.
+  *        In order to set or modify the RTC clock, the backup domain access must be
+  *        disabled. 
+  * @note  LSEON bit that switches on and off the LSE crystal belongs as well to the
+  *        back-up domain.                
+  * @retval None
+  */
+void HAL_PWR_EnableBkUpAccess(void)
+{
+  SET_BIT(PWR->CR1, PWR_CR1_DBP);    
+}
+
+/**
+  * @brief Disable access to the backup domain
+  *        (RTC registers, RTC backup data registers).    
+  * @retval None
+  */
+void HAL_PWR_DisableBkUpAccess(void)
+{
+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);   
+}
+
+
+
+
+/**
+  * @}
+  */
+
+
+
+/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions
+  *  @brief Low Power modes configuration functions
+  *
+@verbatim
+
+ ===============================================================================
+                 ##### Peripheral Control functions #####
+ ===============================================================================
+ 
+     [..]
+     *** PVD configuration ***
+    =========================
+    [..]
+      (+) The PVD is used to monitor the VDD power supply by comparing it to a
+          threshold selected by the PVD Level (PLS[2:0] bits in PWR_CR2 register).
+
+      (+) PVDO flag is available to indicate if VDD/VDDA is higher or lower
+          than the PVD threshold. This event is internally connected to the EXTI
+          line16 and can generate an interrupt if enabled. This is done through
+          __HAL_PVD_EXTI_ENABLE_IT() macro.
+      (+) The PVD is stopped in Standby mode.
+ 
+    
+    *** WakeUp pin configuration ***
+    ================================
+    [..]
+      (+) WakeUp pins are used to wakeup the system from Standby mode or Shutdown mode. 
+          The polarity of these pins can be set to configure event detection on high 
+          level (rising edge) or low level (falling edge).
+
+
+   
+    *** Low Power modes configuration ***
+    =====================================
+    [..]
+      The devices feature 8 low-power modes:
+      (+) Low-power Run mode: core and peripherals are running, main regulator off, low power regulator on.
+      (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running, main and low power regulators on.
+      (+) Low-power Sleep mode: Cortex-M4 core stopped, peripherals kept running, main regulator off, low power regulator on.
+      (+) Stop 0 mode: all clocks are stopped except LSI and LSE, main and low power regulators on.
+      (+) Stop 1 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on.
+      (+) Stop 2 mode: all clocks are stopped except LSI and LSE, main regulator off, low power regulator on, reduced set of waking up IPs compared to Stop 1 mode.      
+      (+) Standby mode with SRAM2: all clocks are stopped except LSI and LSE, SRAM2 content preserved, main regulator off, low power regulator on. 
+      (+) Standby mode without SRAM2: all clocks are stopped except LSI and LSE, main and low power regulators off.
+      (+) Shutdown mode: all clocks are stopped except LSE, main and low power regulators off.
+
+
+   *** Low-power run mode ***
+   ==========================
+    [..]
+      (+) Entry: (from main run mode)
+        (++) set LPR bit with HAL_PWREx_EnableLowPowerRunMode() API after having decreased the system clock below 2 MHz. 
+     
+      (+) Exit:
+        (++) clear LPR bit then wait for REGLP bit to be reset with HAL_PWREx_DisableLowPowerRunMode() API. Only
+             then can the system clock frequency be increased above 2 MHz.
+
+
+   *** Sleep mode / Low-power sleep mode ***
+   =========================================
+    [..]
+      (+) Entry:                                                         
+          The Sleep mode / Low-power Sleep mode is entered thru HAL_PWR_EnterSLEEPMode() API
+          in specifying whether or not the regulator is forced to low-power mode and if exit is interrupt or event-triggered. 
+          (++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).              
+          (++) PWR_LOWPOWERREGULATOR_ON: Low-power sleep (regulator in low power mode).
+          In the latter case, the system clock frequency must have been decreased below 2 MHz beforehand.           
+          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
+          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
+     
+      (+) WFI Exit:
+        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
+             controller (NVIC) or any wake-up event.
+             
+      (+) WFE Exit:
+        (++) Any wake-up event such as an EXTI line configured in event mode.             
+             
+         [..] When exiting the Low-power sleep mode by issuing an interrupt or a wakeup event, 
+             the MCU is in Low-power Run mode. 
+
+   *** Stop 0, Stop 1 and Stop 2 modes ***
+   ===============================
+    [..]
+      (+) Entry:                                                 
+          The Stop 0, Stop 1 or Stop 2 modes are entered thru the following API's:
+          (++) HAL_PWREx_EnterSTOP0Mode() for mode 0 or HAL_PWREx_EnterSTOP1Mode() for mode 1 or for porting reasons HAL_PWR_EnterSTOPMode().
+          (++) HAL_PWREx_EnterSTOP2Mode() for mode 2.  
+      (+) Regulator setting (applicable to HAL_PWR_EnterSTOPMode() only):
+          (++) PWR_MAINREGULATOR_ON
+          (++) PWR_LOWPOWERREGULATOR_ON
+      (+) Exit (interrupt or event-triggered, specified when entering STOP mode):
+          (++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
+          (++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
+          
+      (+) WFI Exit:
+          (++) Any EXTI Line (Internal or External) configured in Interrupt mode.
+          (++) Some specific communication peripherals (USART, LPUART, I2C) interrupts 
+               when programmed in wakeup mode. 
+      (+) WFE Exit:  
+          (++) Any EXTI Line (Internal or External) configured in Event mode.
+       
+       [..]                      
+          When exiting Stop 0 and Stop 1 modes, the MCU is either in Run mode or in Low-power Run mode
+          depending on the LPR bit setting. 
+          When exiting Stop 2 mode, the MCU is in Run mode. 
+
+   *** Standby mode ***
+   ====================
+     [..]
+      The Standby mode offers two options: 
+      (+) option a) all clocks off except LSI and LSE, RRS bit set (keeps voltage regulator in low power mode).
+        SRAM and registers contents are lost except for the SRAM2 content, the RTC registers, RTC backup registers 
+        and Standby circuitry.      
+      (+) option b) all clocks off except LSI and LSE, RRS bit cleared (voltage regulator then disabled).
+        SRAM and register contents are lost except for the RTC registers, RTC backup registers 
+        and Standby circuitry.
+
+      (++) Entry:                                    
+          (+++) The Standby mode is entered thru HAL_PWR_EnterSTANDBYMode() API. 
+                SRAM1 and register contents are lost except for registers in the Backup domain and 
+                Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
+                To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
+                to set RRS bit.   
+          
+      (++) Exit:
+          (+++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
+                external reset in NRST pin, IWDG reset.
+                
+      [..]    After waking up from Standby mode, program execution restarts in the same way as after a Reset.
+          
+
+    *** Shutdown mode ***
+   ======================
+     [..]
+      In Shutdown mode, 
+        voltage regulator is disabled, all clocks are off except LSE, RRS bit is cleared.
+        SRAM and registers contents are lost except for backup domain registers.
+
+      (+) Entry:                                    
+          The Shutdown mode is entered thru HAL_PWREx_EnterSHUTDOWNMode() API.
+          
+      (+) Exit:
+          (++) WKUP pin rising edge, RTC alarm or wakeup, tamper event, time-stamp event, 
+               external reset in NRST pin.
+               
+         [..] After waking up from Shutdown mode, program execution restarts in the same way as after a Reset.
+
+
+   *** Auto-wakeup (AWU) from low-power mode ***
+   =============================================
+    [..]
+      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
+      Wakeup event, a tamper event or a time-stamp event, without depending on
+      an external interrupt (Auto-wakeup mode).
+
+      (+) RTC auto-wakeup (AWU) from the Stop, Standby and Shutdown modes
+  
+
+        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to
+             configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function.
+
+        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
+             is necessary to configure the RTC to detect the tamper or time stamp event using the
+             HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions.
+
+        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to
+              configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer_IT() function.
+
+@endverbatim
+  * @{
+  */
+
+
+
+/**
+  * @brief Configure the voltage threshold detected by the Power Voltage Detector (PVD).
+  * @param sConfigPVD: pointer to a PWR_PVDTypeDef structure that contains the PVD 
+  *        configuration information.
+  * @note Refer to the electrical characteristics of your device datasheet for
+  *         more details about the voltage thresholds corresponding to each
+  *         detection level.
+  * @retval None
+  */
+HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
+  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
+
+  /* Set PLS bits according to PVDLevel value */
+  MODIFY_REG(PWR->CR2, PWR_CR2_PLS, sConfigPVD->PVDLevel);
+  
+  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
+  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
+  __HAL_PWR_PVD_EXTI_DISABLE_IT();
+  __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 
+  __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();
+
+  /* Configure interrupt mode */
+  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_IT();
+  }
+  
+  /* Configure event mode */
+  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
+  }
+  
+  /* Configure the edge */
+  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();
+  }
+  
+  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
+  {
+    __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
+  }
+  
+  return HAL_OK;
+}
+
+
+/**
+  * @brief Enable the Power Voltage Detector (PVD).
+  * @retval None
+  */
+void HAL_PWR_EnablePVD(void)
+{
+  SET_BIT(PWR->CR2, PWR_CR2_PVDE);  
+}
+
+/**
+  * @brief Disable the Power Voltage Detector (PVD).
+  * @retval None
+  */
+void HAL_PWR_DisablePVD(void)
+{
+  CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);   
+}
+
+
+
+
+/**
+  * @brief Enable the WakeUp PINx functionality.
+  * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+  *         This parameter can be one of the following legacy values which set the default polarity 
+  *         i.e. detection on high level (rising edge):
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5
+  *             
+  *         or one of the following value where the user can explicitly specify the enabled pin and
+  *         the chosen polarity:  
+  *           @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW 
+  *           @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW 
+  *           @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW 
+  *           @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
+  *           @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW 
+  * @note  PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.               
+  * @retval None
+  */
+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity)); 
+  
+  /* Specifies the Wake-Up pin polarity for the event detection 
+    (rising or falling edge) */
+  MODIFY_REG(PWR->CR4, (PWR_CR3_EWUP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT)); 
+    
+  /* Enable wake-up pin */
+  SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
+
+    
+}
+
+/**
+  * @brief Disable the WakeUp PINx functionality.
+  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+  *         This parameter can be one of the following values:
+  *           @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 
+  * @retval None
+  */
+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
+{
+  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
+
+  CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx)); 
+}
+
+
+/**
+  * @brief Enter Sleep or Low-power Sleep mode.
+  * @note  In Sleep/Low-power Sleep mode, all I/O pins keep the same state as in Run mode.
+  * @param Regulator: Specifies the regulator state in Sleep/Low-power Sleep mode.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON Low-power Sleep mode (regulator in low-power mode) 
+  * @note  Low-power Sleep mode is entered from Low-power Run mode. Therefore, if not yet 
+  *        in Low-power Run mode before calling HAL_PWR_EnterSLEEPMode() with Regulator set 
+  *        to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the    
+  *        Flash in power-down monde in setting the SLEEP_PD bit in FLASH_ACR register.
+  *        Additionally, the clock frequency must be reduced below 2 MHz.
+  *        Setting SLEEP_PD in FLASH_ACR then appropriately reducing the clock frequency must 
+  *        be done before calling HAL_PWR_EnterSLEEPMode() API. 
+  * @note  When exiting Low-power Sleep mode, the MCU is in Low-power Run mode. To move in 
+  *        Run mode, the user must resort to HAL_PWREx_DisableLowPowerRunMode() API.       
+  * @param SLEEPEntry: Specifies if Sleep mode is entered with WFI or WFE instruction.
+  *           This parameter can be one of the following values:
+  *            @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep mode with WFI instruction
+  *            @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep mode with WFE instruction
+  * @note  When WFI entry is used, tick interrupt have to be disabled if not desired as 
+  *        the interrupt wake up source.   
+  * @retval None
+  */
+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
+
+  /* Set Regulator parameter */
+  if (Regulator == PWR_MAINREGULATOR_ON)
+  {
+    /* If in low-power run mode at this point, exit it */
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))
+    {
+      HAL_PWREx_DisableLowPowerRunMode();  
+    } 
+    /* Regulator now in main mode. */
+  }
+  else
+  {
+    /* If in run mode, first move to low-power run mode.
+       The system clock frequency must be below 2 MHz at this point. */
+    if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF) == RESET)
+    {
+      HAL_PWREx_EnableLowPowerRunMode();  
+    } 
+  } 
+    
+  /* Clear SLEEPDEEP bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+  
+  /* Select SLEEP mode entry -------------------------------------------------*/
+  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
+  {
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __SEV();
+    __WFE();
+    __WFE();
+  }
+
+}
+
+
+/**
+  * @brief Enter Stop mode
+  * @note  This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with legacy code running
+  *        on devices where only "Stop mode" is mentioned with main or low power regulator ON.
+  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.          
+  * @note  All clocks in the VCORE domain are stopped; the PLL, the MSI, 
+  *        the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 
+  *        (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 
+  *        after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 
+  *        only to the peripheral requesting it.
+  *        SRAM1, SRAM2 and register contents are preserved.
+  *        The BOR is available.
+  *        The voltage regulator can be configured either in normal (Stop 0) or low-power mode (Stop 1).  
+  * @note  When exiting Stop 0 or Stop 1 mode by issuing an interrupt or a wakeup event,
+  *         the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
+  *         is set; the MSI oscillator is selected if STOPWUCK is cleared.  
+  * @note  When the voltage regulator operates in low power mode (Stop 1), an additional
+  *         startup delay is incurred when waking up.
+  *         By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
+  *         is higher although the startup time is reduced.
+  * @param Regulator: Specifies the regulator state in Stop mode.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_MAINREGULATOR_ON  Stop 0 mode (main regulator ON)
+  *            @arg @ref PWR_LOWPOWERREGULATOR_ON  Stop 1 mode (low power regulator ON) 
+  * @param STOPEntry: Specifies Stop 0 or Stop 1 mode is entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg @ref PWR_STOPENTRY_WFI  Enter Stop 0 or Stop 1 mode with WFI instruction.
+  *            @arg @ref PWR_STOPENTRY_WFE  Enter Stop 0 or Stop 1 mode with WFE instruction.
+  * @retval None
+  */
+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(Regulator));
+  
+  if(Regulator == PWR_LOWPOWERREGULATOR_ON)
+  {
+    HAL_PWREx_EnterSTOP1Mode(STOPEntry);
+  }
+  else
+  {
+    HAL_PWREx_EnterSTOP0Mode(STOPEntry);
+  }
+}
+
+/**
+  * @brief Enter Standby mode.
+  * @note  In Standby mode, the PLL, the HSI, the MSI and the HSE oscillators are switched 
+  *        off. The voltage regulator is disabled, except when SRAM2 content is preserved
+  *        in which case the regulator is in low-power mode. 
+  *        SRAM1 and register contents are lost except for registers in the Backup domain and 
+  *        Standby circuitry. SRAM2 content can be preserved if the bit RRS is set in PWR_CR3 register. 
+  *        To enable this feature, the user can resort to HAL_PWREx_EnableSRAM2ContentRetention() API 
+  *        to set RRS bit.   
+  *        The BOR is available.  
+  * @note  The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state.
+  *        HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() respectively enable Pull Up and
+  *        Pull Down state, HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() disable the
+  *        same.
+  *        These states are effective in Standby mode only if APC bit is set through
+  *        HAL_PWREx_EnablePullUpPullDownConfig() API.        
+  * @retval None
+  */
+void HAL_PWR_EnterSTANDBYMode(void)
+{
+  /* Set Stand-by mode */
+  MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STANDBY);
+
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM)
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+
+
+/**
+  * @brief Indicate Sleep-On-Exit when returning from Handler mode to Thread mode. 
+  * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.
+  *       Setting this bit is useful when the processor is expected to run only on
+  *       interruptions handling.         
+  * @retval None
+  */
+void HAL_PWR_EnableSleepOnExit(void)
+{
+  /* Set SLEEPONEXIT bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+/**
+  * @brief Disable Sleep-On-Exit feature when returning from Handler mode to Thread mode. 
+  * @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the processor 
+  *       re-enters SLEEP mode when an interruption handling is over.          
+  * @retval None
+  */
+void HAL_PWR_DisableSleepOnExit(void)
+{
+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
+}
+
+
+
+/**
+  * @brief Enable CORTEX M4 SEVONPEND bit. 
+  * @note Set SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.
+  * @retval None
+  */
+void HAL_PWR_EnableSEVOnPend(void)
+{
+  /* Set SEVONPEND bit of Cortex System Control Register */
+  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+/**
+  * @brief Disable CORTEX M4 SEVONPEND bit. 
+  * @note Clear SEVONPEND bit of SCR register. When this bit is set, this causes 
+  *       WFE to wake up when an interrupt moves from inactive to pended.         
+  * @retval None
+  */
+void HAL_PWR_DisableSEVOnPend(void)
+{
+  /* Clear SEVONPEND bit of Cortex System Control Register */
+  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
+}
+
+
+
+
+
+/**
+  * @brief PWR PVD interrupt callback
+  * @retval None
+  */
+__weak void HAL_PWR_PVDCallback(void)
+{
+  /* NOTE : This function should not be modified; when the callback is needed,
+            the HAL_PWR_PVDCallback can be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_PWR_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_rng.c

@@ -0,0 +1,519 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_rng.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   RNG HAL module driver.
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:
+  *           + Initialization/de-initialization functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                     ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      The RNG HAL driver can be used as follows:
+
+      (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro 
+          in HAL_RNG_MspInit().
+      (#) Activate the RNG peripheral using HAL_RNG_Init() function.
+      (#) Wait until the 32-bit Random Number Generator contains a valid 
+          random data using (polling/interrupt) mode.   
+      (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup RNG RNG
+  * @brief RNG HAL module driver.
+  * @{
+  */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup RNG_Private_Constants RNG_Private_Constants
+  * @{
+  */
+#define RNG_TIMEOUT_VALUE     2
+/**
+  * @}
+  */ 
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup RNG_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group1
+ *  @brief   Initialization and de-initialization functions
+ *
+@verbatim
+ ===============================================================================
+          ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize the RNG according to the specified parameters 
+          in the RNG_InitTypeDef and create the associated handle
+      (+) DeInitialize the RNG peripheral
+      (+) Initialize the RNG MSP (MCU Specific Package)
+      (+) DeInitialize the RNG MSP 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the RNG peripheral and initialize the associated handle.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  
+  assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); 
+  
+  __HAL_LOCK(hrng);
+  
+  if(hrng->State == HAL_RNG_STATE_RESET)
+  {  
+    /* Allocate lock resource and initialize it */
+    hrng->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware */
+    HAL_RNG_MspInit(hrng);
+  }
+  
+  /* Change RNG peripheral state */
+  hrng->State = HAL_RNG_STATE_BUSY;
+
+  /* Enable the RNG Peripheral */
+  __HAL_RNG_ENABLE(hrng);
+
+  /* Initialize the RNG state */
+  hrng->State = HAL_RNG_STATE_READY;
+  
+  __HAL_UNLOCK(hrng);
+  
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DeInitialize the RNG peripheral. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng)
+{ 
+  /* Check the RNG handle allocation */
+  if(hrng == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Disable the RNG Peripheral */
+  CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN);
+  
+  /* Clear RNG interrupt status flags */
+  CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS);
+  
+  /* DeInit the low level hardware */
+  HAL_RNG_MspDeInit(hrng);
+  
+  /* Update the RNG state */
+  hrng->State = HAL_RNG_STATE_RESET; 
+
+  /* Release Lock */
+  __HAL_UNLOCK(hrng);
+  
+  /* Return the function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the RNG MSP.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_MspDeInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group2
+ *  @brief    Management functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]  This section provides functions allowing to:
+      (+) Get the 32 bit Random number
+      (+) Get the 32 bit Random number with interrupt enabled
+      (+) Handle RNG interrupt request 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Generate a 32-bit random number.
+  * @note   Each time the random number data is read the RNG_FLAG_DRDY flag 
+  *         is automatically cleared.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @param  random32bit: pointer to generated random number variable if successful.
+  * @retval HAL status
+  */
+
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
+{
+  uint32_t tickstart = 0;    
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process Locked */
+  __HAL_LOCK(hrng); 
+  
+  /* Check RNS peripheral state */
+  if(hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */  
+    hrng->State = HAL_RNG_STATE_BUSY;  
+
+    /* Get tick */
+    tickstart = HAL_GetTick();
+  
+    /* Check if data register contains valid random data */
+    while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET)
+    {
+      if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE)
+      {    
+        hrng->State = HAL_RNG_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hrng);
+      
+        return HAL_TIMEOUT;
+      } 
+    }
+  
+    /* Get a 32bit Random number */
+    hrng->RandomNumber = hrng->Instance->DR;
+    *random32bit = hrng->RandomNumber;
+  
+    hrng->State = HAL_RNG_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+  
+  /* Process Unlocked */
+  __HAL_UNLOCK(hrng);
+
+  return status;
+}
+
+/**
+  * @brief  Generate a 32-bit random number in interrupt mode.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  
+  /* Process Locked */
+  __HAL_LOCK(hrng);
+  
+  /* Check RNG peripheral state */
+  if(hrng->State == HAL_RNG_STATE_READY)
+  {
+    /* Change RNG peripheral state */  
+    hrng->State = HAL_RNG_STATE_BUSY;  
+  
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+    
+    /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+    __HAL_RNG_ENABLE_IT(hrng);
+  }
+  else
+  {
+    /* Process Unlocked */
+    __HAL_UNLOCK(hrng);
+    
+    status = HAL_ERROR;
+  }
+  
+  return status;
+}
+
+/**
+  * @brief  Handle RNG interrupt request.
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User has 
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). 
+  *         The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable 
+  *         the RNG peripheral to reinitialize and restart the RNG.
+  * @note   User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
+  *         or CEIS are set.  
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+
+  */
+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
+{
+  /* RNG clock error interrupt occurred */
+  if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) ||  (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET))
+  { 
+    /* Change RNG peripheral state */
+    hrng->State = HAL_RNG_STATE_ERROR;
+  
+    HAL_RNG_ErrorCallback(hrng);
+    
+    /* Clear the clock error flag */
+    __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI);
+    
+  }
+  
+  /* Check RNG data ready interrupt occurred */    
+  if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET)
+  {
+    /* Generate random number once, so disable the IT */
+    __HAL_RNG_DISABLE_IT(hrng);
+    
+    /* Get the 32bit Random number (DRDY flag automatically cleared) */ 
+    hrng->RandomNumber = hrng->Instance->DR;
+    
+    if(hrng->State != HAL_RNG_STATE_ERROR)
+    {
+      /* Change RNG peripheral state */
+      hrng->State = HAL_RNG_STATE_READY; 
+      
+      /* Data Ready callback */ 
+      HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber);
+    } 
+  }
+} 
+
+/**
+  * @brief  Return generated random number in polling mode (Obsolete).
+  * @note   Use HAL_RNG_GenerateRandomNumber() API instead.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure that contains
+  *                the configuration information for RNG.
+  * @retval random value
+  */
+uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK)
+  {
+    return hrng->RandomNumber; 
+  }
+  else
+  {
+    return 0;
+  }
+}
+
+
+/**
+  * @brief  Return a 32-bit random number with interrupt enabled (Obsolete).
+  * @note   Use HAL_RNG_GenerateRandomNumber_IT() API instead.
+  * @param  hrng: RNG handle
+  * @retval 32-bit random number
+  */
+uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
+{
+  uint32_t random32bit = 0;
+  
+  /* Process locked */
+  __HAL_LOCK(hrng);
+  
+  /* Change RNG peripheral state */  
+  hrng->State = HAL_RNG_STATE_BUSY;  
+  
+  /* Get a 32bit Random number */ 
+  random32bit = hrng->Instance->DR;
+  
+  /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ 
+  __HAL_RNG_ENABLE_IT(hrng); 
+  
+  /* Return the 32 bit random number */   
+  return random32bit;
+}
+
+
+
+/**
+  * @brief  Read latest generated random number. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval random value
+  */
+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
+{
+  return(hrng->RandomNumber);
+}
+
+/**
+  * @brief  Data Ready callback in non-blocking mode. 
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @param  random32bit: generated random value
+  * @retval None
+  */
+__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+  UNUSED(random32bit);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ReadyDataCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  RNG error callback.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval None
+  */
+__weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hrng);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_RNG_ErrorCallback must be implemented in the user file.
+   */
+}
+ 
+/**
+  * @}
+  */
+
+/** @addtogroup RNG_Exported_Functions_Group3
+ *  @brief    Peripheral State functions. 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================  
+    [..]
+    This subsection permits to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the RNG handle state.
+  * @param  hrng: pointer to a RNG_HandleTypeDef structure.
+  * @retval HAL state
+  */
+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng)
+{
+  /* Return RNG handle state */
+  return hrng->State;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+#endif /* HAL_RNG_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_spi_ex.c

@@ -0,0 +1,133 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_spi_ex.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Extended SPI HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          SPI peripheral extended functionalities :
+  *           + IO operation functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SPIEx SPIEx
+  * @brief SPI Extended HAL module driver
+  * @{
+  */
+#ifdef HAL_SPI_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup SPIEx_Private_Constants SPIEx Private Constants
+  * @{
+  */
+#define SPI_FIFO_SIZE       4
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions
+  * @{
+  */
+
+/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions
+ *  @brief   Data transfers functions
+ *
+@verbatim
+  ==============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+ [..]
+    This subsection provides a set of extended functions to manage the SPI
+    data transfers.
+
+    (#) Rx data flush function:
+        (++) HAL_SPIEx_FlushRxFifo()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Flush the RX fifo.
+  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
+  *               the configuration information for the specified SPI module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi)
+{
+  __IO uint32_t tmpreg;
+  uint8_t  count = 0;
+  while((hspi->Instance->SR & SPI_FLAG_FRLVL) !=  SPI_FRLVL_EMPTY)
+  {
+    count++;
+    tmpreg = hspi->Instance->DR;
+    UNUSED(tmpreg); /* To avoid GCC warning */
+    if(count == SPI_FIFO_SIZE)
+    {
+      return HAL_TIMEOUT;
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_hal_uart_ex.c

@@ -0,0 +1,462 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit, 
+  8-bit or 9-bit), the possible UART formats are listed in the 
+  following table.
+  
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart: UART handle.
+  * @param Polarity: select the driver enable polarity.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime: Driver Enable assertion time:
+  *                         5-bit value defining the time between the activation of the DE (Driver Enable)
+  *                         signal and the beginning of the start bit. It is expressed in sample time
+  *                         units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime: Driver Enable deassertion time:
+  *                         5-bit value defining the time between the end of the last stop bit, in a
+  *                         transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *                         It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *                         oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime)
+{
+  uint32_t temp = 0x0;
+
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if(huart->State == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+  }
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  if(huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT|USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->State to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+ *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_UARTEx_EnableClockStopMode() API enables the UART clock (HSI or LSE only) during stop mode
+     (+) HAL_UARTEx_DisableClockStopMode() API disables the above functionality
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_WakeupCallback() called upon UART wakeup interrupt
+
+
+@endverbatim
+  * @{
+  */
+
+
+
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode, 
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart: UART handle.
+  * @param AddressLength: this parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if(huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->State to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @param huart: UART handle.
+  * @param WakeUpSelection: address match, Start Bit detection or RXNE bit status.
+  * This parameter can be one of the following values:
+  *      @arg @ref UART_WAKEUP_ON_ADDRESS
+  *      @arg @ref UART_WAKEUP_ON_STARTBIT
+  *      @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Wait until REACK flag is set */
+  if(UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->State = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Set UESM bit */
+  SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  huart->State = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart: UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->State = HAL_UART_STATE_BUSY;
+
+  /* Clear UESM bit */
+  CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  huart->State = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart: UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart: UART handle.
+  * @param WakeUpSelection: UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32L4xx_HAL_Driver/Src/stm32l4xx_ll_sdmmc.c

@@ -0,0 +1,496 @@
+/**
+  ******************************************************************************
+  * @file    stm32l4xx_ll_sdmmc.c
+  * @author  MCD Application Team
+  * @version V1.3.0
+  * @date    29-January-2016
+  * @brief   SDMMC Low Layer HAL module driver.  
+  *          This file provides firmware functions to manage the following 
+  *          functionalities of the SDMMC peripheral:
+  *           + Initialization/de-initialization functions
+  *           + I/O operation functions
+  *           + Peripheral Control functions 
+  *           + Peripheral State functions
+  *         
+  @verbatim
+  ==============================================================================
+                       ##### SDMMC peripheral features #####
+  ==============================================================================        
+    [..] The SD/SDMMC MMC card host interface (SDMMC) provides an interface between the APB2
+         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDMMC cards and CE-ATA
+         devices.
+    
+    [..] The SDMMC features include the following:
+         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
+             for three different data bus modes: 1-bit (default), 4-bit and 8-bit
+         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
+         (+) Full compliance with SD Memory Card Specifications Version 2.0
+         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
+             different data bus modes: 1-bit (default) and 4-bit
+         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
+             Rev1.1)
+         (+) Data transfer up to 48 MHz for the 8 bit mode
+         (+) Data and command output enable signals to control external bidirectional drivers.
+                 
+   
+                           ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      This driver is a considered as a driver of service for external devices drivers 
+      that interfaces with the SDMMC peripheral.
+      According to the device used (SD card/ MMC card / SDMMC card ...), a set of APIs 
+      is used in the device's driver to perform SDMMC operations and functionalities.
+   
+      This driver is almost transparent for the final user, it is only used to implement other
+      functionalities of the external device.
+   
+    [..]
+      (+) The SDMMC clock (SDMMCCLK = 48 MHz) is coming from a specific output (MSI, PLLUSB1CLK,
+          PLLUSB2CLK). Before start working with SDMMC peripheral make sure that the
+          PLL is well configured.
+          The SDMMC peripheral uses two clock signals:
+          (++) SDMMC adapter clock (SDMMCCLK = 48 MHz)
+          (++) APB2 bus clock (PCLK2)
+       
+          -@@- PCLK2 and SDMMC_CK clock frequencies must respect the following condition:
+               Frequency(PCLK2) >= (3 / 8 x Frequency(SDMMC_CK))
+  
+      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDMMC
+          peripheral.
+
+      (+) Enable the Power ON State using the SDMMC_PowerState_ON(SDMMCx) 
+          function and disable it using the function SDMMC_PowerState_OFF(SDMMCx).
+                
+      (+) Enable/Disable the clock using the __SDMMC_ENABLE()/__SDMMC_DISABLE() macros.
+  
+      (+) Enable/Disable the peripheral interrupts using the macros __SDMMC_ENABLE_IT(hSDMMC, IT) 
+          and __SDMMC_DISABLE_IT(hSDMMC, IT) if you need to use interrupt mode. 
+  
+      (+) When using the DMA mode 
+          (++) Configure the DMA in the MSP layer of the external device
+          (++) Active the needed channel Request 
+          (++) Enable the DMA using __SDMMC_DMA_ENABLE() macro or Disable it using the macro
+               __SDMMC_DMA_DISABLE().
+  
+      (+) To control the CPSM (Command Path State Machine) and send 
+          commands to the card use the SDMMC_SendCommand(SDMMCx), 
+          SDMMC_GetCommandResponse() and SDMMC_GetResponse() functions. First, user has
+          to fill the command structure (pointer to SDMMC_CmdInitTypeDef) according 
+          to the selected command to be sent.
+          The parameters that should be filled are:
+           (++) Command Argument
+           (++) Command Index
+           (++) Command Response type
+           (++) Command Wait
+           (++) CPSM Status (Enable or Disable).
+  
+          -@@- To check if the command is well received, read the SDMMC_CMDRESP
+              register using the SDMMC_GetCommandResponse().
+              The SDMMC responses registers (SDMMC_RESP1 to SDMMC_RESP2), use the
+              SDMMC_GetResponse() function.
+  
+      (+) To control the DPSM (Data Path State Machine) and send/receive 
+           data to/from the card use the SDMMC_DataConfig(), SDMMC_GetDataCounter(), 
+          SDMMC_ReadFIFO(), SDMMC_WriteFIFO() and SDMMC_GetFIFOCount() functions.
+  
+    *** Read Operations ***
+    =======================
+    [..]
+      (#) First, user has to fill the data structure (pointer to
+          SDMMC_DataInitTypeDef) according to the selected data type to be received.
+          The parameters that should be filled are:
+           (++) Data TimeOut
+           (++) Data Length
+           (++) Data Block size
+           (++) Data Transfer direction: should be from card (To SDMMC)
+           (++) Data Transfer mode
+           (++) DPSM Status (Enable or Disable)
+                                     
+      (#) Configure the SDMMC resources to receive the data from the card
+          according to selected transfer mode (Refer to Step 8, 9 and 10).
+  
+      (#) Send the selected Read command (refer to step 11).
+                    
+      (#) Use the SDMMC flags/interrupts to check the transfer status.
+  
+    *** Write Operations ***
+    ========================
+    [..]
+     (#) First, user has to fill the data structure (pointer to
+         SDMMC_DataInitTypeDef) according to the selected data type to be received.
+         The parameters that should be filled are:
+          (++) Data TimeOut
+          (++) Data Length
+          (++) Data Block size
+          (++) Data Transfer direction:  should be to card (To CARD)
+          (++) Data Transfer mode
+          (++) DPSM Status (Enable or Disable)
+  
+     (#) Configure the SDMMC resources to send the data to the card according to 
+         selected transfer mode.
+                     
+     (#) Send the selected Write command.
+                    
+     (#) Use the SDMMC flags/interrupts to check the transfer status.
+  
+  @endverbatim
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32l4xx_hal.h"
+
+/** @addtogroup STM32L4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup SDMMC_LL SDMMC Low Layer
+  * @brief Low layer module for SD
+  * @{
+  */
+
+#if defined (HAL_SD_MODULE_ENABLED)
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup SDMMC_LL_Exported_Functions SDMMC Low Layer Exported Functions
+  * @{
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group1 Initialization de-initialization functions 
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+              ##### Initialization/de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDMMC according to the specified
+  *         parameters in the SDMMC_InitTypeDef and initialize the associated handle.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Init: SDMMC initialization structure   
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_ALL_INSTANCE(SDMMCx));
+  assert_param(IS_SDMMC_CLOCK_EDGE(Init.ClockEdge)); 
+  assert_param(IS_SDMMC_CLOCK_BYPASS(Init.ClockBypass));
+  assert_param(IS_SDMMC_CLOCK_POWER_SAVE(Init.ClockPowerSave));
+  assert_param(IS_SDMMC_BUS_WIDE(Init.BusWide));
+  assert_param(IS_SDMMC_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
+  assert_param(IS_SDMMC_CLKDIV(Init.ClockDiv));
+  
+  /* Set SDMMC configuration parameters */
+  /* Write to SDMMC CLKCR */
+  MODIFY_REG(SDMMCx->CLKCR, CLKCR_CLEAR_MASK, Init.ClockEdge           |\
+                                              Init.ClockBypass         |\
+                                              Init.ClockPowerSave      |\
+                                              Init.BusWide             |\
+                                              Init.HardwareFlowControl |\
+                                              Init.ClockDiv);  
+
+  return HAL_OK;
+}
+
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group2 IO operation functions 
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### I/O operation functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to manage the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
+{
+  /* Read data from Rx FIFO */ 
+  return (SDMMCx->FIFO);
+}
+
+/**
+  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  pWriteData: pointer to data to write
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
+{ 
+  /* Write data to FIFO */ 
+  SDMMCx->FIFO = *pWriteData;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
+ *  @brief   management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================  
+    [..]
+    This subsection provides a set of functions allowing to control the SDMMC data 
+    transfers.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set SDMMC Power state to ON. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
+{  
+  /* Set power state to ON */ 
+  SDMMCx->POWER = SDMMC_POWER_PWRCTRL;
+  
+  return HAL_OK; 
+}
+
+/**
+  * @brief  Set SDMMC Power state to OFF. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
+{
+  /* Set power state to OFF */
+  SDMMCx->POWER = (uint32_t)0x00000000;
+  
+  return HAL_OK;
+}
+
+/**
+  * @brief  Get SDMMC Power state. 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON 
+  */
+uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx)  
+{
+  return (SDMMCx->POWER & SDMMC_POWER_PWRCTRL);
+}
+
+/**
+  * @brief  Configure the SDMMC command path according to the specified parameters in
+  *         SDMMC_CmdInitTypeDef structure and send the command 
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @param  Command: pointer to a SDMMC_CmdInitTypeDef structure that contains 
+  *         the configuration information for the SDMMC command
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_CMD_INDEX(Command->CmdIndex));
+  assert_param(IS_SDMMC_RESPONSE(Command->Response));
+  assert_param(IS_SDMMC_WAIT(Command->WaitForInterrupt));
+  assert_param(IS_SDMMC_CPSM(Command->CPSM));
+
+  /* Set the SDMMC Argument value */
+  SDMMCx->ARG = Command->Argument;
+
+  /* Set SDMMC command parameters */
+  /* Write to SDMMC CMD register */
+  MODIFY_REG(SDMMCx->CMD, CMD_CLEAR_MASK, Command->CmdIndex         |\
+                                          Command->Response         |\
+                                          Command->WaitForInterrupt |\
+                                          Command->CPSM); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @brief  Return the command index of last command for which response received
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Command index of the last command response received
+  */
+uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
+{
+  return (uint8_t)(SDMMCx->RESPCMD);
+}
+
+
+/**
+  * @brief  Return the response received from the card for the last command
+  * @param  SDMMCx: Pointer to SDMMC register base    
+  * @param  Response: Specifies the SDMMC response register. 
+  *          This parameter can be one of the following values:
+  *            @arg SDMMC_RESP1: Response Register 1
+  *            @arg SDMMC_RESP2: Response Register 2
+  *            @arg SDMMC_RESP3: Response Register 3
+  *            @arg SDMMC_RESP4: Response Register 4  
+  * @retval The Corresponding response register value
+  */
+uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDMMC_RESP(Response));
+  
+  /* Get the response */
+  tmp = (uint32_t)&(SDMMCx->RESP1) + Response;
+  
+  return (*(__IO uint32_t *) tmp);
+}  
+
+/**
+  * @brief  Configure the SDMMC data path according to the specified 
+  *         parameters in the SDMMC_DataInitTypeDef.
+  * @param  SDMMCx: Pointer to SDMMC register base  
+  * @param  Data : pointer to a SDMMC_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDMMC data.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef SDMMC_DataConfig(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_DATA_LENGTH(Data->DataLength));
+  assert_param(IS_SDMMC_BLOCK_SIZE(Data->DataBlockSize));
+  assert_param(IS_SDMMC_TRANSFER_DIR(Data->TransferDir));
+  assert_param(IS_SDMMC_TRANSFER_MODE(Data->TransferMode));
+  assert_param(IS_SDMMC_DPSM(Data->DPSM));
+
+  /* Set the SDMMC Data TimeOut value */
+  SDMMCx->DTIMER = Data->DataTimeOut;
+
+  /* Set the SDMMC DataLength value */
+  SDMMCx->DLEN = Data->DataLength;
+
+  /* Set the SDMMC data configuration parameters */
+  /* Write to SDMMC DCTRL */
+  MODIFY_REG(SDMMCx->DCTRL, DCTRL_CLEAR_MASK, Data->DataBlockSize |\
+                                              Data->TransferDir   |\
+                                              Data->TransferMode  |\
+                                              Data->DPSM);
+
+  return HAL_OK;
+
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  SDMMCx: Pointer to SDMMC register base
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->DCOUNT);
+}
+
+/**
+  * @brief  Get the FIFO data
+  * @param  SDMMCx: Pointer to SDMMC register base 
+  * @retval Data received
+  */
+uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
+{
+  return (SDMMCx->FIFO);
+}
+
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDMMCx: Pointer to SDMMC register base   
+  * @param  SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
+  *            @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
+  * @retval None
+  */
+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDMMC_READWAIT_MODE(SDMMC_ReadWaitMode));
+  
+  /* Set SDMMC read wait mode */
+  MODIFY_REG(SDMMCx->DCTRL, SDMMC_DCTRL_RWMOD, SDMMC_ReadWaitMode); 
+  
+  return HAL_OK;  
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* (HAL_SD_MODULE_ENABLED) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/