Import STM32Cube_FW_H7_V1.6.0 on 02-Dec-2019.

CMSIS/STM32H7xx/Include/stm32h7xx.h

@@ -59,7 +59,8 @@
   */
 
 #if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \
-    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx)
+    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \
+    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx) && !defined (STM32H7B0xxQ)
   /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */
   /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */
   /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */
@@ -68,6 +69,11 @@
   /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */
   /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */
   /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */
+  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */
+  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */
+  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */
+  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */
+  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */
 #endif
 
 /*  Tip: To avoid modifying this file each time you need to switch between these
@@ -88,10 +94,10 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V1.5.0
+  * @brief CMSIS Device version number V1.7.0
   */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x05) /*!< [23:16] sub1 version */
+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x07) /*!< [23:16] sub1 version */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
@@ -123,6 +129,18 @@
   #include "stm32h747xx.h"
 #elif defined(STM32H757xx)
   #include "stm32h757xx.h"
+#elif defined(STM32H7B0xx)
+  #include "stm32h7b0xx.h"
+#elif defined(STM32H7B0xxQ)
+  #include "stm32h7b0xxq.h"
+#elif defined(STM32H7A3xx)
+  #include "stm32h7a3xx.h"
+#elif defined(STM32H7B3xx)
+  #include "stm32h7b3xx.h"
+#elif defined(STM32H7A3xxQ)
+  #include "stm32h7a3xxq.h"
+#elif defined(STM32H7B3xxQ)
+  #include "stm32h7b3xxq.h"
 #else
  #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"
 #endif

CMSIS/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xx.s

@@ -0,0 +1,604 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h7a3xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+                DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+                DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+                DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI,PSSI
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+                DCD     BDMA2_Channel0_IRQHandler         ;  BDMA2 Channel 0 global Interrupt
+                DCD     BDMA2_Channel1_IRQHandler         ;  BDMA2 Channel 1 global Interrupt
+                DCD     BDMA2_Channel2_IRQHandler         ;  BDMA2 Channel 2 global Interrupt
+                DCD     BDMA2_Channel3_IRQHandler         ;  BDMA2 Channel 3 global Interrupt
+                DCD     BDMA2_Channel4_IRQHandler         ;  BDMA2 Channel 4 global Interrupt
+                DCD     BDMA2_Channel5_IRQHandler         ;  BDMA2 Channel 5 global Interrupt
+                DCD     BDMA2_Channel6_IRQHandler         ;  BDMA2 Channel 6 global Interrupt
+                DCD     BDMA2_Channel7_IRQHandler         ;  BDMA2 Channel 7 global Interrupt
+                DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+                DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+                DCD     USART10_IRQHandler                ;  USART10 global interrupt
+                DCD     LPUART1_IRQHandler                ;  LPUART1 interrupt
+                DCD     0                                 ;  Reserved
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt
+                DCD     ECC_IRQHandler                    ;  ECC_IRQHandler
+                DCD     0                                 ;  Reserved
+                DCD     DTS_IRQHandler                    ;  DTS
+                DCD     0                                 ;  Reserved
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+                DCD     OCTOSPI2_IRQHandler               ;  OCTOSPI2
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     GFXMMU_IRQHandler                 ;  GFXMMU
+                DCD     BDMA1_IRQHandler                  ;  BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  DFSDM2_IRQHandler                 [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]
+                EXPORT  DFSDM1_FLT4_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT5_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT6_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler              [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]
+                EXPORT  TIM15_IRQHandler                  [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDMA_IRQHandler                   [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  HSEM1_IRQHandler                  [WEAK]
+                EXPORT  DAC2_IRQHandler                   [WEAK]
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]
+                EXPORT  BDMA2_Channel0_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel4_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel5_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel6_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel7_IRQHandler         [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                  [WEAK]
+                EXPORT  USART10_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]
+                EXPORT  DTS_IRQHandler                    [WEAK]
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK]
+                EXPORT  OCTOSPI2_IRQHandler               [WEAK]
+                EXPORT  GFXMMU_IRQHandler                 [WEAK]
+                EXPORT  BDMA1_IRQHandler                  [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32H7xx/Source/Templates/arm/startup_stm32h7a3xxq.s

@@ -0,0 +1,604 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h7a3xxq.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+                DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+                DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+                DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI,PSSI
+                DCD     0                                 ; Reserved
+                DCD     RNG_IRQHandler                    ; Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+                DCD     BDMA2_Channel0_IRQHandler         ;  BDMA2 Channel 0 global Interrupt
+                DCD     BDMA2_Channel1_IRQHandler         ;  BDMA2 Channel 1 global Interrupt
+                DCD     BDMA2_Channel2_IRQHandler         ;  BDMA2 Channel 2 global Interrupt
+                DCD     BDMA2_Channel3_IRQHandler         ;  BDMA2 Channel 3 global Interrupt
+                DCD     BDMA2_Channel4_IRQHandler         ;  BDMA2 Channel 4 global Interrupt
+                DCD     BDMA2_Channel5_IRQHandler         ;  BDMA2 Channel 5 global Interrupt
+                DCD     BDMA2_Channel6_IRQHandler         ;  BDMA2 Channel 6 global Interrupt
+                DCD     BDMA2_Channel7_IRQHandler         ;  BDMA2 Channel 7 global Interrupt
+                DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+                DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+                DCD     USART10_IRQHandler                ;  USART10 global interrupt
+                DCD     LPUART1_IRQHandler                ;  LPUART1 interrupt
+                DCD     0                                 ;  Reserved
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt
+                DCD     ECC_IRQHandler                    ;  ECC_IRQHandler
+                DCD     0                                 ;  Reserved
+                DCD     DTS_IRQHandler                    ;  DTS
+                DCD     0                                 ;  Reserved
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+                DCD     OCTOSPI2_IRQHandler               ;  OCTOSPI2
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     GFXMMU_IRQHandler                 ;  GFXMMU
+                DCD     BDMA1_IRQHandler                  ;  BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  DFSDM2_IRQHandler                 [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]
+                EXPORT  DFSDM1_FLT4_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT5_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT6_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler              [WEAK]
+                EXPORT  RNG_IRQHandler                    [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]
+                EXPORT  TIM15_IRQHandler                  [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDMA_IRQHandler                   [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  HSEM1_IRQHandler                  [WEAK]
+                EXPORT  DAC2_IRQHandler                   [WEAK]
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]
+                EXPORT  BDMA2_Channel0_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel4_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel5_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel6_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel7_IRQHandler         [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                  [WEAK]
+                EXPORT  USART10_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]
+                EXPORT  DTS_IRQHandler                    [WEAK]
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK]
+                EXPORT  OCTOSPI2_IRQHandler               [WEAK]
+                EXPORT  GFXMMU_IRQHandler                 [WEAK]
+                EXPORT  BDMA1_IRQHandler                  [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xx.s

@@ -0,0 +1,610 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h7b0xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+                DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+                DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+                DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI,PSSI
+                DCD     CRYP_IRQHandler                   ; CRYP crypto
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+                DCD     BDMA2_Channel0_IRQHandler         ;  BDMA2 Channel 0 global Interrupt
+                DCD     BDMA2_Channel1_IRQHandler         ;  BDMA2 Channel 1 global Interrupt
+                DCD     BDMA2_Channel2_IRQHandler         ;  BDMA2 Channel 2 global Interrupt
+                DCD     BDMA2_Channel3_IRQHandler         ;  BDMA2 Channel 3 global Interrupt
+                DCD     BDMA2_Channel4_IRQHandler         ;  BDMA2 Channel 4 global Interrupt
+                DCD     BDMA2_Channel5_IRQHandler         ;  BDMA2 Channel 5 global Interrupt
+                DCD     BDMA2_Channel6_IRQHandler         ;  BDMA2 Channel 6 global Interrupt
+                DCD     BDMA2_Channel7_IRQHandler         ;  BDMA2 Channel 7 global Interrupt
+                DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+                DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+                DCD     USART10_IRQHandler                ;  USART10 global interrupt
+                DCD     LPUART1_IRQHandler                ;  LPUART1 interrupt
+                DCD     0                                 ;  Reserved
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt
+                DCD     ECC_IRQHandler                    ;  ECC_IRQHandler
+                DCD     0                                 ;  Reserved
+                DCD     DTS_IRQHandler                    ;  DTS
+                DCD     0                                 ;  Reserved
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+                DCD     OCTOSPI2_IRQHandler               ;  OCTOSPI2
+                DCD     OTFDEC1_IRQHandler                ;  OTFDEC1
+                DCD     OTFDEC2_IRQHandler                ;  OTFDEC2
+                DCD     GFXMMU_IRQHandler                 ;  GFXMMU
+                DCD     BDMA1_IRQHandler                  ;  BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  DFSDM2_IRQHandler                 [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]
+                EXPORT  DFSDM1_FLT4_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT5_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT6_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler              [WEAK]
+                EXPORT  CRYP_IRQHandler                   [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]
+                EXPORT  TIM15_IRQHandler                  [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDMA_IRQHandler                   [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  HSEM1_IRQHandler                  [WEAK]
+                EXPORT  DAC2_IRQHandler                   [WEAK]
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]
+                EXPORT  BDMA2_Channel0_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel4_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel5_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel6_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel7_IRQHandler         [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                  [WEAK]
+                EXPORT  USART10_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]
+                EXPORT  DTS_IRQHandler                    [WEAK]
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK]
+                EXPORT  OCTOSPI2_IRQHandler               [WEAK]
+                EXPORT  OTFDEC1_IRQHandler                [WEAK]
+                EXPORT  OTFDEC2_IRQHandler                [WEAK]
+                EXPORT  GFXMMU_IRQHandler                 [WEAK]
+                EXPORT  BDMA1_IRQHandler                  [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32H7xx/Source/Templates/arm/startup_stm32h7b0xxq.s

@@ -0,0 +1,610 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h7b0xxq.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+                DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+                DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+                DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI,PSSI
+                DCD     CRYP_IRQHandler                   ; CRYP crypto
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+                DCD     BDMA2_Channel0_IRQHandler         ;  BDMA2 Channel 0 global Interrupt
+                DCD     BDMA2_Channel1_IRQHandler         ;  BDMA2 Channel 1 global Interrupt
+                DCD     BDMA2_Channel2_IRQHandler         ;  BDMA2 Channel 2 global Interrupt
+                DCD     BDMA2_Channel3_IRQHandler         ;  BDMA2 Channel 3 global Interrupt
+                DCD     BDMA2_Channel4_IRQHandler         ;  BDMA2 Channel 4 global Interrupt
+                DCD     BDMA2_Channel5_IRQHandler         ;  BDMA2 Channel 5 global Interrupt
+                DCD     BDMA2_Channel6_IRQHandler         ;  BDMA2 Channel 6 global Interrupt
+                DCD     BDMA2_Channel7_IRQHandler         ;  BDMA2 Channel 7 global Interrupt
+                DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+                DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+                DCD     USART10_IRQHandler                ;  USART10 global interrupt
+                DCD     LPUART1_IRQHandler                ;  LPUART1 interrupt
+                DCD     0                                 ;  Reserved
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt
+                DCD     ECC_IRQHandler                    ;  ECC_IRQHandler
+                DCD     0                                 ;  Reserved
+                DCD     DTS_IRQHandler                    ;  DTS
+                DCD     0                                 ;  Reserved
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+                DCD     OCTOSPI2_IRQHandler               ;  OCTOSPI2
+                DCD     OTFDEC1_IRQHandler                ;  OTFDEC1
+                DCD     OTFDEC2_IRQHandler                ;  OTFDEC2
+                DCD     GFXMMU_IRQHandler                 ;  GFXMMU
+                DCD     BDMA1_IRQHandler                  ;  BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  DFSDM2_IRQHandler                 [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]
+                EXPORT  DFSDM1_FLT4_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT5_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT6_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler              [WEAK]
+                EXPORT  CRYP_IRQHandler                   [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]
+                EXPORT  TIM15_IRQHandler                  [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDMA_IRQHandler                   [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  HSEM1_IRQHandler                  [WEAK]
+                EXPORT  DAC2_IRQHandler                   [WEAK]
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]
+                EXPORT  BDMA2_Channel0_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel4_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel5_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel6_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel7_IRQHandler         [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                  [WEAK]
+                EXPORT  USART10_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]
+                EXPORT  DTS_IRQHandler                    [WEAK]
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK]
+                EXPORT  OCTOSPI2_IRQHandler               [WEAK]
+                EXPORT  OTFDEC1_IRQHandler                [WEAK]
+                EXPORT  OTFDEC2_IRQHandler                [WEAK]
+                EXPORT  GFXMMU_IRQHandler                 [WEAK]
+                EXPORT  BDMA1_IRQHandler                  [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xx.s

@@ -0,0 +1,610 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h7b3xx.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+                DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+                DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+                DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI,PSSI
+                DCD     CRYP_IRQHandler                   ; CRYP crypto
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+                DCD     BDMA2_Channel0_IRQHandler         ;  BDMA2 Channel 0 global Interrupt
+                DCD     BDMA2_Channel1_IRQHandler         ;  BDMA2 Channel 1 global Interrupt
+                DCD     BDMA2_Channel2_IRQHandler         ;  BDMA2 Channel 2 global Interrupt
+                DCD     BDMA2_Channel3_IRQHandler         ;  BDMA2 Channel 3 global Interrupt
+                DCD     BDMA2_Channel4_IRQHandler         ;  BDMA2 Channel 4 global Interrupt
+                DCD     BDMA2_Channel5_IRQHandler         ;  BDMA2 Channel 5 global Interrupt
+                DCD     BDMA2_Channel6_IRQHandler         ;  BDMA2 Channel 6 global Interrupt
+                DCD     BDMA2_Channel7_IRQHandler         ;  BDMA2 Channel 7 global Interrupt
+                DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+                DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+                DCD     USART10_IRQHandler                ;  USART10 global interrupt
+                DCD     LPUART1_IRQHandler                ;  LPUART1 interrupt
+                DCD     0                                 ;  Reserved
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt
+                DCD     ECC_IRQHandler                    ;  ECC_IRQHandler
+                DCD     0                                 ;  Reserved
+                DCD     DTS_IRQHandler                    ;  DTS
+                DCD     0                                 ;  Reserved
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+                DCD     OCTOSPI2_IRQHandler               ;  OCTOSPI2
+                DCD     OTFDEC1_IRQHandler                ;  OTFDEC1
+                DCD     OTFDEC2_IRQHandler                ;  OTFDEC2
+                DCD     GFXMMU_IRQHandler                 ;  GFXMMU
+                DCD     BDMA1_IRQHandler                  ;  BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  DFSDM2_IRQHandler                 [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]
+                EXPORT  DFSDM1_FLT4_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT5_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT6_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler              [WEAK]
+                EXPORT  CRYP_IRQHandler                   [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]
+                EXPORT  TIM15_IRQHandler                  [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDMA_IRQHandler                   [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  HSEM1_IRQHandler                  [WEAK]
+                EXPORT  DAC2_IRQHandler                   [WEAK]
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]
+                EXPORT  BDMA2_Channel0_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel4_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel5_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel6_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel7_IRQHandler         [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                  [WEAK]
+                EXPORT  USART10_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]
+                EXPORT  DTS_IRQHandler                    [WEAK]
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK]
+                EXPORT  OCTOSPI2_IRQHandler               [WEAK]
+                EXPORT  OTFDEC1_IRQHandler                [WEAK]
+                EXPORT  OTFDEC2_IRQHandler                [WEAK]
+                EXPORT  GFXMMU_IRQHandler                 [WEAK]
+                EXPORT  BDMA1_IRQHandler                  [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32H7xx/Source/Templates/arm/startup_stm32h7b3xxq.s

@@ -0,0 +1,610 @@
+;******************** (C) COPYRIGHT 2019 STMicroelectronics ********************
+;* File Name          : startup_stm32h7b3xxq.s
+;* @author  MCD Application Team
+;* Description        : STM32H7xx devices vector table for MDK-ARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the Cortex-M processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>
+;******************************************************************************
+;* @attention
+;*
+;* Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+; <h> Stack Configuration
+;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+; <h> Heap Configuration
+;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; </h>
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp                      ; Top of Stack
+                DCD     Reset_Handler                     ; Reset Handler
+                DCD     NMI_Handler                       ; NMI Handler
+                DCD     HardFault_Handler                 ; Hard Fault Handler
+                DCD     MemManage_Handler                 ; MPU Fault Handler
+                DCD     BusFault_Handler                  ; Bus Fault Handler
+                DCD     UsageFault_Handler                ; Usage Fault Handler
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     SVC_Handler                       ; SVCall Handler
+                DCD     DebugMon_Handler                  ; Debug Monitor Handler
+                DCD     0                                 ; Reserved
+                DCD     PendSV_Handler                    ; PendSV Handler
+                DCD     SysTick_Handler                   ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog interrupt
+                DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+                DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+                DCD     FLASH_IRQHandler                  ; FLASH
+                DCD     RCC_IRQHandler                    ; RCC
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2
+                DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+                DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+                DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+                DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+                DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+                DCD     TIM1_UP_IRQHandler                ; TIM1 Update Interrupt
+                DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+                DCD     TIM2_IRQHandler                   ; TIM2
+                DCD     TIM3_IRQHandler                   ; TIM3
+                DCD     TIM4_IRQHandler                   ; TIM4
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+                DCD     SPI1_IRQHandler                   ; SPI1
+                DCD     SPI2_IRQHandler                   ; SPI2
+                DCD     USART1_IRQHandler                 ; USART1
+                DCD     USART2_IRQHandler                 ; USART2
+                DCD     USART3_IRQHandler                 ; USART3
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+                DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+                DCD     FMC_IRQHandler                    ; FMC
+                DCD     SDMMC1_IRQHandler                 ; SDMMC1
+                DCD     TIM5_IRQHandler                   ; TIM5
+                DCD     SPI3_IRQHandler                   ; SPI3
+                DCD     UART4_IRQHandler                  ; UART4
+                DCD     UART5_IRQHandler                  ; UART5
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+                DCD     TIM7_IRQHandler                   ; TIM7
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+                DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+                DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+                DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+                DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+                DCD     USART6_IRQHandler                 ; USART6
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+                DCD     DCMI_PSSI_IRQHandler              ; DCMI,PSSI
+                DCD     CRYP_IRQHandler                   ; CRYP crypto
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                DCD     UART7_IRQHandler                  ; UART7
+                DCD     UART8_IRQHandler                  ; UART8
+                DCD     SPI4_IRQHandler                   ; SPI4
+                DCD     SPI5_IRQHandler                   ; SPI5
+                DCD     SPI6_IRQHandler                   ; SPI6
+                DCD     SAI1_IRQHandler                   ; SAI1
+                DCD     LTDC_IRQHandler                   ; LTDC
+                DCD     LTDC_ER_IRQHandler                ; LTDC error
+                DCD     DMA2D_IRQHandler                  ; DMA2D
+                DCD     SAI2_IRQHandler                   ; SAI2
+                DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+                DCD     LPTIM1_IRQHandler                 ; LPTIM1
+                DCD     CEC_IRQHandler                    ; HDMI_CEC
+                DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+                DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+                DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     0                                 ; Reserved
+                DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     0                                 ;  Reserved
+                DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+                DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+                DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+                DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+                DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+                DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+                DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+                DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+                DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+                DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+                DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+                DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+                DCD     0                                 ;  Reserved
+                DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+                DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+                DCD     BDMA2_Channel0_IRQHandler         ;  BDMA2 Channel 0 global Interrupt
+                DCD     BDMA2_Channel1_IRQHandler         ;  BDMA2 Channel 1 global Interrupt
+                DCD     BDMA2_Channel2_IRQHandler         ;  BDMA2 Channel 2 global Interrupt
+                DCD     BDMA2_Channel3_IRQHandler         ;  BDMA2 Channel 3 global Interrupt
+                DCD     BDMA2_Channel4_IRQHandler         ;  BDMA2 Channel 4 global Interrupt
+                DCD     BDMA2_Channel5_IRQHandler         ;  BDMA2 Channel 5 global Interrupt
+                DCD     BDMA2_Channel6_IRQHandler         ;  BDMA2 Channel 6 global Interrupt
+                DCD     BDMA2_Channel7_IRQHandler         ;  BDMA2 Channel 7 global Interrupt
+                DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+                DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+                DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+                DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+                DCD     USART10_IRQHandler                ;  USART10 global interrupt
+                DCD     LPUART1_IRQHandler                ;  LPUART1 interrupt
+                DCD     0                                 ;  Reserved
+                DCD     CRS_IRQHandler                    ;  Clock Recovery Global Interrupt
+                DCD     ECC_IRQHandler                    ;  ECC_IRQHandler
+                DCD     0                                 ;  Reserved
+                DCD     DTS_IRQHandler                    ;  DTS
+                DCD     0                                 ;  Reserved
+                DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+                DCD     OCTOSPI2_IRQHandler               ;  OCTOSPI2
+                DCD     OTFDEC1_IRQHandler                ;  OTFDEC1
+                DCD     OTFDEC2_IRQHandler                ;  OTFDEC2
+                DCD     GFXMMU_IRQHandler                 ;  GFXMMU
+                DCD     BDMA1_IRQHandler                  ;  BDMA1
+
+
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler                    [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                      [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler                [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler                [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler                 [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler               [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                      [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler                  [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler                    [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler                   [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]
+                EXPORT  PVD_PVM_IRQHandler                [WEAK]
+                EXPORT  RTC_TAMP_STAMP_CSS_LSE_IRQHandler [WEAK]
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]
+                EXPORT  FLASH_IRQHandler                  [WEAK]
+                EXPORT  RCC_IRQHandler                    [WEAK]
+                EXPORT  EXTI0_IRQHandler                  [WEAK]
+                EXPORT  EXTI1_IRQHandler                  [WEAK]
+                EXPORT  EXTI2_IRQHandler                  [WEAK]
+                EXPORT  EXTI3_IRQHandler                  [WEAK]
+                EXPORT  EXTI4_IRQHandler                  [WEAK]
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  ADC_IRQHandler                    [WEAK]
+                EXPORT  FDCAN1_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT0_IRQHandler             [WEAK]
+                EXPORT  FDCAN1_IT1_IRQHandler             [WEAK]
+                EXPORT  FDCAN2_IT1_IRQHandler             [WEAK]
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]
+                EXPORT  TIM1_BRK_IRQHandler               [WEAK]
+                EXPORT  TIM1_UP_IRQHandler                [WEAK]
+                EXPORT  TIM1_TRG_COM_IRQHandler           [WEAK]
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]
+                EXPORT  TIM2_IRQHandler                   [WEAK]
+                EXPORT  TIM3_IRQHandler                   [WEAK]
+                EXPORT  TIM4_IRQHandler                   [WEAK]
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]
+                EXPORT  SPI1_IRQHandler                   [WEAK]
+                EXPORT  SPI2_IRQHandler                   [WEAK]
+                EXPORT  USART1_IRQHandler                 [WEAK]
+                EXPORT  USART2_IRQHandler                 [WEAK]
+                EXPORT  USART3_IRQHandler                 [WEAK]
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]
+                EXPORT  DFSDM2_IRQHandler                 [WEAK]
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK]
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]
+                EXPORT  FMC_IRQHandler                    [WEAK]
+                EXPORT  SDMMC1_IRQHandler                 [WEAK]
+                EXPORT  TIM5_IRQHandler                   [WEAK]
+                EXPORT  SPI3_IRQHandler                   [WEAK]
+                EXPORT  UART4_IRQHandler                  [WEAK]
+                EXPORT  UART5_IRQHandler                  [WEAK]
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]
+                EXPORT  TIM7_IRQHandler                   [WEAK]
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]
+                EXPORT  FDCAN_CAL_IRQHandler              [WEAK]
+                EXPORT  DFSDM1_FLT4_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT5_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT6_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT7_IRQHandler            [WEAK]
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]
+                EXPORT  USART6_IRQHandler                 [WEAK]
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]
+                EXPORT  DCMI_PSSI_IRQHandler              [WEAK]
+                EXPORT  CRYP_IRQHandler                   [WEAK]
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]
+                EXPORT  UART7_IRQHandler                  [WEAK]
+                EXPORT  UART8_IRQHandler                  [WEAK]
+                EXPORT  SPI4_IRQHandler                   [WEAK]
+                EXPORT  SPI5_IRQHandler                   [WEAK]
+                EXPORT  SPI6_IRQHandler                   [WEAK]
+                EXPORT  SAI1_IRQHandler                   [WEAK]
+                EXPORT  LTDC_IRQHandler                   [WEAK]
+                EXPORT  LTDC_ER_IRQHandler                [WEAK]
+                EXPORT  DMA2D_IRQHandler                  [WEAK]
+                EXPORT  SAI2_IRQHandler                   [WEAK]
+                EXPORT  OCTOSPI1_IRQHandler               [WEAK]
+                EXPORT  LPTIM1_IRQHandler                 [WEAK]
+                EXPORT  CEC_IRQHandler                    [WEAK]
+                EXPORT  I2C4_EV_IRQHandler                [WEAK]
+                EXPORT  I2C4_ER_IRQHandler                [WEAK]
+                EXPORT  SPDIF_RX_IRQHandler               [WEAK]
+                EXPORT  DMAMUX1_OVR_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT0_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT1_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT2_IRQHandler            [WEAK]
+                EXPORT  DFSDM1_FLT3_IRQHandler            [WEAK]
+                EXPORT  SWPMI1_IRQHandler                 [WEAK]
+                EXPORT  TIM15_IRQHandler                  [WEAK]
+                EXPORT  TIM16_IRQHandler                  [WEAK]
+                EXPORT  TIM17_IRQHandler                  [WEAK]
+                EXPORT  MDIOS_WKUP_IRQHandler             [WEAK]
+                EXPORT  MDIOS_IRQHandler                  [WEAK]
+                EXPORT  JPEG_IRQHandler                   [WEAK]
+                EXPORT  MDMA_IRQHandler                   [WEAK]
+                EXPORT  SDMMC2_IRQHandler                 [WEAK]
+                EXPORT  HSEM1_IRQHandler                  [WEAK]
+                EXPORT  DAC2_IRQHandler                   [WEAK]
+                EXPORT  DMAMUX2_OVR_IRQHandler            [WEAK]
+                EXPORT  BDMA2_Channel0_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel1_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel2_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel3_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel4_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel5_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel6_IRQHandler         [WEAK]
+                EXPORT  BDMA2_Channel7_IRQHandler         [WEAK]
+                EXPORT  COMP_IRQHandler                   [WEAK]
+                EXPORT  LPTIM2_IRQHandler                 [WEAK]
+                EXPORT  LPTIM3_IRQHandler                 [WEAK]
+                EXPORT  UART9_IRQHandler                  [WEAK]
+                EXPORT  USART10_IRQHandler                [WEAK]
+                EXPORT  LPUART1_IRQHandler                [WEAK]
+                EXPORT  CRS_IRQHandler                    [WEAK]
+                EXPORT  ECC_IRQHandler                    [WEAK]
+                EXPORT  DTS_IRQHandler                    [WEAK]
+                EXPORT  WAKEUP_PIN_IRQHandler             [WEAK]
+                EXPORT  OCTOSPI2_IRQHandler               [WEAK]
+                EXPORT  OTFDEC1_IRQHandler                [WEAK]
+                EXPORT  OTFDEC2_IRQHandler                [WEAK]
+                EXPORT  GFXMMU_IRQHandler                 [WEAK]
+                EXPORT  BDMA1_IRQHandler                  [WEAK]
+
+
+WWDG_IRQHandler
+PVD_PVM_IRQHandler
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+RTC_WKUP_IRQHandler
+FLASH_IRQHandler
+RCC_IRQHandler
+EXTI0_IRQHandler
+EXTI1_IRQHandler
+EXTI2_IRQHandler
+EXTI3_IRQHandler
+EXTI4_IRQHandler
+DMA1_Stream0_IRQHandler
+DMA1_Stream1_IRQHandler
+DMA1_Stream2_IRQHandler
+DMA1_Stream3_IRQHandler
+DMA1_Stream4_IRQHandler
+DMA1_Stream5_IRQHandler
+DMA1_Stream6_IRQHandler
+ADC_IRQHandler
+FDCAN1_IT0_IRQHandler
+FDCAN2_IT0_IRQHandler
+FDCAN1_IT1_IRQHandler
+FDCAN2_IT1_IRQHandler
+EXTI9_5_IRQHandler
+TIM1_BRK_IRQHandler
+TIM1_UP_IRQHandler
+TIM1_TRG_COM_IRQHandler
+TIM1_CC_IRQHandler
+TIM2_IRQHandler
+TIM3_IRQHandler
+TIM4_IRQHandler
+I2C1_EV_IRQHandler
+I2C1_ER_IRQHandler
+I2C2_EV_IRQHandler
+I2C2_ER_IRQHandler
+SPI1_IRQHandler
+SPI2_IRQHandler
+USART1_IRQHandler
+USART2_IRQHandler
+USART3_IRQHandler
+EXTI15_10_IRQHandler
+RTC_Alarm_IRQHandler
+DFSDM2_IRQHandler
+TIM8_BRK_TIM12_IRQHandler
+TIM8_UP_TIM13_IRQHandler
+TIM8_TRG_COM_TIM14_IRQHandler
+TIM8_CC_IRQHandler
+DMA1_Stream7_IRQHandler
+FMC_IRQHandler
+SDMMC1_IRQHandler
+TIM5_IRQHandler
+SPI3_IRQHandler
+UART4_IRQHandler
+UART5_IRQHandler
+TIM6_DAC_IRQHandler
+TIM7_IRQHandler
+DMA2_Stream0_IRQHandler
+DMA2_Stream1_IRQHandler
+DMA2_Stream2_IRQHandler
+DMA2_Stream3_IRQHandler
+DMA2_Stream4_IRQHandler
+FDCAN_CAL_IRQHandler
+DFSDM1_FLT4_IRQHandler
+DFSDM1_FLT5_IRQHandler
+DFSDM1_FLT6_IRQHandler
+DFSDM1_FLT7_IRQHandler
+DMA2_Stream5_IRQHandler
+DMA2_Stream6_IRQHandler
+DMA2_Stream7_IRQHandler
+USART6_IRQHandler
+I2C3_EV_IRQHandler
+I2C3_ER_IRQHandler
+OTG_HS_EP1_OUT_IRQHandler
+OTG_HS_EP1_IN_IRQHandler
+OTG_HS_WKUP_IRQHandler
+OTG_HS_IRQHandler
+DCMI_PSSI_IRQHandler
+CRYP_IRQHandler
+HASH_RNG_IRQHandler
+FPU_IRQHandler
+UART7_IRQHandler
+UART8_IRQHandler
+SPI4_IRQHandler
+SPI5_IRQHandler
+SPI6_IRQHandler
+SAI1_IRQHandler
+LTDC_IRQHandler
+LTDC_ER_IRQHandler
+DMA2D_IRQHandler
+SAI2_IRQHandler
+OCTOSPI1_IRQHandler
+LPTIM1_IRQHandler
+CEC_IRQHandler
+I2C4_EV_IRQHandler
+I2C4_ER_IRQHandler
+SPDIF_RX_IRQHandler
+DMAMUX1_OVR_IRQHandler
+DFSDM1_FLT0_IRQHandler
+DFSDM1_FLT1_IRQHandler
+DFSDM1_FLT2_IRQHandler
+DFSDM1_FLT3_IRQHandler
+SWPMI1_IRQHandler
+TIM15_IRQHandler
+TIM16_IRQHandler
+TIM17_IRQHandler
+MDIOS_WKUP_IRQHandler
+MDIOS_IRQHandler
+JPEG_IRQHandler
+MDMA_IRQHandler
+SDMMC2_IRQHandler
+HSEM1_IRQHandler
+DAC2_IRQHandler
+DMAMUX2_OVR_IRQHandler
+BDMA2_Channel0_IRQHandler
+BDMA2_Channel1_IRQHandler
+BDMA2_Channel2_IRQHandler
+BDMA2_Channel3_IRQHandler
+BDMA2_Channel4_IRQHandler
+BDMA2_Channel5_IRQHandler
+BDMA2_Channel6_IRQHandler
+BDMA2_Channel7_IRQHandler
+COMP_IRQHandler
+LPTIM2_IRQHandler
+LPTIM3_IRQHandler
+UART9_IRQHandler
+USART10_IRQHandler
+LPUART1_IRQHandler
+CRS_IRQHandler
+ECC_IRQHandler
+DTS_IRQHandler
+WAKEUP_PIN_IRQHandler
+OCTOSPI2_IRQHandler
+OTFDEC1_IRQHandler
+OTFDEC2_IRQHandler
+GFXMMU_IRQHandler
+BDMA1_IRQHandler
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+
+                 ELSE
+
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

CMSIS/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xx.s

@@ -0,0 +1,741 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h7a3xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H7B3xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_PVM_IRQHandler                /* PVD/PVM through EXTI Line detection */
+  .word     RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     DFSDM2_IRQHandler                 /* DFSDM2 Interrupt             */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     DFSDM1_FLT4_IRQHandler            /* DFSDM Filter4 Interrupt      */
+  .word     DFSDM1_FLT5_IRQHandler            /* DFSDM Filter5 Interrupt      */
+  .word     DFSDM1_FLT6_IRQHandler            /* DFSDM Filter6 Interrupt      */
+  .word     DFSDM1_FLT7_IRQHandler            /* DFSDM Filter7 Interrupt      */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     0                                 /* Reserved                     */
+  .word     RNG_IRQHandler                    /* RNG                          */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
+  .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
+  .word     0                                 /* Reserved                    */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
+  .word     0                                 /* Reserved                    */
+  .word     DAC2_IRQHandler                   /* DAC2 global Interrupt       */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
+  .word     BDMA2_Channel0_IRQHandler         /* BDMA2 Channel 0 global Interrupt */
+  .word     BDMA2_Channel1_IRQHandler         /* BDMA2 Channel 1 global Interrupt */
+  .word     BDMA2_Channel2_IRQHandler         /* BDMA2 Channel 2 global Interrupt */
+  .word     BDMA2_Channel3_IRQHandler         /* BDMA2 Channel 3 global Interrupt */
+  .word     BDMA2_Channel4_IRQHandler         /* BDMA2 Channel 4 global Interrupt */
+  .word     BDMA2_Channel5_IRQHandler         /* BDMA2 Channel 5 global Interrupt */
+  .word     BDMA2_Channel6_IRQHandler         /* BDMA2 Channel 6 global Interrupt */
+  .word     BDMA2_Channel7_IRQHandler         /* BDMA2 Channel 7 global Interrupt */
+  .word     COMP_IRQHandler                   /* COMP global Interrupt      */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt     */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt     */
+  .word     UART9_IRQHandler                  /* UART9 global interrupt       */
+  .word     USART10_IRQHandler                /* USART10 global interrupt     */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt           */
+  .word     0                                 /* Reserved                     */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     0                                 /* Reserved                     */
+  .word     DTS_IRQHandler                    /* DTS                          */
+  .word     0                                 /* Reserved                     */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     GFXMMU_IRQHandler                 /* GFXMMU                       */
+  .word     BDMA1_IRQHandler                  /* BDMA1                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_PVM_IRQHandler
+   .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+   .weak      RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+   .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_IRQHandler
+   .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT4_IRQHandler
+   .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT5_IRQHandler
+   .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT6_IRQHandler
+   .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT7_IRQHandler
+   .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler
+   .thumb_set RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      SAI2_IRQHandler
+   .thumb_set SAI2_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      DAC2_IRQHandler
+   .thumb_set DAC2_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel0_IRQHandler
+   .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel1_IRQHandler
+   .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel2_IRQHandler
+   .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel3_IRQHandler
+   .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel4_IRQHandler
+   .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel5_IRQHandler
+   .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel6_IRQHandler
+   .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel7_IRQHandler
+   .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP_IRQHandler
+   .thumb_set COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      GFXMMU_IRQHandler
+   .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+   .weak      BDMA1_IRQHandler
+   .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

CMSIS/STM32H7xx/Source/Templates/gcc/startup_stm32h7a3xxq.s

@@ -0,0 +1,741 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h7a3xxq.s
+  * @author    MCD Application Team
+  * @brief     STM32H7B3xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_PVM_IRQHandler                /* PVD/PVM through EXTI Line detection */
+  .word     RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     DFSDM2_IRQHandler                 /* DFSDM2 Interrupt             */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     DFSDM1_FLT4_IRQHandler            /* DFSDM Filter4 Interrupt      */
+  .word     DFSDM1_FLT5_IRQHandler            /* DFSDM Filter5 Interrupt      */
+  .word     DFSDM1_FLT6_IRQHandler            /* DFSDM Filter6 Interrupt      */
+  .word     DFSDM1_FLT7_IRQHandler            /* DFSDM Filter7 Interrupt      */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     0                                 /* Reserved                     */
+  .word     RNG_IRQHandler                    /* RNG                          */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
+  .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
+  .word     0                                 /* Reserved                    */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
+  .word     0                                 /* Reserved                    */
+  .word     DAC2_IRQHandler                   /* DAC2 global Interrupt       */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
+  .word     BDMA2_Channel0_IRQHandler         /* BDMA2 Channel 0 global Interrupt */
+  .word     BDMA2_Channel1_IRQHandler         /* BDMA2 Channel 1 global Interrupt */
+  .word     BDMA2_Channel2_IRQHandler         /* BDMA2 Channel 2 global Interrupt */
+  .word     BDMA2_Channel3_IRQHandler         /* BDMA2 Channel 3 global Interrupt */
+  .word     BDMA2_Channel4_IRQHandler         /* BDMA2 Channel 4 global Interrupt */
+  .word     BDMA2_Channel5_IRQHandler         /* BDMA2 Channel 5 global Interrupt */
+  .word     BDMA2_Channel6_IRQHandler         /* BDMA2 Channel 6 global Interrupt */
+  .word     BDMA2_Channel7_IRQHandler         /* BDMA2 Channel 7 global Interrupt */
+  .word     COMP_IRQHandler                   /* COMP global Interrupt      */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt     */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt     */
+  .word     UART9_IRQHandler                  /* UART9 global interrupt       */
+  .word     USART10_IRQHandler                /* USART10 global interrupt     */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt           */
+  .word     0                                 /* Reserved                     */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     0                                 /* Reserved                     */
+  .word     DTS_IRQHandler                    /* DTS                          */
+  .word     0                                 /* Reserved                     */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     GFXMMU_IRQHandler                 /* GFXMMU                       */
+  .word     BDMA1_IRQHandler                  /* BDMA1                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_PVM_IRQHandler
+   .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+   .weak      RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+   .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_IRQHandler
+   .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT4_IRQHandler
+   .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT5_IRQHandler
+   .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT6_IRQHandler
+   .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT7_IRQHandler
+   .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      RNG_IRQHandler
+   .thumb_set RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      SAI2_IRQHandler
+   .thumb_set SAI2_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      DAC2_IRQHandler
+   .thumb_set DAC2_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel0_IRQHandler
+   .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel1_IRQHandler
+   .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel2_IRQHandler
+   .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel3_IRQHandler
+   .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel4_IRQHandler
+   .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel5_IRQHandler
+   .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel6_IRQHandler
+   .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel7_IRQHandler
+   .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP_IRQHandler
+   .thumb_set COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      GFXMMU_IRQHandler
+   .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+   .weak      BDMA1_IRQHandler
+   .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

CMSIS/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xx.s

@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h7b0xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H7B0xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_PVM_IRQHandler                /* PVD/PVM through EXTI Line detection */
+  .word     RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     DFSDM2_IRQHandler                 /* DFSDM2 Interrupt             */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     DFSDM1_FLT4_IRQHandler            /* DFSDM Filter4 Interrupt      */
+  .word     DFSDM1_FLT5_IRQHandler            /* DFSDM Filter5 Interrupt      */
+  .word     DFSDM1_FLT6_IRQHandler            /* DFSDM Filter6 Interrupt      */
+  .word     DFSDM1_FLT7_IRQHandler            /* DFSDM Filter7 Interrupt      */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     CRYP_IRQHandler                   /* CRYP crypto global interrupt */
+  .word     HASH_RNG_IRQHandler               /* RNG, HASH                    */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
+  .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
+  .word     0                                 /* Reserved                    */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
+  .word     0                                 /* Reserved                    */
+  .word     DAC2_IRQHandler                   /* DAC2 global Interrupt       */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
+  .word     BDMA2_Channel0_IRQHandler         /* BDMA2 Channel 0 global Interrupt */
+  .word     BDMA2_Channel1_IRQHandler         /* BDMA2 Channel 1 global Interrupt */
+  .word     BDMA2_Channel2_IRQHandler         /* BDMA2 Channel 2 global Interrupt */
+  .word     BDMA2_Channel3_IRQHandler         /* BDMA2 Channel 3 global Interrupt */
+  .word     BDMA2_Channel4_IRQHandler         /* BDMA2 Channel 4 global Interrupt */
+  .word     BDMA2_Channel5_IRQHandler         /* BDMA2 Channel 5 global Interrupt */
+  .word     BDMA2_Channel6_IRQHandler         /* BDMA2 Channel 6 global Interrupt */
+  .word     BDMA2_Channel7_IRQHandler         /* BDMA2 Channel 7 global Interrupt */
+  .word     COMP_IRQHandler                   /* COMP global Interrupt      */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt     */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt     */
+  .word     UART9_IRQHandler                  /* UART9 global interrupt       */
+  .word     USART10_IRQHandler                /* USART10 global interrupt     */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt           */
+  .word     0                                 /* Reserved                     */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     0                                 /* Reserved                     */
+  .word     DTS_IRQHandler                    /* DTS                          */
+  .word     0                                 /* Reserved                     */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2                     */
+  .word     OTFDEC1_IRQHandler                /* OTFDEC1                      */
+  .word     OTFDEC2_IRQHandler                /* OTFDEC2                      */
+  .word     GFXMMU_IRQHandler                 /* GFXMMU                       */
+  .word     BDMA1_IRQHandler                  /* BDMA1                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_PVM_IRQHandler
+   .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+   .weak      RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+   .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_IRQHandler
+   .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT4_IRQHandler
+   .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT5_IRQHandler
+   .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT6_IRQHandler
+   .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT7_IRQHandler
+   .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      CRYP_IRQHandler
+   .thumb_set CRYP_IRQHandler,Default_Handler
+
+   .weak      HASH_RNG_IRQHandler
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      SAI2_IRQHandler
+   .thumb_set SAI2_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      DAC2_IRQHandler
+   .thumb_set DAC2_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel0_IRQHandler
+   .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel1_IRQHandler
+   .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel2_IRQHandler
+   .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel3_IRQHandler
+   .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel4_IRQHandler
+   .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel5_IRQHandler
+   .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel6_IRQHandler
+   .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel7_IRQHandler
+   .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP_IRQHandler
+   .thumb_set COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      OTFDEC1_IRQHandler
+   .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+   .weak      OTFDEC2_IRQHandler
+   .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+   .weak      GFXMMU_IRQHandler
+   .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+   .weak      BDMA1_IRQHandler
+   .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

CMSIS/STM32H7xx/Source/Templates/gcc/startup_stm32h7b0xxq.s

@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h7b0xxq.s
+  * @author    MCD Application Team
+  * @brief     STM32H7B0xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_PVM_IRQHandler                /* PVD/PVM through EXTI Line detection */
+  .word     RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     DFSDM2_IRQHandler                 /* DFSDM2 Interrupt             */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     DFSDM1_FLT4_IRQHandler            /* DFSDM Filter4 Interrupt      */
+  .word     DFSDM1_FLT5_IRQHandler            /* DFSDM Filter5 Interrupt      */
+  .word     DFSDM1_FLT6_IRQHandler            /* DFSDM Filter6 Interrupt      */
+  .word     DFSDM1_FLT7_IRQHandler            /* DFSDM Filter7 Interrupt      */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     CRYP_IRQHandler                   /* CRYP crypto global interrupt */
+  .word     HASH_RNG_IRQHandler               /* RNG, HASH                    */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
+  .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
+  .word     0                                 /* Reserved                    */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
+  .word     0                                 /* Reserved                    */
+  .word     DAC2_IRQHandler                   /* DAC2 global Interrupt       */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
+  .word     BDMA2_Channel0_IRQHandler         /* BDMA2 Channel 0 global Interrupt */
+  .word     BDMA2_Channel1_IRQHandler         /* BDMA2 Channel 1 global Interrupt */
+  .word     BDMA2_Channel2_IRQHandler         /* BDMA2 Channel 2 global Interrupt */
+  .word     BDMA2_Channel3_IRQHandler         /* BDMA2 Channel 3 global Interrupt */
+  .word     BDMA2_Channel4_IRQHandler         /* BDMA2 Channel 4 global Interrupt */
+  .word     BDMA2_Channel5_IRQHandler         /* BDMA2 Channel 5 global Interrupt */
+  .word     BDMA2_Channel6_IRQHandler         /* BDMA2 Channel 6 global Interrupt */
+  .word     BDMA2_Channel7_IRQHandler         /* BDMA2 Channel 7 global Interrupt */
+  .word     COMP_IRQHandler                   /* COMP global Interrupt      */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt     */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt     */
+  .word     UART9_IRQHandler                  /* UART9 global interrupt       */
+  .word     USART10_IRQHandler                /* USART10 global interrupt     */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt           */
+  .word     0                                 /* Reserved                     */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     0                                 /* Reserved                     */
+  .word     DTS_IRQHandler                    /* DTS                          */
+  .word     0                                 /* Reserved                     */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2                     */
+  .word     OTFDEC1_IRQHandler                /* OTFDEC1                      */
+  .word     OTFDEC2_IRQHandler                /* OTFDEC2                      */
+  .word     GFXMMU_IRQHandler                 /* GFXMMU                       */
+  .word     BDMA1_IRQHandler                  /* BDMA1                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_PVM_IRQHandler
+   .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+   .weak      RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+   .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_IRQHandler
+   .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT4_IRQHandler
+   .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT5_IRQHandler
+   .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT6_IRQHandler
+   .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT7_IRQHandler
+   .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      CRYP_IRQHandler
+   .thumb_set CRYP_IRQHandler,Default_Handler
+
+   .weak      HASH_RNG_IRQHandler
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      SAI2_IRQHandler
+   .thumb_set SAI2_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      DAC2_IRQHandler
+   .thumb_set DAC2_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel0_IRQHandler
+   .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel1_IRQHandler
+   .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel2_IRQHandler
+   .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel3_IRQHandler
+   .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel4_IRQHandler
+   .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel5_IRQHandler
+   .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel6_IRQHandler
+   .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel7_IRQHandler
+   .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP_IRQHandler
+   .thumb_set COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      OTFDEC1_IRQHandler
+   .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+   .weak      OTFDEC2_IRQHandler
+   .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+   .weak      GFXMMU_IRQHandler
+   .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+   .weak      BDMA1_IRQHandler
+   .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

CMSIS/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xx.s

@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h7b3xx.s
+  * @author    MCD Application Team
+  * @brief     STM32H7B3xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_PVM_IRQHandler                /* PVD/PVM through EXTI Line detection */
+  .word     RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     DFSDM2_IRQHandler                 /* DFSDM2 Interrupt             */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     DFSDM1_FLT4_IRQHandler            /* DFSDM Filter4 Interrupt      */
+  .word     DFSDM1_FLT5_IRQHandler            /* DFSDM Filter5 Interrupt      */
+  .word     DFSDM1_FLT6_IRQHandler            /* DFSDM Filter6 Interrupt      */
+  .word     DFSDM1_FLT7_IRQHandler            /* DFSDM Filter7 Interrupt      */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     CRYP_IRQHandler                   /* CRYP crypto global interrupt */
+  .word     HASH_RNG_IRQHandler               /* RNG, HASH                    */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
+  .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
+  .word     0                                 /* Reserved                    */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
+  .word     0                                 /* Reserved                    */
+  .word     DAC2_IRQHandler                   /* DAC2 global Interrupt       */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
+  .word     BDMA2_Channel0_IRQHandler         /* BDMA2 Channel 0 global Interrupt */
+  .word     BDMA2_Channel1_IRQHandler         /* BDMA2 Channel 1 global Interrupt */
+  .word     BDMA2_Channel2_IRQHandler         /* BDMA2 Channel 2 global Interrupt */
+  .word     BDMA2_Channel3_IRQHandler         /* BDMA2 Channel 3 global Interrupt */
+  .word     BDMA2_Channel4_IRQHandler         /* BDMA2 Channel 4 global Interrupt */
+  .word     BDMA2_Channel5_IRQHandler         /* BDMA2 Channel 5 global Interrupt */
+  .word     BDMA2_Channel6_IRQHandler         /* BDMA2 Channel 6 global Interrupt */
+  .word     BDMA2_Channel7_IRQHandler         /* BDMA2 Channel 7 global Interrupt */
+  .word     COMP_IRQHandler                   /* COMP global Interrupt      */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt     */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt     */
+  .word     UART9_IRQHandler                  /* UART9 global interrupt       */
+  .word     USART10_IRQHandler                /* USART10 global interrupt     */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt           */
+  .word     0                                 /* Reserved                     */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     0                                 /* Reserved                     */
+  .word     DTS_IRQHandler                    /* DTS                          */
+  .word     0                                 /* Reserved                     */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2                     */
+  .word     OTFDEC1_IRQHandler                /* OTFDEC1                      */
+  .word     OTFDEC2_IRQHandler                /* OTFDEC2                      */
+  .word     GFXMMU_IRQHandler                 /* GFXMMU                       */
+  .word     BDMA1_IRQHandler                  /* BDMA1                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_PVM_IRQHandler
+   .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+   .weak      RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+   .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_IRQHandler
+   .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT4_IRQHandler
+   .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT5_IRQHandler
+   .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT6_IRQHandler
+   .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT7_IRQHandler
+   .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      CRYP_IRQHandler
+   .thumb_set CRYP_IRQHandler,Default_Handler
+
+   .weak      HASH_RNG_IRQHandler
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      SAI2_IRQHandler
+   .thumb_set SAI2_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      DAC2_IRQHandler
+   .thumb_set DAC2_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel0_IRQHandler
+   .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel1_IRQHandler
+   .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel2_IRQHandler
+   .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel3_IRQHandler
+   .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel4_IRQHandler
+   .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel5_IRQHandler
+   .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel6_IRQHandler
+   .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel7_IRQHandler
+   .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP_IRQHandler
+   .thumb_set COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      OTFDEC1_IRQHandler
+   .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+   .weak      OTFDEC2_IRQHandler
+   .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+   .weak      GFXMMU_IRQHandler
+   .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+   .weak      BDMA1_IRQHandler
+   .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

CMSIS/STM32H7xx/Source/Templates/gcc/startup_stm32h7b3xxq.s

@@ -0,0 +1,750 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32h7b3xxq.s
+  * @author    MCD Application Team
+  * @brief     STM32H7B3xx Devices vector table for GCC based toolchain.
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+  .syntax unified
+  .cpu cortex-m7
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called.
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:
+  ldr   sp, =_estack      /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None
+ * @retval None
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */
+  .word     PVD_PVM_IRQHandler                /* PVD/PVM through EXTI Line detection */
+  .word     RTC_TAMP_STAMP_CSS_LSE_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
+  .word     FLASH_IRQHandler                  /* FLASH                        */
+  .word     RCC_IRQHandler                    /* RCC                          */
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
+  .word     FDCAN1_IT0_IRQHandler             /* FDCAN1 interrupt line 0      */
+  .word     FDCAN2_IT0_IRQHandler             /* FDCAN2 interrupt line 0      */
+  .word     FDCAN1_IT1_IRQHandler             /* FDCAN1 interrupt line 1      */
+  .word     FDCAN2_IT1_IRQHandler             /* FDCAN2 interrupt line 1      */
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
+  .word     TIM1_BRK_IRQHandler               /* TIM1 Break interrupt         */
+  .word     TIM1_UP_IRQHandler                /* TIM1 Update interrupt        */
+  .word     TIM1_TRG_COM_IRQHandler           /* TIM1 Trigger and Commutation interrupt */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
+  .word     TIM2_IRQHandler                   /* TIM2                         */
+  .word     TIM3_IRQHandler                   /* TIM3                         */
+  .word     TIM4_IRQHandler                   /* TIM4                         */
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
+  .word     SPI1_IRQHandler                   /* SPI1                         */
+  .word     SPI2_IRQHandler                   /* SPI2                         */
+  .word     USART1_IRQHandler                 /* USART1                       */
+  .word     USART2_IRQHandler                 /* USART2                       */
+  .word     USART3_IRQHandler                 /* USART3                       */
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
+  .word     DFSDM2_IRQHandler                 /* DFSDM2 Interrupt             */
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
+  .word     FMC_IRQHandler                    /* FMC                          */
+  .word     SDMMC1_IRQHandler                 /* SDMMC1                       */
+  .word     TIM5_IRQHandler                   /* TIM5                         */
+  .word     SPI3_IRQHandler                   /* SPI3                         */
+  .word     UART4_IRQHandler                  /* UART4                        */
+  .word     UART5_IRQHandler                  /* UART5                        */
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     FDCAN_CAL_IRQHandler              /* FDCAN calibration unit interrupt*/
+  .word     DFSDM1_FLT4_IRQHandler            /* DFSDM Filter4 Interrupt      */
+  .word     DFSDM1_FLT5_IRQHandler            /* DFSDM Filter5 Interrupt      */
+  .word     DFSDM1_FLT6_IRQHandler            /* DFSDM Filter6 Interrupt      */
+  .word     DFSDM1_FLT7_IRQHandler            /* DFSDM Filter7 Interrupt      */
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
+  .word     USART6_IRQHandler                 /* USART6                       */
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
+  .word     DCMI_PSSI_IRQHandler              /* DCMI, PSSI                   */
+  .word     CRYP_IRQHandler                   /* CRYP crypto global interrupt */
+  .word     HASH_RNG_IRQHandler               /* RNG, HASH                    */
+  .word     FPU_IRQHandler                    /* FPU                          */
+  .word     UART7_IRQHandler                  /* UART7                        */
+  .word     UART8_IRQHandler                  /* UART8                        */
+  .word     SPI4_IRQHandler                   /* SPI4                         */
+  .word     SPI5_IRQHandler                   /* SPI5                         */
+  .word     SPI6_IRQHandler                   /* SPI6                         */
+  .word     SAI1_IRQHandler                   /* SAI1                         */
+  .word     LTDC_IRQHandler                   /* LTDC                         */
+  .word     LTDC_ER_IRQHandler                /* LTDC error                   */
+  .word     DMA2D_IRQHandler                  /* DMA2D                        */
+  .word     SAI2_IRQHandler                   /* SAI2                         */
+  .word     OCTOSPI1_IRQHandler               /* OCTOSPI1                     */
+  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
+  .word     CEC_IRQHandler                    /* HDMI_CEC                     */
+  .word     I2C4_EV_IRQHandler                /* I2C4 Event                   */
+  .word     I2C4_ER_IRQHandler                /* I2C4 Error                   */
+  .word     SPDIF_RX_IRQHandler               /* SPDIF_RX                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DMAMUX1_OVR_IRQHandler            /* DMAMUX1 Overrun interrupt    */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     0                                 /* Reserved                     */
+  .word     DFSDM1_FLT0_IRQHandler            /* DFSDM Filter0 Interrupt      */
+  .word     DFSDM1_FLT1_IRQHandler            /* DFSDM Filter1 Interrupt      */
+  .word     DFSDM1_FLT2_IRQHandler            /* DFSDM Filter2 Interrupt      */
+  .word     DFSDM1_FLT3_IRQHandler            /* DFSDM Filter3 Interrupt      */
+  .word     0                                 /* Reserved                     */
+  .word     SWPMI1_IRQHandler                 /* Serial Wire Interface 1 global interrupt */
+  .word     TIM15_IRQHandler                  /* TIM15 global Interrupt      */
+  .word     TIM16_IRQHandler                  /* TIM16 global Interrupt      */
+  .word     TIM17_IRQHandler                  /* TIM17 global Interrupt      */
+  .word     MDIOS_WKUP_IRQHandler             /* MDIOS Wakeup  Interrupt     */
+  .word     MDIOS_IRQHandler                  /* MDIOS global Interrupt      */
+  .word     JPEG_IRQHandler                   /* JPEG global Interrupt       */
+  .word     MDMA_IRQHandler                   /* MDMA global Interrupt       */
+  .word     0                                 /* Reserved                    */
+  .word     SDMMC2_IRQHandler                 /* SDMMC2 global Interrupt     */
+  .word     HSEM1_IRQHandler                  /* HSEM1 global Interrupt      */
+  .word     0                                 /* Reserved                    */
+  .word     DAC2_IRQHandler                   /* DAC2 global Interrupt       */
+  .word     DMAMUX2_OVR_IRQHandler            /* DMAMUX Overrun interrupt    */
+  .word     BDMA2_Channel0_IRQHandler         /* BDMA2 Channel 0 global Interrupt */
+  .word     BDMA2_Channel1_IRQHandler         /* BDMA2 Channel 1 global Interrupt */
+  .word     BDMA2_Channel2_IRQHandler         /* BDMA2 Channel 2 global Interrupt */
+  .word     BDMA2_Channel3_IRQHandler         /* BDMA2 Channel 3 global Interrupt */
+  .word     BDMA2_Channel4_IRQHandler         /* BDMA2 Channel 4 global Interrupt */
+  .word     BDMA2_Channel5_IRQHandler         /* BDMA2 Channel 5 global Interrupt */
+  .word     BDMA2_Channel6_IRQHandler         /* BDMA2 Channel 6 global Interrupt */
+  .word     BDMA2_Channel7_IRQHandler         /* BDMA2 Channel 7 global Interrupt */
+  .word     COMP_IRQHandler                   /* COMP global Interrupt      */
+  .word     LPTIM2_IRQHandler                 /* LP TIM2 global interrupt     */
+  .word     LPTIM3_IRQHandler                 /* LP TIM3 global interrupt     */
+  .word     UART9_IRQHandler                  /* UART9 global interrupt       */
+  .word     USART10_IRQHandler                /* USART10 global interrupt     */
+  .word     LPUART1_IRQHandler                /* LP UART1 interrupt           */
+  .word     0                                 /* Reserved                     */
+  .word     CRS_IRQHandler                    /* Clock Recovery Global Interrupt */
+  .word     ECC_IRQHandler                    /* ECC diagnostic Global Interrupt */
+  .word     0                                 /* Reserved                     */
+  .word     DTS_IRQHandler                    /* DTS                          */
+  .word     0                                 /* Reserved                     */
+  .word     WAKEUP_PIN_IRQHandler             /* Interrupt for all 6 wake-up pins */
+  .word     OCTOSPI2_IRQHandler               /* OCTOSPI2                     */
+  .word     OTFDEC1_IRQHandler                /* OTFDEC1                      */
+  .word     OTFDEC2_IRQHandler                /* OTFDEC2                      */
+  .word     GFXMMU_IRQHandler                 /* GFXMMU                       */
+  .word     BDMA1_IRQHandler                  /* BDMA1                        */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler
+
+   .weak      WWDG_IRQHandler
+   .thumb_set WWDG_IRQHandler,Default_Handler
+
+   .weak      PVD_PVM_IRQHandler
+   .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+   .weak      RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+   .thumb_set RTC_TAMP_STAMP_CSS_LSE_IRQHandler,Default_Handler
+
+   .weak      RTC_WKUP_IRQHandler
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+   .weak      FLASH_IRQHandler
+   .thumb_set FLASH_IRQHandler,Default_Handler
+
+   .weak      RCC_IRQHandler
+   .thumb_set RCC_IRQHandler,Default_Handler
+
+   .weak      EXTI0_IRQHandler
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+
+   .weak      EXTI1_IRQHandler
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+
+   .weak      EXTI2_IRQHandler
+   .thumb_set EXTI2_IRQHandler,Default_Handler
+
+   .weak      EXTI3_IRQHandler
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+
+   .weak      EXTI4_IRQHandler
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream0_IRQHandler
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream1_IRQHandler
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream2_IRQHandler
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream3_IRQHandler
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream4_IRQHandler
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream5_IRQHandler
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream6_IRQHandler
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+   .weak      ADC_IRQHandler
+   .thumb_set ADC_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT0_IRQHandler
+   .thumb_set FDCAN1_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT0_IRQHandler
+   .thumb_set FDCAN2_IT0_IRQHandler,Default_Handler
+
+   .weak      FDCAN1_IT1_IRQHandler
+   .thumb_set FDCAN1_IT1_IRQHandler,Default_Handler
+
+   .weak      FDCAN2_IT1_IRQHandler
+   .thumb_set FDCAN2_IT1_IRQHandler,Default_Handler
+
+   .weak      EXTI9_5_IRQHandler
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+   .weak      TIM1_BRK_IRQHandler
+   .thumb_set TIM1_BRK_IRQHandler,Default_Handler
+
+   .weak      TIM1_UP_IRQHandler
+   .thumb_set TIM1_UP_IRQHandler,Default_Handler
+
+   .weak      TIM1_TRG_COM_IRQHandler
+   .thumb_set TIM1_TRG_COM_IRQHandler,Default_Handler
+
+   .weak      TIM1_CC_IRQHandler
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+   .weak      TIM2_IRQHandler
+   .thumb_set TIM2_IRQHandler,Default_Handler
+
+   .weak      TIM3_IRQHandler
+   .thumb_set TIM3_IRQHandler,Default_Handler
+
+   .weak      TIM4_IRQHandler
+   .thumb_set TIM4_IRQHandler,Default_Handler
+
+   .weak      I2C1_EV_IRQHandler
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+   .weak      I2C1_ER_IRQHandler
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+   .weak      I2C2_EV_IRQHandler
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+   .weak      I2C2_ER_IRQHandler
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+   .weak      SPI1_IRQHandler
+   .thumb_set SPI1_IRQHandler,Default_Handler
+
+   .weak      SPI2_IRQHandler
+   .thumb_set SPI2_IRQHandler,Default_Handler
+
+   .weak      USART1_IRQHandler
+   .thumb_set USART1_IRQHandler,Default_Handler
+
+   .weak      USART2_IRQHandler
+   .thumb_set USART2_IRQHandler,Default_Handler
+
+   .weak      USART3_IRQHandler
+   .thumb_set USART3_IRQHandler,Default_Handler
+
+   .weak      EXTI15_10_IRQHandler
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+   .weak      RTC_Alarm_IRQHandler
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+   .weak      DFSDM2_IRQHandler
+   .thumb_set DFSDM2_IRQHandler,Default_Handler
+
+   .weak      TIM8_BRK_TIM12_IRQHandler
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+   .weak      TIM8_UP_TIM13_IRQHandler
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+   .weak      TIM8_CC_IRQHandler
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+   .weak      DMA1_Stream7_IRQHandler
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+   .weak      FMC_IRQHandler
+   .thumb_set FMC_IRQHandler,Default_Handler
+
+   .weak      SDMMC1_IRQHandler
+   .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+   .weak      TIM5_IRQHandler
+   .thumb_set TIM5_IRQHandler,Default_Handler
+
+   .weak      SPI3_IRQHandler
+   .thumb_set SPI3_IRQHandler,Default_Handler
+
+   .weak      UART4_IRQHandler
+   .thumb_set UART4_IRQHandler,Default_Handler
+
+   .weak      UART5_IRQHandler
+   .thumb_set UART5_IRQHandler,Default_Handler
+
+   .weak      TIM6_DAC_IRQHandler
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+   .weak      TIM7_IRQHandler
+   .thumb_set TIM7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream0_IRQHandler
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream1_IRQHandler
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream2_IRQHandler
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream3_IRQHandler
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream4_IRQHandler
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+   .weak      FDCAN_CAL_IRQHandler
+   .thumb_set FDCAN_CAL_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT4_IRQHandler
+   .thumb_set DFSDM1_FLT4_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT5_IRQHandler
+   .thumb_set DFSDM1_FLT5_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT6_IRQHandler
+   .thumb_set DFSDM1_FLT6_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT7_IRQHandler
+   .thumb_set DFSDM1_FLT7_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream5_IRQHandler
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream6_IRQHandler
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+   .weak      DMA2_Stream7_IRQHandler
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+   .weak      USART6_IRQHandler
+   .thumb_set USART6_IRQHandler,Default_Handler
+
+   .weak      I2C3_EV_IRQHandler
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+   .weak      I2C3_ER_IRQHandler
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_OUT_IRQHandler
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_EP1_IN_IRQHandler
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_WKUP_IRQHandler
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+   .weak      OTG_HS_IRQHandler
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+   .weak      DCMI_PSSI_IRQHandler
+   .thumb_set DCMI_PSSI_IRQHandler,Default_Handler
+
+   .weak      CRYP_IRQHandler
+   .thumb_set CRYP_IRQHandler,Default_Handler
+
+   .weak      HASH_RNG_IRQHandler
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler
+
+   .weak      FPU_IRQHandler
+   .thumb_set FPU_IRQHandler,Default_Handler
+
+   .weak      UART7_IRQHandler
+   .thumb_set UART7_IRQHandler,Default_Handler
+
+   .weak      UART8_IRQHandler
+   .thumb_set UART8_IRQHandler,Default_Handler
+
+   .weak      SPI4_IRQHandler
+   .thumb_set SPI4_IRQHandler,Default_Handler
+
+   .weak      SPI5_IRQHandler
+   .thumb_set SPI5_IRQHandler,Default_Handler
+
+   .weak      SPI6_IRQHandler
+   .thumb_set SPI6_IRQHandler,Default_Handler
+
+   .weak      SAI1_IRQHandler
+   .thumb_set SAI1_IRQHandler,Default_Handler
+
+   .weak      LTDC_IRQHandler
+   .thumb_set LTDC_IRQHandler,Default_Handler
+
+   .weak      LTDC_ER_IRQHandler
+   .thumb_set LTDC_ER_IRQHandler,Default_Handler
+
+   .weak      DMA2D_IRQHandler
+   .thumb_set DMA2D_IRQHandler,Default_Handler
+
+   .weak      SAI2_IRQHandler
+   .thumb_set SAI2_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI1_IRQHandler
+   .thumb_set OCTOSPI1_IRQHandler,Default_Handler
+
+   .weak      LPTIM1_IRQHandler
+   .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+   .weak      CEC_IRQHandler
+   .thumb_set CEC_IRQHandler,Default_Handler
+
+   .weak      I2C4_EV_IRQHandler
+   .thumb_set I2C4_EV_IRQHandler,Default_Handler
+
+   .weak      I2C4_ER_IRQHandler
+   .thumb_set I2C4_ER_IRQHandler,Default_Handler
+
+   .weak      SPDIF_RX_IRQHandler
+   .thumb_set SPDIF_RX_IRQHandler,Default_Handler
+
+   .weak      DMAMUX1_OVR_IRQHandler
+   .thumb_set DMAMUX1_OVR_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT0_IRQHandler
+   .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT1_IRQHandler
+   .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT2_IRQHandler
+   .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+   .weak      DFSDM1_FLT3_IRQHandler
+   .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+   .weak      SWPMI1_IRQHandler
+   .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+   .weak      TIM15_IRQHandler
+   .thumb_set TIM15_IRQHandler,Default_Handler
+
+   .weak      TIM16_IRQHandler
+   .thumb_set TIM16_IRQHandler,Default_Handler
+
+   .weak      TIM17_IRQHandler
+   .thumb_set TIM17_IRQHandler,Default_Handler
+
+   .weak      MDIOS_WKUP_IRQHandler
+   .thumb_set MDIOS_WKUP_IRQHandler,Default_Handler
+
+   .weak      MDIOS_IRQHandler
+   .thumb_set MDIOS_IRQHandler,Default_Handler
+
+   .weak      JPEG_IRQHandler
+   .thumb_set JPEG_IRQHandler,Default_Handler
+
+   .weak      MDMA_IRQHandler
+   .thumb_set MDMA_IRQHandler,Default_Handler
+
+   .weak      SDMMC2_IRQHandler
+   .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+   .weak      HSEM1_IRQHandler
+   .thumb_set HSEM1_IRQHandler,Default_Handler
+
+   .weak      DAC2_IRQHandler
+   .thumb_set DAC2_IRQHandler,Default_Handler
+
+   .weak      DMAMUX2_OVR_IRQHandler
+   .thumb_set DMAMUX2_OVR_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel0_IRQHandler
+   .thumb_set BDMA2_Channel0_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel1_IRQHandler
+   .thumb_set BDMA2_Channel1_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel2_IRQHandler
+   .thumb_set BDMA2_Channel2_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel3_IRQHandler
+   .thumb_set BDMA2_Channel3_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel4_IRQHandler
+   .thumb_set BDMA2_Channel4_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel5_IRQHandler
+   .thumb_set BDMA2_Channel5_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel6_IRQHandler
+   .thumb_set BDMA2_Channel6_IRQHandler,Default_Handler
+
+   .weak      BDMA2_Channel7_IRQHandler
+   .thumb_set BDMA2_Channel7_IRQHandler,Default_Handler
+
+   .weak      COMP_IRQHandler
+   .thumb_set COMP_IRQHandler,Default_Handler
+
+   .weak      LPTIM2_IRQHandler
+   .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+   .weak      LPTIM3_IRQHandler
+   .thumb_set LPTIM3_IRQHandler,Default_Handler
+
+   .weak      LPTIM4_IRQHandler
+   .thumb_set LPTIM4_IRQHandler,Default_Handler
+
+   .weak      LPTIM5_IRQHandler
+   .thumb_set LPTIM5_IRQHandler,Default_Handler
+
+   .weak      UART9_IRQHandler
+   .thumb_set UART9_IRQHandler,Default_Handler
+
+   .weak      USART10_IRQHandler
+   .thumb_set USART10_IRQHandler,Default_Handler
+
+   .weak      LPUART1_IRQHandler
+   .thumb_set LPUART1_IRQHandler,Default_Handler
+
+   .weak      CRS_IRQHandler
+   .thumb_set CRS_IRQHandler,Default_Handler
+
+   .weak      ECC_IRQHandler
+   .thumb_set ECC_IRQHandler,Default_Handler
+
+   .weak      DTS_IRQHandler
+   .thumb_set DTS_IRQHandler,Default_Handler
+
+   .weak      WAKEUP_PIN_IRQHandler
+   .thumb_set WAKEUP_PIN_IRQHandler,Default_Handler
+
+   .weak      OCTOSPI2_IRQHandler
+   .thumb_set OCTOSPI2_IRQHandler,Default_Handler
+
+   .weak      OTFDEC1_IRQHandler
+   .thumb_set OTFDEC1_IRQHandler,Default_Handler
+
+   .weak      OTFDEC2_IRQHandler
+   .thumb_set OTFDEC2_IRQHandler,Default_Handler
+
+   .weak      GFXMMU_IRQHandler
+   .thumb_set GFXMMU_IRQHandler,Default_Handler
+
+   .weak      BDMA1_IRQHandler
+   .thumb_set BDMA1_IRQHandler,Default_Handler
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

CMSIS/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xx.s

@@ -0,0 +1,956 @@
+;/******************************************************************************
+; * @file    startup_stm32h7a3xx.s
+; * @author  MCD Application Team
+; * @brief   STM32H7B3xx devices vector table for EWARM toolchain.
+;*           This module performs:
+;*           - Set the initial SP
+;*           - Set the initial PC == _iar_program_start,
+;*           - Set the vector table entries with the exceptions ISR
+;*           address.
+;*           - Branches to main in the C library (which eventually
+;*           calls main()).
+;*           After Reset the Cortex-M processor is in Thread mode,
+;*           priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+        DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+        DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+        DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+        DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+        DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+        DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+        DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+        DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+        DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+        DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+        DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+        DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+        DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+        DCD     BDMA2_Channel0_IRQHandler         ;  BDMA Channel 0 global Interrupt
+        DCD     BDMA2_Channel1_IRQHandler         ;  BDMA Channel 1 global Interrupt
+        DCD     BDMA2_Channel2_IRQHandler         ;  BDMA Channel 2 global Interrupt
+        DCD     BDMA2_Channel3_IRQHandler         ;  BDMA Channel 3 global Interrupt
+        DCD     BDMA2_Channel4_IRQHandler         ;  BDMA Channel 4 global Interrupt
+        DCD     BDMA2_Channel5_IRQHandler         ;  BDMA Channel 5 global Interrupt
+        DCD     BDMA2_Channel6_IRQHandler         ;  BDMA Channel 6 global Interrupt
+        DCD     BDMA2_Channel7_IRQHandler         ;  BDMA Channel 7 global Interrupt
+        DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+        DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+        DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+        DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+        DCD     USART10_IRQHandler                ;  USART10 global interrupt
+        DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt
+        DCD     0                                 ; Reserved
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt
+        DCD     ECC_IRQHandler                    ; ECC
+        DCD     0                                 ; Reserved
+        DCD     DTS_IRQHandler                    ; DTS
+        DCD     0                                 ; Reserved
+        DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+        DCD     OCTOSPI2_IRQHandler               ; OCTOSPI2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU
+        DCD     BDMA1_IRQHandler                  ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+        B DFSDM2_IRQHandler
+
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DFSDM1_FLT4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+        B DFSDM1_FLT4_IRQHandler
+
+        PUBWEAK DFSDM1_FLT5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+        B DFSDM1_FLT5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+        B DFSDM1_FLT6_IRQHandler
+
+        PUBWEAK DFSDM1_FLT7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+        B DFSDM1_FLT7_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK OCTOSPI1_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+        B HSEM1_IRQHandler
+
+        PUBWEAK DAC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+        B DAC2_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+        B BDMA2_Channel0_IRQHandler
+
+        PUBWEAK BDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+        B BDMA2_Channel1_IRQHandler
+
+        PUBWEAK BDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+        B BDMA2_Channel2_IRQHandler
+
+        PUBWEAK BDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+        B BDMA2_Channel3_IRQHandler
+
+        PUBWEAK BDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+        B BDMA2_Channel4_IRQHandler
+
+        PUBWEAK BDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+        B BDMA2_Channel5_IRQHandler
+
+        PUBWEAK BDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+        B BDMA2_Channel6_IRQHandler
+
+        PUBWEAK BDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+        B BDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+        B ECC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+        B WAKEUP_PIN_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK BDMA1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+        B BDMA1_IRQHandler
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32H7xx/Source/Templates/iar/startup_stm32h7a3xxq.s

@@ -0,0 +1,956 @@
+;/******************************************************************************
+; * @file    startup_stm32h7a3xxq.s
+; * @author  MCD Application Team
+; * @brief   STM32H7B3xx devices vector table for EWARM toolchain.
+;*           This module performs:
+;*           - Set the initial SP
+;*           - Set the initial PC == _iar_program_start,
+;*           - Set the vector table entries with the exceptions ISR
+;*           address.
+;*           - Branches to main in the C library (which eventually
+;*           calls main()).
+;*           After Reset the Cortex-M processor is in Thread mode,
+;*           priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+        DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+        DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+        DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+        DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+        DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI
+        DCD     0                                 ; Reserved
+        DCD     RNG_IRQHandler                    ; Rng
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+        DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+        DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+        DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+        DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+        DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+        DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+        DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+        DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+        DCD     BDMA2_Channel0_IRQHandler         ;  BDMA Channel 0 global Interrupt
+        DCD     BDMA2_Channel1_IRQHandler         ;  BDMA Channel 1 global Interrupt
+        DCD     BDMA2_Channel2_IRQHandler         ;  BDMA Channel 2 global Interrupt
+        DCD     BDMA2_Channel3_IRQHandler         ;  BDMA Channel 3 global Interrupt
+        DCD     BDMA2_Channel4_IRQHandler         ;  BDMA Channel 4 global Interrupt
+        DCD     BDMA2_Channel5_IRQHandler         ;  BDMA Channel 5 global Interrupt
+        DCD     BDMA2_Channel6_IRQHandler         ;  BDMA Channel 6 global Interrupt
+        DCD     BDMA2_Channel7_IRQHandler         ;  BDMA Channel 7 global Interrupt
+        DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+        DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+        DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+        DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+        DCD     USART10_IRQHandler                ;  USART10 global interrupt
+        DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt
+        DCD     0                                 ; Reserved
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt
+        DCD     ECC_IRQHandler                    ; ECC
+        DCD     0                                 ; Reserved
+        DCD     DTS_IRQHandler                    ; DTS
+        DCD     0                                 ; Reserved
+        DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+        DCD     OCTOSPI2_IRQHandler               ; OCTOSPI2
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU
+        DCD     BDMA1_IRQHandler                  ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+        B DFSDM2_IRQHandler
+
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DFSDM1_FLT4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+       B DFSDM1_FLT4_IRQHandler
+
+        PUBWEAK DFSDM1_FLT5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+        B DFSDM1_FLT5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+        B DFSDM1_FLT6_IRQHandler
+
+        PUBWEAK DFSDM1_FLT7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+        B DFSDM1_FLT7_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RNG_IRQHandler
+        B RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK OCTOSPI1_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+        B HSEM1_IRQHandler
+
+        PUBWEAK DAC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+        B DAC2_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+        B BDMA2_Channel0_IRQHandler
+
+        PUBWEAK BDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+        B BDMA2_Channel1_IRQHandler
+
+        PUBWEAK BDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+        B BDMA2_Channel2_IRQHandler
+
+        PUBWEAK BDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+        B BDMA2_Channel3_IRQHandler
+
+        PUBWEAK BDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+        B BDMA2_Channel4_IRQHandler
+
+        PUBWEAK BDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+        B BDMA2_Channel5_IRQHandler
+
+        PUBWEAK BDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+        B BDMA2_Channel6_IRQHandler
+
+        PUBWEAK BDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+        B BDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+        B ECC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+        B WAKEUP_PIN_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK BDMA1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+        B BDMA1_IRQHandler
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xx.s

@@ -0,0 +1,971 @@
+;/******************************************************************************
+; * @file    startup_stm32h7b0xx.s
+; * @author  MCD Application Team
+; * @brief   STM32H7B0xx devices vector table for EWARM toolchain.
+;*           This module performs:
+;*           - Set the initial SP
+;*           - Set the initial PC == _iar_program_start,
+;*           - Set the vector table entries with the exceptions ISR
+;*           address.
+;*           - Branches to main in the C library (which eventually
+;*           calls main()).
+;*           After Reset the Cortex-M processor is in Thread mode,
+;*           priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+        DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+        DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+        DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+        DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+        DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI
+        DCD     CRYP_IRQHandler                   ; CRYP crypto global interrupt
+        DCD     HASH_RNG_IRQHandler               ; HASH, RNG
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+        DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+        DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+        DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+        DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+        DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+        DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+        DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+        DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+        DCD     BDMA2_Channel0_IRQHandler         ;  BDMA Channel 0 global Interrupt
+        DCD     BDMA2_Channel1_IRQHandler         ;  BDMA Channel 1 global Interrupt
+        DCD     BDMA2_Channel2_IRQHandler         ;  BDMA Channel 2 global Interrupt
+        DCD     BDMA2_Channel3_IRQHandler         ;  BDMA Channel 3 global Interrupt
+        DCD     BDMA2_Channel4_IRQHandler         ;  BDMA Channel 4 global Interrupt
+        DCD     BDMA2_Channel5_IRQHandler         ;  BDMA Channel 5 global Interrupt
+        DCD     BDMA2_Channel6_IRQHandler         ;  BDMA Channel 6 global Interrupt
+        DCD     BDMA2_Channel7_IRQHandler         ;  BDMA Channel 7 global Interrupt
+        DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+        DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+        DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+        DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+        DCD     USART10_IRQHandler                ;  USART10 global interrupt
+        DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt
+        DCD     0                                 ; Reserved
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt
+        DCD     ECC_IRQHandler                    ; ECC
+        DCD     0                                 ; Reserved
+        DCD     DTS_IRQHandler                    ; DTS
+        DCD     0                                 ; Reserved
+        DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+        DCD     OCTOSPI2_IRQHandler               ; OCTOSPI2
+        DCD     OTFDEC1_IRQHandler                ; OTFDEC1
+        DCD     OTFDEC2_IRQHandler                ; OTFDEC2
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU
+        DCD     BDMA1_IRQHandler                  ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+        B DFSDM2_IRQHandler
+
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DFSDM1_FLT4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+        B DFSDM1_FLT4_IRQHandler
+
+        PUBWEAK DFSDM1_FLT5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+        B DFSDM1_FLT5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+        B DFSDM1_FLT6_IRQHandler
+
+        PUBWEAK DFSDM1_FLT7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+        B DFSDM1_FLT7_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK OCTOSPI1_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+        B HSEM1_IRQHandler
+
+        PUBWEAK DAC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+        B DAC2_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+        B BDMA2_Channel0_IRQHandler
+
+        PUBWEAK BDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+        B BDMA2_Channel1_IRQHandler
+
+        PUBWEAK BDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+        B BDMA2_Channel2_IRQHandler
+
+        PUBWEAK BDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+        B BDMA2_Channel3_IRQHandler
+
+        PUBWEAK BDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+        B BDMA2_Channel4_IRQHandler
+
+        PUBWEAK BDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+        B BDMA2_Channel5_IRQHandler
+
+        PUBWEAK BDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+        B BDMA2_Channel6_IRQHandler
+
+        PUBWEAK BDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+        B BDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+        B ECC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+        B WAKEUP_PIN_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        PUBWEAK OTFDEC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+        B OTFDEC2_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK BDMA1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+        B BDMA1_IRQHandler
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32H7xx/Source/Templates/iar/startup_stm32h7b0xxq.s

@@ -0,0 +1,971 @@
+;/******************************************************************************
+; * @file    startup_stm32h7b0xxq.s
+; * @author  MCD Application Team
+; * @brief   STM32H7B0xx devices vector table for EWARM toolchain.
+;*           This module performs:
+;*           - Set the initial SP
+;*           - Set the initial PC == _iar_program_start,
+;*           - Set the vector table entries with the exceptions ISR
+;*           address.
+;*           - Branches to main in the C library (which eventually
+;*           calls main()).
+;*           After Reset the Cortex-M processor is in Thread mode,
+;*           priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+        DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+        DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+        DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+        DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+        DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI
+        DCD     CRYP_IRQHandler                   ; CRYP crypto global interrupt
+        DCD     HASH_RNG_IRQHandler               ; HASH, RNG
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+        DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+        DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+        DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+        DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+        DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+        DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+        DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+        DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+        DCD     BDMA2_Channel0_IRQHandler         ;  BDMA Channel 0 global Interrupt
+        DCD     BDMA2_Channel1_IRQHandler         ;  BDMA Channel 1 global Interrupt
+        DCD     BDMA2_Channel2_IRQHandler         ;  BDMA Channel 2 global Interrupt
+        DCD     BDMA2_Channel3_IRQHandler         ;  BDMA Channel 3 global Interrupt
+        DCD     BDMA2_Channel4_IRQHandler         ;  BDMA Channel 4 global Interrupt
+        DCD     BDMA2_Channel5_IRQHandler         ;  BDMA Channel 5 global Interrupt
+        DCD     BDMA2_Channel6_IRQHandler         ;  BDMA Channel 6 global Interrupt
+        DCD     BDMA2_Channel7_IRQHandler         ;  BDMA Channel 7 global Interrupt
+        DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+        DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+        DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+        DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+        DCD     USART10_IRQHandler                ;  USART10 global interrupt
+        DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt
+        DCD     0                                 ; Reserved
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt
+        DCD     ECC_IRQHandler                    ; ECC
+        DCD     0                                 ; Reserved
+        DCD     DTS_IRQHandler                    ; DTS
+        DCD     0                                 ; Reserved
+        DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+        DCD     OCTOSPI2_IRQHandler               ; OCTOSPI2
+        DCD     OTFDEC1_IRQHandler                ; OTFDEC1
+        DCD     OTFDEC2_IRQHandler                ; OTFDEC2
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU
+        DCD     BDMA1_IRQHandler                  ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+        B DFSDM2_IRQHandler
+
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DFSDM1_FLT4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+        B DFSDM1_FLT4_IRQHandler
+
+        PUBWEAK DFSDM1_FLT5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+        B DFSDM1_FLT5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+        B DFSDM1_FLT6_IRQHandler
+
+        PUBWEAK DFSDM1_FLT7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+        B DFSDM1_FLT7_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK OCTOSPI1_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+        B HSEM1_IRQHandler
+
+        PUBWEAK DAC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+        B DAC2_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+        B BDMA2_Channel0_IRQHandler
+
+        PUBWEAK BDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+        B BDMA2_Channel1_IRQHandler
+
+        PUBWEAK BDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+        B BDMA2_Channel2_IRQHandler
+
+        PUBWEAK BDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+        B BDMA2_Channel3_IRQHandler
+
+        PUBWEAK BDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+        B BDMA2_Channel4_IRQHandler
+
+        PUBWEAK BDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+        B BDMA2_Channel5_IRQHandler
+
+        PUBWEAK BDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+        B BDMA2_Channel6_IRQHandler
+
+        PUBWEAK BDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+        B BDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+        B ECC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+        B WAKEUP_PIN_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        PUBWEAK OTFDEC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+        B OTFDEC2_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK BDMA1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+        B BDMA1_IRQHandler
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xx.s

@@ -0,0 +1,971 @@
+;/******************************************************************************
+; * @file    startup_stm32h7b3xx.s
+; * @author  MCD Application Team
+; * @brief   STM32H7B3xx devices vector table for EWARM toolchain.
+;*           This module performs:
+;*           - Set the initial SP
+;*           - Set the initial PC == _iar_program_start,
+;*           - Set the vector table entries with the exceptions ISR
+;*           address.
+;*           - Branches to main in the C library (which eventually
+;*           calls main()).
+;*           After Reset the Cortex-M processor is in Thread mode,
+;*           priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+        DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+        DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+        DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+        DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+        DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI
+        DCD     CRYP_IRQHandler                   ; CRYP crypto global interrupt
+        DCD     HASH_RNG_IRQHandler               ; HASH, RNG
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+        DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+        DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+        DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+        DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+        DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+        DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+        DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+        DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+        DCD     BDMA2_Channel0_IRQHandler         ;  BDMA Channel 0 global Interrupt
+        DCD     BDMA2_Channel1_IRQHandler         ;  BDMA Channel 1 global Interrupt
+        DCD     BDMA2_Channel2_IRQHandler         ;  BDMA Channel 2 global Interrupt
+        DCD     BDMA2_Channel3_IRQHandler         ;  BDMA Channel 3 global Interrupt
+        DCD     BDMA2_Channel4_IRQHandler         ;  BDMA Channel 4 global Interrupt
+        DCD     BDMA2_Channel5_IRQHandler         ;  BDMA Channel 5 global Interrupt
+        DCD     BDMA2_Channel6_IRQHandler         ;  BDMA Channel 6 global Interrupt
+        DCD     BDMA2_Channel7_IRQHandler         ;  BDMA Channel 7 global Interrupt
+        DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+        DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+        DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+        DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+        DCD     USART10_IRQHandler                ;  USART10 global interrupt
+        DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt
+        DCD     0                                 ; Reserved
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt
+        DCD     ECC_IRQHandler                    ; ECC
+        DCD     0                                 ; Reserved
+        DCD     DTS_IRQHandler                    ; DTS
+        DCD     0                                 ; Reserved
+        DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+        DCD     OCTOSPI2_IRQHandler               ; OCTOSPI2
+        DCD     OTFDEC1_IRQHandler                ; OTFDEC1
+        DCD     OTFDEC2_IRQHandler                ; OTFDEC2
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU
+        DCD     BDMA1_IRQHandler                  ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+        B DFSDM2_IRQHandler
+
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DFSDM1_FLT4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+        B DFSDM1_FLT4_IRQHandler
+
+        PUBWEAK DFSDM1_FLT5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+        B DFSDM1_FLT5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+        B DFSDM1_FLT6_IRQHandler
+
+        PUBWEAK DFSDM1_FLT7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+        B DFSDM1_FLT7_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK OCTOSPI1_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+        B HSEM1_IRQHandler
+
+        PUBWEAK DAC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+        B DAC2_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+        B BDMA2_Channel0_IRQHandler
+
+        PUBWEAK BDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+        B BDMA2_Channel1_IRQHandler
+
+        PUBWEAK BDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+        B BDMA2_Channel2_IRQHandler
+
+        PUBWEAK BDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+        B BDMA2_Channel3_IRQHandler
+
+        PUBWEAK BDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+        B BDMA2_Channel4_IRQHandler
+
+        PUBWEAK BDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+        B BDMA2_Channel5_IRQHandler
+
+        PUBWEAK BDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+        B BDMA2_Channel6_IRQHandler
+
+        PUBWEAK BDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+        B BDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+        B ECC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+        B WAKEUP_PIN_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        PUBWEAK OTFDEC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+        B OTFDEC2_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK BDMA1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+        B BDMA1_IRQHandler
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32H7xx/Source/Templates/iar/startup_stm32h7b3xxq.s

@@ -0,0 +1,971 @@
+;/******************************************************************************
+; * @file    startup_stm32h7b3xxq.s
+; * @author  MCD Application Team
+; * @brief   STM32H7B3xx devices vector table for EWARM toolchain.
+;*           This module performs:
+;*           - Set the initial SP
+;*           - Set the initial PC == _iar_program_start,
+;*           - Set the vector table entries with the exceptions ISR
+;*           address.
+;*           - Branches to main in the C library (which eventually
+;*           calls main()).
+;*           After Reset the Cortex-M processor is in Thread mode,
+;*           priority is Privileged, and the Stack is set to Main.
+;*******************************************************************************
+;* @attention
+;*
+;* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
+;* All rights reserved.</center></h2>
+;*
+;* This software component is licensed by ST under BSD 3-Clause license,
+;* the "License"; You may not use this file except in compliance with the
+;* License. You may obtain a copy of the License at:
+;*                        opensource.org/licenses/BSD-3-Clause
+;*
+;*******************************************************************************
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler                     ; Reset Handler
+
+        DCD     NMI_Handler                       ; NMI Handler
+        DCD     HardFault_Handler                 ; Hard Fault Handler
+        DCD     MemManage_Handler                 ; MPU Fault Handler
+        DCD     BusFault_Handler                  ; Bus Fault Handler
+        DCD     UsageFault_Handler                ; Usage Fault Handler
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     SVC_Handler                       ; SVCall Handler
+        DCD     DebugMon_Handler                  ; Debug Monitor Handler
+        DCD     0                                 ; Reserved
+        DCD     PendSV_Handler                    ; PendSV Handler
+        DCD     SysTick_Handler                   ; SysTick Handler
+
+        ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog Interrupt
+        DCD     PVD_PVM_IRQHandler                ; PVD/PVM through EXTI Line detection
+        DCD     RTC_TAMP_STAMP_CSS_LSE_IRQHandler ; Tamper and TimeStamps through the EXTI line
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line
+        DCD     FLASH_IRQHandler                  ; FLASH
+        DCD     RCC_IRQHandler                    ; RCC
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2
+        DCD     FDCAN1_IT0_IRQHandler             ; FDCAN1 interrupt line 0
+        DCD     FDCAN2_IT0_IRQHandler             ; FDCAN2 interrupt line 0
+        DCD     FDCAN1_IT1_IRQHandler             ; FDCAN1 interrupt line 1
+        DCD     FDCAN2_IT1_IRQHandler             ; FDCAN2 interrupt line 1
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s
+        DCD     TIM1_BRK_IRQHandler               ; TIM1 Break interrupt
+        DCD     TIM1_UP_IRQHandler                ; TIM1 Update
+        DCD     TIM1_TRG_COM_IRQHandler           ; TIM1 Trigger and Commutation Interrupt
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare
+        DCD     TIM2_IRQHandler                   ; TIM2
+        DCD     TIM3_IRQHandler                   ; TIM3
+        DCD     TIM4_IRQHandler                   ; TIM4
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error
+        DCD     SPI1_IRQHandler                   ; SPI1
+        DCD     SPI2_IRQHandler                   ; SPI2
+        DCD     USART1_IRQHandler                 ; USART1
+        DCD     USART2_IRQHandler                 ; USART2
+        DCD     USART3_IRQHandler                 ; USART3
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line
+        DCD     DFSDM2_IRQHandler                 ; DFSDM2 Interrupt
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break Interrupt and TIM12 global interrupt
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update Interrupt and TIM13 global interrupt
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation Interrupt and TIM14 glob
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare Interrupt
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7
+        DCD     FMC_IRQHandler                    ; FMC
+        DCD     SDMMC1_IRQHandler                 ; SDMMC1
+        DCD     TIM5_IRQHandler                   ; TIM5
+        DCD     SPI3_IRQHandler                   ; SPI3
+        DCD     UART4_IRQHandler                  ; UART4
+        DCD     UART5_IRQHandler                  ; UART5
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors
+        DCD     TIM7_IRQHandler                   ; TIM7
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     FDCAN_CAL_IRQHandler              ; FDCAN calibration unit interrupt
+        DCD     DFSDM1_FLT4_IRQHandler            ; DFSDM Filter4 Interrupt
+        DCD     DFSDM1_FLT5_IRQHandler            ; DFSDM Filter5 Interrupt
+        DCD     DFSDM1_FLT6_IRQHandler            ; DFSDM Filter6 Interrupt
+        DCD     DFSDM1_FLT7_IRQHandler            ; DFSDM Filter7 Interrupt
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7
+        DCD     USART6_IRQHandler                 ; USART6
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS
+        DCD     DCMI_PSSI_IRQHandler              ; DCMI, PSSI
+        DCD     CRYP_IRQHandler                   ; CRYP crypto global interrupt
+        DCD     HASH_RNG_IRQHandler               ; HASH, RNG
+        DCD     FPU_IRQHandler                    ; FPU
+        DCD     UART7_IRQHandler                  ; UART7
+        DCD     UART8_IRQHandler                  ; UART8
+        DCD     SPI4_IRQHandler                   ; SPI4
+        DCD     SPI5_IRQHandler                   ; SPI5
+        DCD     SPI6_IRQHandler                   ; SPI6
+        DCD     SAI1_IRQHandler                   ; SAI1
+        DCD     LTDC_IRQHandler                   ; LTDC
+        DCD     LTDC_ER_IRQHandler                ; LTDC error
+        DCD     DMA2D_IRQHandler                  ; DMA2D
+        DCD     SAI2_IRQHandler                   ; SAI2
+        DCD     OCTOSPI1_IRQHandler               ; OCTOSPI1
+        DCD     LPTIM1_IRQHandler                 ; LPTIM1
+        DCD     CEC_IRQHandler                    ; HDMI_CEC
+        DCD     I2C4_EV_IRQHandler                ; I2C4 Event
+        DCD     I2C4_ER_IRQHandler                ; I2C4 Error
+        DCD     SPDIF_RX_IRQHandler               ; SPDIF_RX
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     0                                 ; Reserved
+        DCD     DMAMUX1_OVR_IRQHandler            ; DMAMUX1 Overrun interrupt
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     0                                 ;  Reserved
+        DCD     DFSDM1_FLT0_IRQHandler            ; DFSDM Filter0 Interrupt
+        DCD     DFSDM1_FLT1_IRQHandler            ; DFSDM Filter1 Interrupt
+        DCD     DFSDM1_FLT2_IRQHandler            ; DFSDM Filter2 Interrupt
+        DCD     DFSDM1_FLT3_IRQHandler            ; DFSDM Filter3 Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SWPMI1_IRQHandler                 ;  Serial Wire Interface 1 global interrupt
+        DCD     TIM15_IRQHandler                  ;  TIM15 global Interrupt
+        DCD     TIM16_IRQHandler                  ;  TIM16 global Interrupt
+        DCD     TIM17_IRQHandler                  ;  TIM17 global Interrupt
+        DCD     MDIOS_WKUP_IRQHandler             ;  MDIOS Wakeup  Interrupt
+        DCD     MDIOS_IRQHandler                  ;  MDIOS global Interrupt
+        DCD     JPEG_IRQHandler                   ;  JPEG global Interrupt
+        DCD     MDMA_IRQHandler                   ;  MDMA global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     SDMMC2_IRQHandler                 ;  SDMMC2 global Interrupt
+        DCD     HSEM1_IRQHandler                  ;  HSEM1 global Interrupt
+        DCD     0                                 ;  Reserved
+        DCD     DAC2_IRQHandler                   ;  DAC2 global Interrupt
+        DCD     DMAMUX2_OVR_IRQHandler            ; DMAMUX Overrun interrupt
+        DCD     BDMA2_Channel0_IRQHandler         ;  BDMA Channel 0 global Interrupt
+        DCD     BDMA2_Channel1_IRQHandler         ;  BDMA Channel 1 global Interrupt
+        DCD     BDMA2_Channel2_IRQHandler         ;  BDMA Channel 2 global Interrupt
+        DCD     BDMA2_Channel3_IRQHandler         ;  BDMA Channel 3 global Interrupt
+        DCD     BDMA2_Channel4_IRQHandler         ;  BDMA Channel 4 global Interrupt
+        DCD     BDMA2_Channel5_IRQHandler         ;  BDMA Channel 5 global Interrupt
+        DCD     BDMA2_Channel6_IRQHandler         ;  BDMA Channel 6 global Interrupt
+        DCD     BDMA2_Channel7_IRQHandler         ;  BDMA Channel 7 global Interrupt
+        DCD     COMP_IRQHandler                   ;  COMP global Interrupt
+        DCD     LPTIM2_IRQHandler                 ;  LP TIM2 global interrupt
+        DCD     LPTIM3_IRQHandler                 ;  LP TIM3 global interrupt
+        DCD     UART9_IRQHandler                  ;  UART9 global interrupt
+        DCD     USART10_IRQHandler                ;  USART10 global interrupt
+        DCD     LPUART1_IRQHandler                ;  LP UART1 interrupt
+        DCD     0                                 ; Reserved
+        DCD     CRS_IRQHandler                    ; Clock Recovery Global Interrupt
+        DCD     ECC_IRQHandler                    ; ECC
+        DCD     0                                 ; Reserved
+        DCD     DTS_IRQHandler                    ; DTS
+        DCD     0                                 ; Reserved
+        DCD     WAKEUP_PIN_IRQHandler             ;  Interrupt for all 6 wake-up pins
+        DCD     OCTOSPI2_IRQHandler               ; OCTOSPI2
+        DCD     OTFDEC1_IRQHandler                ; OTFDEC1
+        DCD     OTFDEC2_IRQHandler                ; OTFDEC2
+        DCD     GFXMMU_IRQHandler                 ; GFXMMU
+        DCD     BDMA1_IRQHandler                  ; BDMA1
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT:REORDER(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WWDG_IRQHandler
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_PVM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+PVD_PVM_IRQHandler
+        B PVD_PVM_IRQHandler
+
+        PUBWEAK RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+        B RTC_TAMP_STAMP_CSS_LSE_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_WKUP_IRQHandler
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FLASH_IRQHandler
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RCC_IRQHandler
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI0_IRQHandler
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI1_IRQHandler
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI2_IRQHandler
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI4_IRQHandler
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream0_IRQHandler
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream1_IRQHandler
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream2_IRQHandler
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream3_IRQHandler
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream4_IRQHandler
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream5_IRQHandler
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream6_IRQHandler
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ADC_IRQHandler
+        B ADC_IRQHandler
+
+        PUBWEAK FDCAN1_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT0_IRQHandler
+        B FDCAN1_IT0_IRQHandler
+
+        PUBWEAK FDCAN2_IT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT0_IRQHandler
+        B FDCAN2_IT0_IRQHandler
+
+        PUBWEAK FDCAN1_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN1_IT1_IRQHandler
+        B FDCAN1_IT1_IRQHandler
+
+        PUBWEAK FDCAN2_IT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN2_IT1_IRQHandler
+        B FDCAN2_IT1_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI9_5_IRQHandler
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_BRK_IRQHandler
+        B TIM1_BRK_IRQHandler
+
+        PUBWEAK TIM1_UP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_UP_IRQHandler
+        B TIM1_UP_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_TRG_COM_IRQHandler
+        B TIM1_TRG_COM_IRQHandler
+
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM1_CC_IRQHandler
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM2_IRQHandler
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM3_IRQHandler
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM4_IRQHandler
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_EV_IRQHandler
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C1_ER_IRQHandler
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_EV_IRQHandler
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C2_ER_IRQHandler
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI1_IRQHandler
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI2_IRQHandler
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART1_IRQHandler
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART2_IRQHandler
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART3_IRQHandler
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+EXTI15_10_IRQHandler
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+RTC_Alarm_IRQHandler
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK DFSDM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM2_IRQHandler
+        B DFSDM2_IRQHandler
+
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_BRK_TIM12_IRQHandler
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_UP_TIM13_IRQHandler
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_TRG_COM_TIM14_IRQHandler
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM8_CC_IRQHandler
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA1_Stream7_IRQHandler
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FMC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FMC_IRQHandler
+        B FMC_IRQHandler
+
+        PUBWEAK SDMMC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC1_IRQHandler
+        B SDMMC1_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM5_IRQHandler
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI3_IRQHandler
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART4_IRQHandler
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART5_IRQHandler
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM6_DAC_IRQHandler
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM7_IRQHandler
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream0_IRQHandler
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream1_IRQHandler
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream2_IRQHandler
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream3_IRQHandler
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream4_IRQHandler
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK FDCAN_CAL_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FDCAN_CAL_IRQHandler
+        B FDCAN_CAL_IRQHandler
+
+        PUBWEAK DFSDM1_FLT4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT4_IRQHandler
+        B DFSDM1_FLT4_IRQHandler
+
+        PUBWEAK DFSDM1_FLT5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT5_IRQHandler
+        B DFSDM1_FLT5_IRQHandler
+
+        PUBWEAK DFSDM1_FLT6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT6_IRQHandler
+        B DFSDM1_FLT6_IRQHandler
+
+        PUBWEAK DFSDM1_FLT7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT7_IRQHandler
+        B DFSDM1_FLT7_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream5_IRQHandler
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream6_IRQHandler
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2_Stream7_IRQHandler
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART6_IRQHandler
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_EV_IRQHandler
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C3_ER_IRQHandler
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_OUT_IRQHandler
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_EP1_IN_IRQHandler
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_WKUP_IRQHandler
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTG_HS_IRQHandler
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_PSSI_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DCMI_PSSI_IRQHandler
+        B DCMI_PSSI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRYP_IRQHandler
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HASH_RNG_IRQHandler
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+FPU_IRQHandler
+        B FPU_IRQHandler
+
+        PUBWEAK UART7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART7_IRQHandler
+        B UART7_IRQHandler
+
+        PUBWEAK UART8_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART8_IRQHandler
+        B UART8_IRQHandler
+
+        PUBWEAK SPI4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI4_IRQHandler
+        B SPI4_IRQHandler
+
+        PUBWEAK SPI5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI5_IRQHandler
+        B SPI5_IRQHandler
+
+        PUBWEAK SPI6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPI6_IRQHandler
+        B SPI6_IRQHandler
+
+        PUBWEAK SAI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SAI1_IRQHandler
+        B SAI1_IRQHandler
+
+        PUBWEAK LTDC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_IRQHandler
+        B LTDC_IRQHandler
+
+        PUBWEAK LTDC_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LTDC_ER_IRQHandler
+        B LTDC_ER_IRQHandler
+
+        PUBWEAK DMA2D_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMA2D_IRQHandler
+        B DMA2D_IRQHandler
+
+       PUBWEAK SAI2_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+SAI2_IRQHandler
+        B SAI2_IRQHandler
+
+       PUBWEAK OCTOSPI1_IRQHandler
+       SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI1_IRQHandler
+        B OCTOSPI1_IRQHandler
+
+        PUBWEAK LPTIM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM1_IRQHandler
+        B LPTIM1_IRQHandler
+
+        PUBWEAK CEC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CEC_IRQHandler
+        B CEC_IRQHandler
+
+        PUBWEAK I2C4_EV_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_EV_IRQHandler
+        B I2C4_EV_IRQHandler
+
+        PUBWEAK I2C4_ER_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+I2C4_ER_IRQHandler
+        B I2C4_ER_IRQHandler
+
+        PUBWEAK SPDIF_RX_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SPDIF_RX_IRQHandler
+        B SPDIF_RX_IRQHandler
+
+        PUBWEAK DMAMUX1_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DMAMUX1_OVR_IRQHandler
+        B DMAMUX1_OVR_IRQHandler
+
+        PUBWEAK DFSDM1_FLT0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+
+DFSDM1_FLT0_IRQHandler
+        B DFSDM1_FLT0_IRQHandler
+
+        PUBWEAK DFSDM1_FLT1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT1_IRQHandler
+        B DFSDM1_FLT1_IRQHandler
+
+        PUBWEAK DFSDM1_FLT2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT2_IRQHandler
+        B DFSDM1_FLT2_IRQHandler
+
+        PUBWEAK DFSDM1_FLT3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DFSDM1_FLT3_IRQHandler
+        B DFSDM1_FLT3_IRQHandler
+
+        PUBWEAK SWPMI1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SWPMI1_IRQHandler
+        B SWPMI1_IRQHandler
+
+        PUBWEAK TIM15_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM15_IRQHandler
+        B TIM15_IRQHandler
+
+        PUBWEAK TIM16_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM16_IRQHandler
+        B TIM16_IRQHandler
+
+        PUBWEAK TIM17_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+TIM17_IRQHandler
+        B TIM17_IRQHandler
+
+        PUBWEAK MDIOS_WKUP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_WKUP_IRQHandler
+        B MDIOS_WKUP_IRQHandler
+
+        PUBWEAK MDIOS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDIOS_IRQHandler
+        B MDIOS_IRQHandler
+
+        PUBWEAK JPEG_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+JPEG_IRQHandler
+        B JPEG_IRQHandler
+
+        PUBWEAK MDMA_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+MDMA_IRQHandler
+        B MDMA_IRQHandler
+
+        PUBWEAK SDMMC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+SDMMC2_IRQHandler
+        B SDMMC2_IRQHandler
+
+        PUBWEAK HSEM1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+HSEM1_IRQHandler
+        B HSEM1_IRQHandler
+
+        PUBWEAK DAC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DAC2_IRQHandler
+        B DAC2_IRQHandler
+
+        PUBWEAK DMAMUX2_OVR_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DMAMUX2_OVR_IRQHandler
+        B DMAMUX2_OVR_IRQHandler
+
+        PUBWEAK BDMA2_Channel0_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel0_IRQHandler
+        B BDMA2_Channel0_IRQHandler
+
+        PUBWEAK BDMA2_Channel1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel1_IRQHandler
+        B BDMA2_Channel1_IRQHandler
+
+        PUBWEAK BDMA2_Channel2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel2_IRQHandler
+        B BDMA2_Channel2_IRQHandler
+
+        PUBWEAK BDMA2_Channel3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel3_IRQHandler
+        B BDMA2_Channel3_IRQHandler
+
+        PUBWEAK BDMA2_Channel4_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel4_IRQHandler
+        B BDMA2_Channel4_IRQHandler
+
+        PUBWEAK BDMA2_Channel5_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel5_IRQHandler
+        B BDMA2_Channel5_IRQHandler
+
+        PUBWEAK BDMA2_Channel6_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel6_IRQHandler
+        B BDMA2_Channel6_IRQHandler
+
+        PUBWEAK BDMA2_Channel7_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA2_Channel7_IRQHandler
+        B BDMA2_Channel7_IRQHandler
+
+        PUBWEAK COMP_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+COMP_IRQHandler
+        B COMP_IRQHandler
+
+        PUBWEAK LPTIM2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM2_IRQHandler
+        B LPTIM2_IRQHandler
+
+        PUBWEAK LPTIM3_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPTIM3_IRQHandler
+        B LPTIM3_IRQHandler
+
+        PUBWEAK UART9_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+UART9_IRQHandler
+        B UART9_IRQHandler
+
+        PUBWEAK USART10_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+USART10_IRQHandler
+        B USART10_IRQHandler
+
+        PUBWEAK LPUART1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+LPUART1_IRQHandler
+        B LPUART1_IRQHandler
+
+        PUBWEAK CRS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+CRS_IRQHandler
+        B CRS_IRQHandler
+
+        PUBWEAK ECC_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+ECC_IRQHandler
+        B ECC_IRQHandler
+
+        PUBWEAK DTS_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+DTS_IRQHandler
+        B DTS_IRQHandler
+
+        PUBWEAK WAKEUP_PIN_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+WAKEUP_PIN_IRQHandler
+        B WAKEUP_PIN_IRQHandler
+
+        PUBWEAK OCTOSPI2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OCTOSPI2_IRQHandler
+        B OCTOSPI2_IRQHandler
+
+        PUBWEAK OTFDEC1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC1_IRQHandler
+        B OTFDEC1_IRQHandler
+
+        PUBWEAK OTFDEC2_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+OTFDEC2_IRQHandler
+        B OTFDEC2_IRQHandler
+
+        PUBWEAK GFXMMU_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+GFXMMU_IRQHandler
+        B GFXMMU_IRQHandler
+
+        PUBWEAK BDMA1_IRQHandler
+        SECTION .text:CODE:NOROOT:REORDER(1)
+BDMA1_IRQHandler
+        B BDMA1_IRQHandler
+        END
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

CMSIS/STM32H7xx/Source/Templates/system_stm32h7xx.c

@@ -157,6 +157,7 @@ void SystemInit (void)
   /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */
   RCC->CR &= 0xEAF6ED7FU;
 
+#if defined(D3_SRAM_BASE)
   /* Reset D1CFGR register */
   RCC->D1CFGR = 0x00000000;
 
@@ -165,7 +166,16 @@ void SystemInit (void)
 
   /* Reset D3CFGR register */
   RCC->D3CFGR = 0x00000000;
+#else
+  /* Reset CDCFGR1 register */
+  RCC->CDCFGR1 = 0x00000000;
+
+  /* Reset CDCFGR2 register */
+  RCC->CDCFGR2 = 0x00000000;
 
+  /* Reset SRDCFGR register */
+  RCC->SRDCFGR = 0x00000000;
+#endif
   /* Reset PLLCKSELR register */
   RCC->PLLCKSELR = 0x00000000;
 
@@ -340,6 +350,7 @@ void SystemCoreClockUpdate (void)
   }
 
   /* Compute SystemClock frequency --------------------------------------------------*/
+#if defined (RCC_D1CFGR_D1CPRE)
   tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
 
   /* SystemCoreClock frequency : CM7 CPU frequency  */
@@ -348,6 +359,16 @@ void SystemCoreClockUpdate (void)
   /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency  */
   SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
 
+#else
+  tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
+
+  /* SystemCoreClock frequency : CM7 CPU frequency  */
+  SystemCoreClock >>= tmp;
+
+  /* SystemD2Clock frequency : AXI and AHBs Clock frequency  */
+  SystemD2Clock = (SystemCoreClock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
+
+#endif
 }
 
 

STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h

@@ -7,7 +7,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
   * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
@@ -236,7 +236,12 @@
 #define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 #define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
 
-#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0)
+#if defined(STM32G4) || defined(STM32H7)
+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
+#endif
+
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4)
 #define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
 #define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
 #endif
@@ -301,8 +306,17 @@
 #define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
 #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
 
+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
+#endif
+
 #endif /* STM32L4 */
 
+#if defined(STM32G0)
+#define DMA_REQUEST_DAC1_CHANNEL1                                DMA_REQUEST_DAC1_CH1
+#define DMA_REQUEST_DAC1_CHANNEL2                                DMA_REQUEST_DAC1_CH2
+#endif
+
 #if defined(STM32H7)
 
 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@@ -360,6 +374,9 @@
 #define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
 #define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
 
+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
+
 #endif /* STM32H7 */
 
 /**
@@ -455,7 +472,9 @@
 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
 #define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
-#endif
+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
+#endif /* STM32H7 */
 
 /**
   * @}
@@ -491,7 +510,13 @@
 #define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
 #define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
 #define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
+#if defined(STM32G4)
 
+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
+#endif /* STM32G4 */
 /**
   * @}
   */
@@ -500,7 +525,7 @@
 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
   * @{
   */
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
@@ -553,18 +578,25 @@
 #define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
 #define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
 #define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
-#endif
+
+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
+#endif /* STM32H7 */
 
 #define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
 #define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
 #define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
 
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
 #define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
 #define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
 #define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
 #define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
 
 #if defined(STM32L1)
  #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
@@ -606,6 +638,184 @@
 #define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
 #define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
 
+#if defined(STM32G4)
+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
+#endif /* STM32G4 */
+
+#if defined(STM32H7)
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
+#endif /* STM32H7 */
+
+#if defined(STM32F3)
+/** @brief Constants defining available sources associated to external events.
+  */
+#define HRTIM_EVENTSRC_1              (0x00000000U)
+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
+
+/** @brief Constants defining the events that can be selected to configure the
+  *        set/reset crossbar of a timer output
+  */
+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)
+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)
+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)
+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)
+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)
+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)
+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)
+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)
+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)
+
+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)
+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)
+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)
+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)
+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)
+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)
+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)
+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)
+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)
+
+/** @brief Constants defining the event filtering applied to external events
+  *        by a timer
+  */
+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
+
+/** @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
+
+#endif /* STM32F3 */
 /**
   * @}
   */
@@ -745,7 +955,7 @@
 #define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
 #define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
 
-#if defined(STM32L1) || defined(STM32L4)
+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7)
 #define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
 #define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
 #endif
@@ -836,6 +1046,16 @@
 #define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
 #define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
 
+#if defined(STM32H7)
+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
+
+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
+#endif /* STM32H7 */
+
 /**
   * @}
   */
@@ -1229,6 +1449,30 @@
 
 #define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
 #define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
+
+#if defined(STM32L4) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
+
+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
+
+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
+
+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
+
+#endif  /* STM32L4 || STM32F4 || STM32F7 || STM32H7 */
 /**
   * @}
   */
@@ -1251,6 +1495,13 @@
 #endif
 #define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
+
 /**
   * @}
   */
@@ -1280,16 +1531,18 @@
 
 #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
 
-#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
 #define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
 #define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
 #define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
 #define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)
 #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
 #define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
 #define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
 #define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
-#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 */
+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
 
 #if defined(STM32F4)
 #define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
@@ -1308,6 +1561,13 @@
 /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
   * @{
   */
+
+#if defined(STM32G0)
+#define HAL_PWR_ConfigPVD                                                           HAL_PWREx_ConfigPVD
+#define HAL_PWR_EnablePVD                                                           HAL_PWREx_EnablePVD
+#define HAL_PWR_DisablePVD                                                    HAL_PWREx_DisablePVD
+#define HAL_PWR_PVD_IRQHandler                                            HAL_PWREx_PVD_IRQHandler
+#endif
 #define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
 #define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
 #define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
@@ -1380,14 +1640,14 @@
 #define HAL_TIM_DMAError                                TIM_DMAError
 #define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
 #define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
-#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) || defined(STM32L4)
+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
 #define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
 #define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
 #define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
 #define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
 #define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
 #define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
-#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4  || STM32L0 */
+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
 /**
   * @}
   */
@@ -2985,7 +3245,7 @@
 
 #if defined(STM32L4)
 #define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
-#elif defined(STM32WB) || defined(STM32G0)
+#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
 #else
 #define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
 #endif
@@ -3113,7 +3373,7 @@
 /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
   * @{
   */
-#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx)
+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
 #else
 #define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 #endif
@@ -3229,14 +3489,14 @@
 #define  SDIO_IRQHandler            SDMMC1_IRQHandler
 #endif
 
-#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
 #define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
 #define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
 #define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
 #define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
 #endif
 
-#if defined(STM32H7)
+#if defined(STM32H7) || defined(STM32L5)
 #define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
 #define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
 #define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
@@ -3476,13 +3736,13 @@
 /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
   * @{
   */
-#if defined (STM32H7) || defined (STM32F3)
-#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
-#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
-#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
-#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
-#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
-#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
 #endif
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal.h

@@ -96,6 +96,28 @@ typedef enum
 
 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
 
+/**
+  * @}
+  */
+
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO
+  * @{
+  */
+
+/** @brief  Fast-mode Plus driving capability on a specific GPIO
+  */
+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */
+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */
+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */
+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */
+
+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
+
+#endif /* ! SYSCFG_PMCR_BOOSTEN */
 /**
   * @}
   */
@@ -241,17 +263,16 @@ typedef enum
 #define EXTI_LINE41      ((uint32_t)0x29)
 #define EXTI_LINE42      ((uint32_t)0x2A)
 #define EXTI_LINE43      ((uint32_t)0x2B)
-#define EXTI_LINE44      ((uint32_t)0x2C)
+#define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */
 /* EXTI_LINE45 Reserved */
 #if defined(DUAL_CORE)
 #define EXTI_LINE46      ((uint32_t)0x2E)
 #else
 /* EXTI_LINE46 Reserved */
-#endif
+#endif /* DUAL_CORE */
 #define EXTI_LINE47      ((uint32_t)0x2F)
 #define EXTI_LINE48      ((uint32_t)0x30)
 #define EXTI_LINE49      ((uint32_t)0x31)
-
 #define EXTI_LINE50      ((uint32_t)0x32)
 #define EXTI_LINE51      ((uint32_t)0x33)
 #define EXTI_LINE52      ((uint32_t)0x34)
@@ -262,7 +283,6 @@ typedef enum
 #define EXTI_LINE57      ((uint32_t)0x39)
 #define EXTI_LINE58      ((uint32_t)0x3A)
 #define EXTI_LINE59      ((uint32_t)0x3B)
-
 #define EXTI_LINE60      ((uint32_t)0x3C)
 #define EXTI_LINE61      ((uint32_t)0x3D)
 #define EXTI_LINE62      ((uint32_t)0x3E)
@@ -273,45 +293,40 @@ typedef enum
 #define EXTI_LINE67      ((uint32_t)0x43)
 #define EXTI_LINE68      ((uint32_t)0x44)
 #define EXTI_LINE69      ((uint32_t)0x45)
-
 #define EXTI_LINE70      ((uint32_t)0x46)
 #define EXTI_LINE71      ((uint32_t)0x47)
 #define EXTI_LINE72      ((uint32_t)0x48)
 #define EXTI_LINE73      ((uint32_t)0x49)
 #define EXTI_LINE74      ((uint32_t)0x4A)
-#define EXTI_LINE75      ((uint32_t)0x4B)
-#define EXTI_LINE76      ((uint32_t)0x4C)
-
+#define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */
+#define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */
 #if defined(DUAL_CORE)
 #define EXTI_LINE77      ((uint32_t)0x4D)
 #define EXTI_LINE78      ((uint32_t)0x4E)
 #define EXTI_LINE79      ((uint32_t)0x4F)
-
 #define EXTI_LINE80      ((uint32_t)0x50)
+#else
+/* EXTI_LINE77 Reserved */
+/* EXTI_LINE78 Reserved */
+/* EXTI_LINE79 Reserved */
+/* EXTI_LINE80 Reserved */
+#endif /* DUAL_CORE */
 /* EXTI_LINE81   Reserved */
+#if defined(DUAL_CORE)
 #define EXTI_LINE82      ((uint32_t)0x52)
+#else
+/* EXTI_LINE82 Reserved */
+#endif /* DUAL_CORE */
 /* EXTI_LINE83   Reserved */
+#if defined(DUAL_CORE)
 #define EXTI_LINE84      ((uint32_t)0x54)
-#define EXTI_LINE85      ((uint32_t)0x55)
-#define EXTI_LINE86      ((uint32_t)0x56)
-#define EXTI_LINE87      ((uint32_t)0x57)
-/* EXTI_LINE88   Reserved */
 #else
-/* EXTI_LINE77   Reserved */
-/* EXTI_LINE78   Reserved */
-/* EXTI_LINE79   Reserved */
-/* EXTI_LINE80   Reserved */
-/* EXTI_LINE81   Reserved */
-/* EXTI_LINE82   Reserved */
-/* EXTI_LINE83   Reserved */
-/* EXTI_LINE84   Reserved */
-
+/* EXTI_LINE84 Reserved */
+#endif /* DUAL_CORE */
 #define EXTI_LINE85      ((uint32_t)0x55)
-#define EXTI_LINE86      ((uint32_t)0x56)
+#define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */
 #define EXTI_LINE87      ((uint32_t)0x57)
-
-/* EXTI_LINE88   Reserved */
-#endif
+#define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */
 
 #if defined(DUAL_CORE)
 #define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \
@@ -342,7 +357,7 @@ typedef enum
                                 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \
                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \
                                 ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))
-#endif
+#endif /* DUAL_CORE */
 
 #if defined(DUAL_CORE)
 #define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \
@@ -428,7 +443,8 @@ typedef enum
                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
                                 ((LINE) == EXTI_LINE85) || \
-                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
 #endif /*DUAL_CORE*/
 
 #if defined(DUAL_CORE)
@@ -513,7 +529,8 @@ typedef enum
                                 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \
                                 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \
                                 ((LINE) == EXTI_LINE85) || \
-                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))
+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \
+                                ((LINE) == EXTI_LINE88))
 #endif /*DUAL_CORE*/
 
 #if defined(DUAL_CORE)
@@ -576,7 +593,7 @@ typedef enum
                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
                                 ((LINE) == EXTI_LINE53))
-#else
+#elif (POWER_DOMAINS_NUMBER == 3U)
 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
                                 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
                                 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
@@ -592,17 +609,43 @@ typedef enum
                                 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
                                 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \
                                 ((LINE) == EXTI_LINE53))
-#endif
+#else
+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \
+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \
+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \
+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \
+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \
+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \
+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \
+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \
+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \
+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \
+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \
+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \
+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \
+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))
+#endif /*DUAL_CORE*/
 
 
 #define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/
 #define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/
+#if defined (LPTIM4)
 #define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/
+#else
+#define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/
+#endif /* LPTIM4 */
+#if defined (LPTIM5)
 #define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/
-
+#else
+#define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/
+#endif /* LPTIM5 */
+#if defined (LPTIM4) && defined (LPTIM5)
 #define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
                                  ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))
-
+#else
+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \
+                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))
+#endif /* LPTIM4 LPTIM5 */
 /**
   * @}
   */
@@ -624,6 +667,31 @@ typedef enum
 
 
 /* Exported macro ------------------------------------------------------------*/
+/** @defgroup ART_Exported_Macros ART Exported Macros
+  * @{
+  */
+#if defined(DUAL_CORE)
+
+/** @brief  ART Enable Macro.
+  *         Enable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Disable Macro.
+  *         Disable the Cortex-M4 ART cache.
+  */
+#define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)
+
+/** @brief  ART Cache BaseAddress Config.
+  *         Configure the Cortex-M4 ART cache Base Address.
+  */
+#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))
+
+#endif /* DUAL_CORE */
+/**
+  * @}
+  */
+
 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros
   * @{
   */
@@ -714,6 +782,23 @@ typedef enum
 #define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)
 #endif /* DUAL_CORE */
 
+#if !defined(SYSCFG_PMCR_BOOSTEN)
+/** @brief  Fast-mode Plus driving capability enable/disable macros
+  * @param __FASTMODEPLUS__  This parameter can be a value of :
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
+  */
+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
+                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\
+                                                               }while(0)
+
+#endif /* !SYSCFG_PMCR_BOOSTEN */
 /**
   * @}
   */
@@ -874,6 +959,18 @@ typedef enum
   * @}
   */
 
+/* Exported variables --------------------------------------------------------*/
+
+/** @addtogroup HAL_Exported_Variables
+  * @{
+  */
+extern __IO uint32_t uwTick;
+extern uint32_t uwTickPrio;
+extern HAL_TickFreqTypeDef uwTickFreq;
+/**
+  * @}
+  */
+
 /* Exported functions --------------------------------------------------------*/
 
 /* Initialization and de-initialization functions  ******************************/
@@ -895,11 +992,22 @@ void HAL_ResumeTick(void);
 uint32_t HAL_GetHalVersion(void);
 uint32_t HAL_GetREVID(void);
 uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
+#if defined(SYSCFG_PMCR_EPIS_SEL)
 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);
+#endif /* SYSCFG_PMCR_EPIS_SEL */
 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );
+#if defined(SYSCFG_PMCR_BOOSTEN)
 void HAL_SYSCFG_EnableBOOST(void);
 void HAL_SYSCFG_DisableBOOST(void);
+#endif /* SYSCFG_PMCR_BOOSTEN */
+
+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)
 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/
+
 #if defined(DUAL_CORE)
 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);
 void HAL_SYSCFG_EnableCM7BOOT(void);
@@ -913,6 +1021,9 @@ void HAL_SYSCFG_EnableIOSpeedOptimize(void);
 void HAL_SYSCFG_DisableIOSpeedOptimize(void);
 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);
 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#if defined(SYSCFG_CCCR_NCC_MMC)
+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);
+#endif /* SYSCFG_CCCR_NCC_MMC */
 void HAL_EnableDBGSleepMode(void);
 void HAL_DisableDBGSleepMode(void);
 void HAL_EnableDBGStopMode(void);

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc.h

@@ -22,7 +22,7 @@
 #define STM32H7xx_HAL_ADC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -50,7 +50,7 @@
 typedef struct
 {
   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
-                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+                                               This parameter can be a value between 1 and 1024 */
 
   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
@@ -66,7 +66,7 @@ typedef struct
                                                (the oversampling buffer is zeroed during injection sequence).
                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
 
-}ADC_OversamplingTypeDef;
+} ADC_OversamplingTypeDef;
 
 /**
   * @brief  Structure definition of ADC instance and ADC group regular.
@@ -178,7 +178,7 @@ typedef struct
   ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
                                                Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
 
-}ADC_InitTypeDef;
+} ADC_InitTypeDef;
 
 /**
   * @brief  Structure definition of ADC channel for regular group
@@ -244,7 +244,7 @@ typedef struct
                                              This parameter is applied only for 16-bit or 8-bit resolution.
                                              This parameter can be set to ENABLE or DISABLE. */
 
-}ADC_ChannelConfTypeDef;
+} ADC_ChannelConfTypeDef;
 
 /**
   * @brief  Structure definition of ADC analog watchdog
@@ -291,7 +291,7 @@ typedef struct
                                          impacted: the comparison of analog watchdog thresholds is done
                                          on oversampling intermediate computation (after ratio, before shift
                                          application): intermediate register bitfield [32:7] (26 most significant bits). */
-}ADC_AnalogWDGConfTypeDef;
+} ADC_AnalogWDGConfTypeDef;
 
 /**
   * @brief  ADC group injected contexts queue configuration
@@ -304,7 +304,7 @@ typedef struct
                                               JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
 
   uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
-}ADC_InjectionConfigTypeDef;
+} ADC_InjectionConfigTypeDef;
 
 /** @defgroup ADC_States ADC States
   * @{
@@ -383,7 +383,7 @@ typedef struct
   void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
   void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
-}ADC_HandleTypeDef;
+} ADC_HandleTypeDef;
 
 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
 /**
@@ -618,6 +618,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */
 #define ADC_CHANNEL_DAC1CH1_ADC2           (LL_ADC_CHANNEL_DAC1CH1_ADC2)    /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */
 #define ADC_CHANNEL_DAC1CH2_ADC2           (LL_ADC_CHANNEL_DAC1CH2_ADC2)    /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */
+#if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2)
+#define ADC_CHANNEL_DAC2CH1_ADC2           (LL_ADC_CHANNEL_DAC2CH1_ADC2)    /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */
+#endif
 /**
   * @}
   */
@@ -625,10 +628,10 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 /** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management
   * @{
   */
-#define ADC_CONVERSIONDATA_DR                  ((uint32_t)0x00000000)                            /*!< Regular Conversion data stored in DR register only  */
-#define ADC_CONVERSIONDATA_DFSDM               ((uint32_t)ADC_CFGR_DMNGT_1)                      /*!< DFSDM mode selected */
-#define ADC_CONVERSIONDATA_DMA_ONESHOT         ((uint32_t)ADC_CFGR_DMNGT_0)                      /*!< DMA one shot mode selected */
-#define ADC_CONVERSIONDATA_DMA_CIRCULAR        ((uint32_t)(ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)) /*!< DMA circular mode selected */
+#define ADC_CONVERSIONDATA_DR                  (0x00000000UL)                          /*!< Regular Conversion data stored in DR register only  */
+#define ADC_CONVERSIONDATA_DFSDM               (ADC_CFGR_DMNGT_1)                      /*!< DFSDM mode selected */
+#define ADC_CONVERSIONDATA_DMA_ONESHOT         (ADC_CFGR_DMNGT_0)                      /*!< DMA one shot mode selected */
+#define ADC_CONVERSIONDATA_DMA_CIRCULAR        (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)   /*!< DMA circular mode selected */
 /**
   * @}
   */
@@ -656,23 +659,6 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @}
   */
 
-/** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
-  * @{
-  */
-#define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)   /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)   /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)   /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)  /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)  /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)  /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_512         (LL_ADC_OVS_RATIO_512) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-#define ADC_OVERSAMPLING_RATIO_1024        (LL_ADC_OVS_RATIO_1024) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */
-/**
-  * @}
-  */
-
 /** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
   * @{
   */
@@ -849,10 +835,15 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @param __HANDLE__: ADC handle
   * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)
   */
+#if defined (ADC3)
 #define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)                                   \
        (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \
      ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)                              \
      :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL))
+#else
+#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)     ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)
+
+#endif
 
 /**
   * @brief Simultaneously clear and set specific bits of the handle State.
@@ -1078,10 +1069,10 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
   do{                                                                          \
-     (__HANDLE__)->State = HAL_ADC_STATE_RESET;                               \
-     (__HANDLE__)->MspInitCallback = NULL;                                     \
-     (__HANDLE__)->MspDeInitCallback = NULL;                                   \
-    } while(0)
+    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
+    (__HANDLE__)->MspInitCallback = NULL;                                      \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
+  } while(0)
 #else
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
   ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
@@ -1242,7 +1233,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @retval Value between Min_Data=0 and Max_Data=18
   */
 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
-         __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
 
 /**
   * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
@@ -1286,7 +1277,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
   */
 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
-         __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
 
 /**
   * @brief  Helper macro to determine whether the selected channel
@@ -1339,7 +1330,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
   */
 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
-         __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
 
 /**
   * @brief  Helper macro to convert a channel defined from parameter
@@ -1406,7 +1397,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         @arg @ref ADC_CHANNEL_18
   */
 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
-         __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
 
 /**
   * @brief  Helper macro to determine whether the internal channel
@@ -1435,7 +1426,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         Value "1" if the internal channel selected is available on the ADC instance selected.
   */
 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
-         __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
 
 /**
   * @brief  Helper macro to get the ADC multimode conversion data of ADC master
@@ -1451,7 +1442,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
   */
 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
-         __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
 
 /**
   * @brief  Helper macro to select the ADC common instance
@@ -1464,7 +1455,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @retval ADC common register instance
   */
 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
-         __LL_ADC_COMMON_INSTANCE((__ADCx__))
+  __LL_ADC_COMMON_INSTANCE((__ADCx__))
 
 /**
   * @brief  Helper macro to check if all ADC instances sharing the same
@@ -1484,7 +1475,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   *         is enabled.
   */
 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
-         __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
 
 /**
   * @brief  Helper macro to define the ADC conversion data full-scale digital
@@ -1501,7 +1492,7 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @retval ADC conversion data full-scale digital value
   */
 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
-         __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to convert the ADC conversion data from
@@ -1526,9 +1517,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
                                           __ADC_RESOLUTION_CURRENT__,\
                                           __ADC_RESOLUTION_TARGET__)            \
-         __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
-                                          (__ADC_RESOLUTION_CURRENT__),\
-                                          (__ADC_RESOLUTION_TARGET__))
+  __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \
+                                   (__ADC_RESOLUTION_CURRENT__),                \
+                                   (__ADC_RESOLUTION_TARGET__))
 
 /**
   * @brief  Helper macro to calculate the voltage (unit: mVolt)
@@ -1550,9 +1541,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
                                        __ADC_DATA__,\
                                        __ADC_RESOLUTION__)                     \
-         __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
-                                       (__ADC_DATA__),\
-                                       (__ADC_RESOLUTION__))
+  __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \
+                                (__ADC_DATA__),                                \
+                                (__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to calculate analog reference voltage (Vref+)
@@ -1582,8 +1573,8 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   */
 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
                                           __ADC_RESOLUTION__)                  \
-         __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
-                                          (__ADC_RESOLUTION__))
+  __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \
+                                  (__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1634,9 +1625,9 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
                                    __TEMPSENSOR_ADC_DATA__,\
                                    __ADC_RESOLUTION__)                         \
-         __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
-                                   (__TEMPSENSOR_ADC_DATA__),\
-                                   (__ADC_RESOLUTION__))
+  __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \
+                            (__TEMPSENSOR_ADC_DATA__),                         \
+                            (__ADC_RESOLUTION__))
 
 /**
   * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
@@ -1689,12 +1680,12 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
                                               __VREFANALOG_VOLTAGE__,\
                                               __TEMPSENSOR_ADC_DATA__,\
                                               __ADC_RESOLUTION__)              \
-         __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
-                                              (__TEMPSENSOR_TYP_CALX_V__),\
-                                              (__TEMPSENSOR_CALX_TEMP__),\
-                                              (__VREFANALOG_VOLTAGE__),\
-                                              (__TEMPSENSOR_ADC_DATA__),\
-                                              (__ADC_RESOLUTION__))
+  __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \
+                                      (__TEMPSENSOR_TYP_CALX_V__),             \
+                                      (__TEMPSENSOR_CALX_TEMP__),              \
+                                      (__VREFANALOG_VOLTAGE__),                \
+                                      (__TEMPSENSOR_ADC_DATA__),               \
+                                      (__ADC_RESOLUTION__))
 
 /**
   * @}
@@ -1717,14 +1708,15 @@ typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
   * @{
   */
 /* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
 HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
 
 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
 /* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
 /**
@@ -1738,39 +1730,39 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
 /* IO operation functions  *****************************************************/
 
 /* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
 
 /* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
 
 /* Non-blocking mode: DMA */
-HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
 
 /* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
+uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
 
 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
 void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
 /**
   * @}
   */
 
 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions
- * @{
- */
+  *  @brief    Peripheral Control functions
+  * @{
+  */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
 
 /**
   * @}
@@ -1780,7 +1772,7 @@ HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana
 /** @addtogroup ADC_Exported_Functions_Group4
   * @{
   */
-uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
+uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
 uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 
 /**
@@ -1795,9 +1787,9 @@ uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
 /** @addtogroup ADC_Private_Functions ADC Private Functions
   * @{
   */
-HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup);
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
 void ADC_DMAError(DMA_HandleTypeDef *hdma);

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_adc_ex.h

@@ -22,7 +22,7 @@
 #define STM32H7xx_HAL_ADC_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -47,11 +47,11 @@
 typedef struct
 {
   uint32_t Ratio;                         /*!< Configures the oversampling ratio.
-                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+                                               This parameter can be a value between 1 and 1024 */
 
   uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
                                                This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
-}ADC_InjOversamplingTypeDef;
+} ADC_InjOversamplingTypeDef;
 
 /**
   * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
@@ -179,7 +179,7 @@ typedef struct
   ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
                                                       Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
                                                       Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
-}ADC_InjectionConfTypeDef;
+} ADC_InjectionConfTypeDef;
 
 /**
   * @brief  Structure definition of ADC multimode
@@ -202,7 +202,7 @@ typedef struct
                                    from 1 to 8 clock cycles for 12 bits
                                    from 1 to 6 clock cycles for 10 bits
                                    from 1 to 6 clock cycles for 8 bits     */
-}ADC_MultiModeTypeDef;
+} ADC_MultiModeTypeDef;
 
 /**
   * @}
@@ -455,6 +455,7 @@ typedef struct
   * @note  When multimode feature is not available, the macro always returns SET.
   * @retval SET (ADC is independent) or RESET (ADC is not).
   */
+#if defined (ADC3)
 #define ADC_IS_INDEPENDENT(__HANDLE__)    \
   ( ( ( ((__HANDLE__)->Instance) == ADC3) \
     )?                                    \
@@ -462,6 +463,7 @@ typedef struct
      :                                    \
      RESET                                \
   )
+#endif
 
 /**
   * @brief Set the selected injected Channel rank.
@@ -575,6 +577,15 @@ typedef struct
   * @param __OFFSET__: Value to be shifted
   * @retval None
   */
+#if defined(ADC_VER_V5_3)
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \
+        (                                                                                                       \
+           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                           \
+              ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                   \
+               :                                                                                                \
+               ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
+        )
+#else
 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \
         (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                      \
           ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                       \
@@ -584,6 +595,7 @@ typedef struct
                :                                                                                                \
                ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
         )
+#endif /* ADC_VER_V5_3 */
 
 /**
   * @brief Shift the AWD1 threshold in function of the selected ADC resolution.
@@ -598,6 +610,15 @@ typedef struct
   * @param __THRESHOLD__: Value to be shifted
   * @retval None
   */
+#if defined(ADC_VER_V5_3)
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                             \
+        (                                                                                                         \
+           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                             \
+            ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
+              :                                                                                                   \
+              ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
+        )
+#else
 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                             \
         (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                        \
          ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                       \
@@ -607,6 +628,7 @@ typedef struct
               :                                                                                                   \
               ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
         )
+#endif /* ADC_VER_V5_3 */
 
 /**
   * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.
@@ -621,6 +643,15 @@ typedef struct
   * @param __THRESHOLD__: Value to be shifted
   * @retval None
   */
+#if defined(ADC_VER_V5_3)
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                              \
+        (                                                                                                           \
+            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                              \
+              ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \
+                :                                                                                                   \
+                ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
+        )
+#else
 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                              \
         (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                          \
           ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                        \
@@ -630,6 +661,7 @@ typedef struct
                 :                                                                                                   \
                 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \
         )
+#endif /* ADC_VER_V5_3 */
 /**
   * @brief Clear Common Control Register.
   * @param __HANDLE__ ADC handle.
@@ -641,18 +673,21 @@ typedef struct
   * @retval Common control register
   */
 #define ADC12_COMMON_REGISTER(__HANDLE__)   (ADC12_COMMON)
+#if defined (ADC3)
 /**
   * @brief Report common register to ADC3
   * @param __HANDLE__: ADC handle
   * @retval Common control register
   */
 #define ADC3_COMMON_REGISTER(__HANDLE__)   (ADC3_COMMON)
+#endif
 /**
   * @brief Report Master Instance
   * @param __HANDLE__: ADC handle
   * @note return same instance if ADC of input handle is independent ADC
   * @retval Master Instance
   */
+#if defined (ADC3)
 #define ADC_MASTER_REGISTER(__HANDLE__)                                          \
   ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \
     )?                                                                           \
@@ -660,6 +695,9 @@ typedef struct
      :                                                                           \
      (ADC1)                                                                      \
   )
+#else
+#define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))
+#endif
 
 /**
   * @brief Check whether or not dual regular conversions are enabled
@@ -688,7 +726,7 @@ typedef struct
      :                                                                         \
      ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
   )
-
+#if defined (ADC3)
 /**
   * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master
   * @param __HANDLE__: ADC handle
@@ -701,13 +739,13 @@ typedef struct
      :                                                                         \
      ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \
   )
-
+#endif
 /**
   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled
   * @param __HANDLE__: ADC handle
   * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
   */
-
+#if defined (ADC3)
 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \
     )?                                                                      \
@@ -716,13 +754,23 @@ typedef struct
      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
+#else
+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \
+  ( ( ((__HANDLE__)->Instance == ADC1)                                      \
+    )?                                                                      \
+     SET                                                                    \
+     :                                                                      \
+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \
+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \
+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
+#endif
 
 /**
   * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled
   * @param __HANDLE__: ADC handle
   * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
   */
-
+#if defined (ADC3)
 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \
   ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \
     )?                                                                     \
@@ -731,6 +779,16 @@ typedef struct
      ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
        ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+#else
+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \
+  ( ( ((__HANDLE__)->Instance == ADC1)                                    \
+    )?                                                                     \
+     SET                                                                   \
+     :                                                                     \
+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \
+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \
+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
+#endif
 
 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE    | \
                                                                                                       ADC_CCR_PRESC     | \
@@ -757,21 +815,33 @@ typedef struct
   * @param __HANDLE__ ADC handle.
   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
   */
+#if defined(ADC3)
 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)
+#else
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
+#endif
 
 /**
   * @brief Verify the ADC instance connected to the battery voltage VBAT.
   * @param __HANDLE__ ADC handle.
   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
   */
+#if defined(ADC3)
 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)
+#else
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
+#endif
 
 /**
   * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
   * @param __HANDLE__ ADC handle.
   * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
   */
+#if defined(ADC3)
 #define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)
+#else
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)
+#endif
 
 /**
   * @brief Verify the length of scheduled injected conversions group.
@@ -924,24 +994,24 @@ typedef struct
   * @param __EDGE__ programmed ADC edge trigger setting.
   * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
   */
-#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)        || \
-                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
-                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
-                                           ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
 
 /**
   * @brief Verify the ADC multimode setting.
   * @param __MODE__ programmed ADC multimode setting.
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */
-#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)          || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
-                               ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
-                               ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
-                               ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
-                               ((__MODE__) == ADC_DUALMODE_INTERL)                || \
-                               ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
+                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
+                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \
+                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
 
 /**
   * @brief Verify the ADC dual data mode setting.
@@ -994,28 +1064,28 @@ typedef struct
   * @param __CONVERSION__ ADC conversion group.
   * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
   */
-#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)     || \
-                                             ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
-                                             ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
+                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
+                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
 
 /**
   * @brief Verify the ADC event type.
   * @param __EVENT__ ADC event.
   * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
   */
-#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
-                                     ((__EVENT__) == ADC_AWD_EVENT)    || \
-                                     ((__EVENT__) == ADC_AWD2_EVENT)   || \
-                                     ((__EVENT__) == ADC_AWD3_EVENT)   || \
-                                     ((__EVENT__) == ADC_OVR_EVENT)    || \
-                                     ((__EVENT__) == ADC_JQOVF_EVENT)  )
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
+                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
+                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
+                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
+                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
+                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )
 
 /**
   * @brief Verify the ADC oversampling ratio.
   * @param RATIO: programmed ADC oversampling ratio.
   * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)
   */
-#define IS_ADC_OVERSAMPLING_RATIO(RATIO)  ((RATIO) < 1024UL)
+#define IS_ADC_OVERSAMPLING_RATIO(RATIO)  (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))
 
 /**
   * @brief Verify the ADC oversampling shift.
@@ -1093,20 +1163,22 @@ typedef struct
 /* IO operation functions *****************************************************/
 
 /* ADC calibration */
-HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff);
 uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
-HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t* LinearCalib_Buffer);
+HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
 HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
 HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);
+HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc);
+
 
 /* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
 
 /* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
 
 /* ADC multimode */
 HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
@@ -1114,20 +1186,20 @@ HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
 uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
 
 /* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
+uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
 
 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
+void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
 
 /* ADC group regular conversions stop */
-HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
 
 /**
   * @}
@@ -1137,12 +1209,12 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
 HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);
-HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
+HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_comp.h

@@ -178,6 +178,9 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   */
 #define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */
 #define COMP_INPUT_PLUS_IO2            (COMP_CFGRx_INPSEL)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */
+#if defined (COMP_CFGRx_INP2SEL)
+#define COMP_INPUT_PLUS_DAC2_CH1       (COMP_CFGRx_INP2SEL)   /*!< Comparator input plus 2 connected to (DAC2_CH1 for COMP1) */
+#endif
 /**
   * @}
   */
@@ -185,14 +188,18 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
 /** @defgroup COMP_InputMinus COMP input minus (inverting input)
   * @{
   */
-#define COMP_INPUT_MINUS_1_4VREFINT     (                                                                  COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
-#define COMP_INPUT_MINUS_1_2VREFINT     (                                            COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
-#define COMP_INPUT_MINUS_3_4VREFINT     (                      COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
-#define COMP_INPUT_MINUS_VREFINT        (                      COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                 )          /*!< Comparator input minus connected to VrefInt */
-#define COMP_INPUT_MINUS_DAC1_CH1       (COMP_CFGRx_INMSEL_2                                            )                                               /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
-#define COMP_INPUT_MINUS_DAC1_CH2       (COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0)                                               /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
-#define COMP_INPUT_MINUS_IO1            (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                      )                                               /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
-#define COMP_INPUT_MINUS_IO2            (COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0)                                               /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
+#define COMP_INPUT_MINUS_1_4VREFINT     (                                                                                        COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 1/4 VrefInt */
+#define COMP_INPUT_MINUS_1_2VREFINT     (                                                                  COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 1/2 VrefInt */
+#define COMP_INPUT_MINUS_3_4VREFINT     (                                            COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 3/4 VrefInt */
+#define COMP_INPUT_MINUS_VREFINT        (                                            COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                   )    /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1       (                      COMP_CFGRx_INMSEL_2                                                                                   )    /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */
+#define COMP_INPUT_MINUS_DAC1_CH2       (                      COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */
+#define COMP_INPUT_MINUS_IO1            (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                                                             )    /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */
+#define COMP_INPUT_MINUS_IO2            (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */
+#if defined (COMP_CFGRx_INMSEL_3)
+#define COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3                                                                                                         )    /*!< Comparator input minus connected to (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2) */
+#define COMP_INPUT_MINUS_VBAT_VDDAP     (COMP_CFGRx_INMSEL_3                                             | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to (VBAT/4 for COMP1, VDDAP for COMP2) */
+#endif
 /**
   * @}
   */
@@ -212,7 +219,7 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @{
   */
 #define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000)  /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
-#define COMP_OUTPUTPOL_INVERTED        (COMP_CFGRx_POLARITY)     /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
+#define COMP_OUTPUTPOL_INVERTED        (COMP_CFGRx_POLARITY)   /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
 /**
   * @}
   */
@@ -314,7 +321,7 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @retval None
   */
 #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \
                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
                                                      (__HANDLE__)->MspInitCallback = NULL;            \
                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
@@ -400,8 +407,8 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
   * @retval None
   */
-#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do {                                           \
+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();  \
                                                                __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \
                                                              } while(0)
 
@@ -410,8 +417,8 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
   * @retval None
   */
-#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \
-                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do {                                            \
+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();  \
                                                                __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \
                                                              } while(0)
 
@@ -536,8 +543,8 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
   * @retval None
   */
-#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do {                                           \
+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();  \
                                                                __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \
                                                              } while(0)
 
@@ -545,8 +552,8 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
   * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
   * @retval None
   */
-#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do { \
-                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do {                                           \
+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();  \
                                                                __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \
                                                              } while(0)
 /**
@@ -800,12 +807,28 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
                                              ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \
                                              ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )
 
-
+#if defined (COMP_CFGRx_INP2SEL)
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_DAC2_CH1))
+#else
 #define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
                                                                ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
+#endif
 
 
-
+#if defined (COMP_CFGRx_INMSEL_3)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)        || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)       || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)       || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)            || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)            || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_TPSENS_DAC2CH1) || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VBAT_VDDAP))
+#else
 #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
@@ -814,7 +837,7 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \
                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
                                                                  ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))
-
+#endif
 
 #define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
                                              ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
@@ -824,7 +847,7 @@ typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
 #define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
                                              ((__POL__) == COMP_OUTPUTPOL_INVERTED))
 
-#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)            || \
+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)      || \
                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)  || \
                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)  || \
                                              ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)  || \

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_conf_template.h

@@ -46,11 +46,13 @@
 #define HAL_DFSDM_MODULE_ENABLED
 #define HAL_DMA_MODULE_ENABLED
 #define HAL_DMA2D_MODULE_ENABLED
+#define HAL_DTS_MODULE_ENABLED
 #define HAL_DSI_MODULE_ENABLED
 #define HAL_ETH_MODULE_ENABLED
 #define HAL_EXTI_MODULE_ENABLED
 #define HAL_FDCAN_MODULE_ENABLED
 #define HAL_FLASH_MODULE_ENABLED
+#define HAL_GFXMMU_MODULE_ENABLED
 #define HAL_GPIO_MODULE_ENABLED
 #define HAL_HASH_MODULE_ENABLED
 #define HAL_HCD_MODULE_ENABLED
@@ -69,8 +71,11 @@
 #define HAL_NAND_MODULE_ENABLED
 #define HAL_NOR_MODULE_ENABLED
 #define HAL_OPAMP_MODULE_ENABLED
+#define HAL_OSPI_MODULE_ENABLED
+#define HAL_OTFDEC_MODULE_ENABLED
 #define HAL_PCD_MODULE_ENABLED
 #define HAL_PWR_MODULE_ENABLED
+#define HAL_PSSI_MODULE_ENABLED
 #define HAL_QSPI_MODULE_ENABLED
 #define HAL_RAMECC_MODULE_ENABLED
 #define HAL_RCC_MODULE_ENABLED
@@ -160,6 +165,7 @@
 #define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */
 #define  USE_RTOS                     0
 #define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */
+#define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */
 
 #define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */
 #define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */
@@ -170,6 +176,7 @@
 #define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */
 #define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */
 #define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */
+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */
 #define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */
 #define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */
 #define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */
@@ -178,24 +185,33 @@
 #define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */
 #define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */
 #define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */
+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */
 #define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */
 #define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */
 #define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */
+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */
 #define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */
 #define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */
 #define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */
 #define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */
 #define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */
+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */
+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */
 #define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */
 #define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */
 #define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */
 #define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */
 #define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */
+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */
+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */
 #define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */
 #define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */
 #define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */
 #define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */
 #define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */
+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */
+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */
 #define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */
 
 /* ########################### Ethernet Configuration ######################### */
@@ -258,6 +274,10 @@
   #include "stm32h7xx_hal_dfsdm.h"
 #endif /* HAL_DFSDM_MODULE_ENABLED */
 
+#ifdef HAL_DTS_MODULE_ENABLED
+ #include "stm32h7xx_hal_dts.h"
+#endif /* HAL_DTS_MODULE_ENABLED */
+
 #ifdef HAL_ETH_MODULE_ENABLED
   #include "stm32h7xx_hal_eth.h"
 #endif /* HAL_ETH_MODULE_ENABLED */
@@ -302,6 +322,10 @@
   #include "stm32h7xx_hal_flash.h"
 #endif /* HAL_FLASH_MODULE_ENABLED */
 
+#ifdef HAL_GFXMMU_MODULE_ENABLED
+  #include "stm32h7xx_hal_gfxmmu.h"
+#endif /* HAL_GFXMMU_MODULE_ENABLED */
+
 #ifdef HAL_HRTIM_MODULE_ENABLED
   #include "stm32h7xx_hal_hrtim.h"
 #endif /* HAL_HRTIM_MODULE_ENABLED */
@@ -358,6 +382,18 @@
 #include "stm32h7xx_hal_opamp.h"
 #endif /* HAL_OPAMP_MODULE_ENABLED */
 
+#ifdef HAL_OSPI_MODULE_ENABLED
+ #include "stm32h7xx_hal_ospi.h"
+#endif /* HAL_OSPI_MODULE_ENABLED */
+
+#ifdef HAL_OTFDEC_MODULE_ENABLED
+#include "stm32h7xx_hal_otfdec.h"
+#endif /* HAL_OTFDEC_MODULE_ENABLED */
+
+#ifdef HAL_PSSI_MODULE_ENABLED
+ #include "stm32h7xx_hal_pssi.h"
+#endif /* HAL_PSSI_MODULE_ENABLED */
+
 #ifdef HAL_PWR_MODULE_ENABLED
  #include "stm32h7xx_hal_pwr.h"
 #endif /* HAL_PWR_MODULE_ENABLED */
@@ -368,7 +404,7 @@
 
 #ifdef HAL_RAMECC_MODULE_ENABLED
  #include "stm32h7xx_hal_ramecc.h"
-#endif /* HAL_HCD_MODULE_ENABLED */
+#endif /* HAL_RAMECC_MODULE_ENABLED */
 
 #ifdef HAL_RNG_MODULE_ENABLED
  #include "stm32h7xx_hal_rng.h"

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_crc.h

@@ -267,7 +267,6 @@ typedef struct
 #define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \
                                         ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))
 
-
 #define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \
                                        ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))
 

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_cryp.h

@@ -64,6 +64,9 @@ typedef struct
   uint32_t HeaderSize;                /*!< The size of header buffer in word  */
   uint32_t *B0;                       /*!< B0 is first authentication block used only  in AES CCM mode */
   uint32_t DataWidthUnit;             /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/
+  uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization
+                                           Vector only once and to skip configuration for consecutive processings.
+                                           This parameter can be a value of @ref CRYP_Configuration_Skip */
 
 } CRYP_ConfigTypeDef;
 
@@ -121,6 +124,13 @@ typedef struct
 
   uint32_t                          Version;          /*!< CRYP1 IP version*/
 
+  uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when
+                                                           configuration can be skipped */
+
+  uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored
+                                                           for a single signature computation after several
+                                                           messages processing */
+
 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
   void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */
   void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */
@@ -279,6 +289,16 @@ typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< point
   * @}
   */
 
+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode
+  * @{
+  */
+
+#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */
+#define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */
+
+/**
+  * @}
+  */
 
 /**
   * @}
@@ -461,6 +481,9 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
                                    ((DATATYPE) == CRYP_DATATYPE_8B) || \
                                    ((DATATYPE) == CRYP_DATATYPE_1B))
 
+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
+                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
+
 /**
   * @}
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac.h

@@ -22,16 +22,17 @@
 #define STM32H7xx_HAL_DAC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
-/** @addtogroup STM32H7xx_HAL_Driver
-  * @{
-  */
+#if defined(DAC1) || defined(DAC2)
 
 /** @addtogroup DAC
   * @{
@@ -54,7 +55,7 @@ typedef enum
   HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
   HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
 
-}HAL_DAC_StateTypeDef;
+} HAL_DAC_StateTypeDef;
 
 /**
   * @brief  DAC handle Structure definition
@@ -78,20 +79,20 @@ typedef struct
   __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
 
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
-  void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
-  void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
-  void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
-  void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
-  void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
-
-  void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
-  void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
+  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);
+
+  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);
+  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
 
-}DAC_HandleTypeDef;
+} DAC_HandleTypeDef;
 
 /**
   * @brief   DAC Configuration sample and hold Channel structure definition
@@ -109,8 +110,7 @@ typedef struct
   uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
                                           This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-}
-DAC_SampleAndHoldConfTypeDef;
+} DAC_SampleAndHoldConfTypeDef;
 
 /**
   * @brief   DAC Configuration regular Channel structure definition
@@ -139,7 +139,7 @@ typedef struct
 
   DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
 
-}DAC_ChannelConfTypeDef;
+} DAC_ChannelConfTypeDef;
 
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 /**
@@ -155,8 +155,8 @@ typedef enum
   HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
   HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
   HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
-  HAL_DAC_MSP_INIT_CB_ID                     = 0x08U,  /*!< DAC MspInit Callback ID           */
-  HAL_DAC_MSP_DEINIT_CB_ID                   = 0x09U,  /*!< DAC MspDeInit Callback ID         */
+  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
+  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
   HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
 } HAL_DAC_CallbackIDTypeDef;
 
@@ -187,6 +187,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 #define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -194,108 +195,116 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 /** @defgroup DAC_trigger_selection DAC trigger selection
   * @{
   */
-#define DAC_TRIGGER_NONE                   0x00000000U        /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
-#define DAC_TRIGGER_SOFTWARE               (DAC_CR_TEN1)     /*!< Conversion started by software trigger for DAC channel */
-#define DAC_TRIGGER_T1_TRGO                (DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO                (DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                (DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T5_TRGO                (DAC_CR_TSEL1_2 |DAC_CR_TEN1)   /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T6_TRGO                (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T8_TRGO                (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T15_TRGO               (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_HR1_TRGO1              (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_HR1_TRGO2              (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LP1_OUT                (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LP1 OUT TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_LP2_OUT                (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LP2 OUT TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9                (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_NONE                0x00000000U                                                                       /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_SOFTWARE            (                                                                    DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T1_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO             (                                  DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO             (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T5_TRGO             (                 DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T6_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T8_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO            (DAC_CR_TSEL1_3                                                    | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */
+#if defined(HRTIM1)
+#define DAC_TRIGGER_HR1_TRGO1           (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_HR1_TRGO2           (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */
+#endif
+#define DAC_TRIGGER_LPTIM1_OUT          (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_LPTIM2_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#if defined(TIM23)
+#define DAC_TRIGGER_T23_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */
+#endif
+#if defined(TIM24)
+#define DAC_TRIGGER_T24_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */
+#endif
+#if defined(DAC2)
+#define DAC_TRIGGER_LPTIM3_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */
+#endif
+
 /**
   * @}
   */
 
-  /** @defgroup DAC_output_buffer DAC output buffer
+/** @defgroup DAC_output_buffer DAC output buffer
   * @{
   */
 #define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
-#define DAC_OUTPUTBUFFER_DISABLE           DAC_MCR_MODE1_1
+#define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
 
-  /**
+/**
   * @}
   */
 
-/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+/** @defgroup DAC_Channel_selection DAC Channel selection
   * @{
   */
-#define DAC_CHIPCONNECT_DISABLE      0x00000000U
-#define DAC_CHIPCONNECT_ENABLE       DAC_MCR_MODE1_0
-
+#define DAC_CHANNEL_1                      0x00000000U
+#define DAC_CHANNEL_2                      0x00000010U
 /**
   * @}
   */
 
-/** @defgroup DAC_UserTrimming DAC User Trimming
+/** @defgroup DAC_data_alignment DAC data alignment
   * @{
   */
-
-#define DAC_TRIMMING_FACTORY        0x00000000U           /*!< Factory trimming */
-#define DAC_TRIMMING_USER           0x00000001U           /*!< User trimming */
+#define DAC_ALIGN_12B_R                    0x00000000U
+#define DAC_ALIGN_12B_L                    0x00000004U
+#define DAC_ALIGN_8B_R                     0x00000008U
 
 /**
   * @}
   */
 
-/** @defgroup DAC_SampleAndHold DAC Sample and hold
+/** @defgroup DAC_flags_definition DAC flags definition
   * @{
   */
-#define DAC_SAMPLEANDHOLD_DISABLE     0x00000000U
-#define DAC_SAMPLEANDHOLD_ENABLE      DAC_MCR_MODE1_2
-
+#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
+#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
 
 /**
   * @}
   */
 
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
+/** @defgroup DAC_IT_definition  DAC IT definition
   * @{
   */
-#define DAC_CHANNEL_1                       0x00000000U
-#define DAC_CHANNEL_2                       0x00000010U
+#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
+#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
 
 /**
   * @}
   */
 
-/** @defgroup DAC_data_alignment DAC data alignment
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
   * @{
   */
-#define DAC_ALIGN_12B_R                     0x00000000U
-#define DAC_ALIGN_12B_L                     0x00000004U
-#define DAC_ALIGN_8B_R                      0x00000008U
+#define DAC_CHIPCONNECT_EXTERNAL       (1UL << 0)
+#define DAC_CHIPCONNECT_INTERNAL       (1UL << 1)
+#define DAC_CHIPCONNECT_BOTH           (1UL << 2)
+
 /**
   * @}
   */
 
-/** @defgroup DAC_flags_definition DAC flags definition
+/** @defgroup DAC_UserTrimming DAC User Trimming
   * @{
   */
-#define DAC_FLAG_DMAUDR1                    DAC_SR_DMAUDR1
-#define DAC_FLAG_DMAUDR2                    DAC_SR_DMAUDR2
-
+#define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */
+#define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */
 /**
   * @}
   */
 
-/** @defgroup DAC_IT_definition  DAC IT definition
+/** @defgroup DAC_SampleAndHold DAC power mode
   * @{
   */
-#define DAC_IT_DMAUDR1                    DAC_SR_DMAUDR1
-#define DAC_IT_DMAUDR2                    DAC_SR_DMAUDR2
+#define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)
+#define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
 
 /**
   * @}
   */
-
 /**
   * @}
   */
@@ -313,8 +322,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
                                                       (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback   = NULL;                  \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;                  \
+                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
                                                      } while(0)
 #else
 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
@@ -326,7 +335,7 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @retval None
   */
 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
 
 /** @brief Disable the DAC channel.
   * @param  __HANDLE__ specifies the DAC handle
@@ -334,32 +343,32 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @retval None
   */
 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
 
 /** @brief Set DHR12R1 alignment.
   * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
-#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
 
 /** @brief  Set DHR12R2 alignment.
   * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
-#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014U + (__ALIGNMENT__))
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
 
 /** @brief  Set DHR12RD alignment.
   * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
-#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
 
 /** @brief Enable the DAC interrupt.
   * @param  __HANDLE__ specifies the DAC handle
   * @param  __INTERRUPT__ specifies the DAC interrupt.
   *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
   * @retval None
   */
 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
@@ -368,8 +377,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @param  __HANDLE__ specifies the DAC handle
   * @param  __INTERRUPT__ specifies the DAC interrupt.
   *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
   * @retval None
   */
 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
@@ -378,8 +387,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @param __HANDLE__ DAC handle
   * @param __INTERRUPT__ DAC interrupt source to check
   *          This parameter can be any combination of the following values:
-  *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
-  *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt
   * @retval State of interruption (SET or RESET)
   */
 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
@@ -388,8 +397,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @param  __HANDLE__ specifies the DAC handle.
   * @param  __FLAG__ specifies the DAC flag to get.
   *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
   * @retval None
   */
 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
@@ -398,8 +407,8 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @param  __HANDLE__ specifies the DAC handle.
   * @param  __FLAG__ specifies the DAC flag to clear.
   *          This parameter can be any combination of the following values:
-  *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
-  *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag
   * @retval None
   */
 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
@@ -417,15 +426,15 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
                                            ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
 
 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                ((CHANNEL) == DAC_CHANNEL_2))
+                                 ((CHANNEL) == DAC_CHANNEL_2))
 
 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
                              ((ALIGN) == DAC_ALIGN_12B_L) || \
                              ((ALIGN) == DAC_ALIGN_8B_R))
 
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
 
-#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFU)
+#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)
 
 /**
   * @}
@@ -444,35 +453,39 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
   * @{
   */
 /* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
 
 /**
   * @}
   */
 
 /** @addtogroup DAC_Exported_Functions_Group2
- * @{
- */
+  * @{
+  */
 /* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+                                    uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
 /* DAC callback registering/unregistering */
-HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId, pDAC_CallbackTypeDef pCallback);
-HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackId);
+HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+                                               pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
 /**
   * @}
   */
@@ -481,8 +494,8 @@ HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DA
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
 /**
   * @}
   */
@@ -491,7 +504,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
   * @{
   */
 /* Peripheral State and Error functions ***************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);
 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
 
 /**
@@ -502,10 +515,22 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
   * @}
   */
 
+/** @defgroup DAC_Private_Functions DAC Private Functions
+  * @{
+  */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
 /**
   * @}
   */
 
+/**
+  * @}
+  */
+
+#endif /* DAC1 || DAC2 */
+
 /**
   * @}
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dac_ex.h

@@ -22,16 +22,18 @@
 #define STM32H7xx_HAL_DAC_EX_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
 
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(DAC1) || defined(DAC2)
+
 /** @addtogroup DACEx
   * @{
   */
@@ -47,33 +49,35 @@
 /** @defgroup DACEx_Exported_Constants DACEx Exported Constants
   * @{
   */
+
 /** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
   * @{
   */
-#define DAC_LFSRUNMASK_BIT0                0x00000000U                                                                  /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             (                                                             DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             (                                            DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             (                                            DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             (                           DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             (                           DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             (                           DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             (                           DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                             ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                             | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                            | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                            | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            0x00000000U                                                                   /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            (                                                             DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            (                                            DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           (                                            DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           (                           DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           (                           DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          (                           DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          (                           DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                             ) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                             | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                            | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                            | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+#define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
 /**
   * @}
   */
@@ -90,22 +94,54 @@
 /** @defgroup DACEx_Private_Macros DACEx Private Macros
   * @{
   */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1) || \
-                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2) || \
-                                 ((TRIGGER) == DAC_TRIGGER_LP1_OUT) || \
-                                 ((TRIGGER) == DAC_TRIGGER_LP2_OUT) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
+#if defined(HRTIM1)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1)  || \
+                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2)  || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
                                  ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#elif defined(DAC2)
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#else
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \
+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \
+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \
+                                 ((TRIGGER) == DAC_TRIGGER_T23_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_T24_TRGO)   || \
+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
+#endif
 
 #define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
 
@@ -114,16 +150,16 @@
 #define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
                                     ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
 
-
 #define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
 
 #define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
 
-#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_DISABLE) || \
-                                         ((CONNECT) == DAC_CHIPCONNECT_ENABLE))
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_BOTH))
 
-#define IS_DAC_TRIMMING(TRIMMING)       (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
-                                        ((TRIMMING) == DAC_TRIMMING_USER))
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+                                   ((TRIMMING) == DAC_TRIMMING_USER))
 
 #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
                                                       ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
@@ -149,8 +185,6 @@
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
                                                       ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-
-
 /**
   * @}
   */
@@ -161,22 +195,28 @@
 /** @addtogroup DACEx_Exported_Functions
   * @{
   */
-  /** @addtogroup DACEx_Exported_Functions_Group2
- * @{
- */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+  * @{
+  */
 /* IO operation functions *****************************************************/
 
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
 
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,
+                                          uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
 
-HAL_StatusTypeDef HAL_DACEx_SelfCalibrate (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel, uint32_t NewTrimmingValue);
 
 /**
   * @}
@@ -187,8 +227,10 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming (DAC_HandleTypeDef* hdac, DAC_Channe
   */
 /* Peripheral Control functions ***********************************************/
 
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DACEx_GetTrimOffset (DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+                                            uint32_t NewTrimmingValue);
+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);
 
 /**
   * @}
@@ -212,14 +254,15 @@ void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
   * @}
   */
 
- /**
- * @}
- */
-
 /**
   * @}
   */
 
+#endif /* DAC1 || DAC2 */
+
+/**
+  * @}
+  */
 
 #ifdef __cplusplus
 }

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dcmi.h

@@ -53,7 +53,7 @@ typedef enum
   HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */
   HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */
   HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */
-}HAL_DCMI_StateTypeDef;
+} HAL_DCMI_StateTypeDef;
 
 /**
   * @brief   DCMI Embedded Synchronisation CODE Init structure definition
@@ -64,8 +64,18 @@ typedef struct
   uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */
   uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */
   uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */
-}DCMI_CodesInitTypeDef;
+} DCMI_CodesInitTypeDef;
 
+/**
+  * @brief   DCMI Embedded Synchronisation UNMASK Init structure definition
+  */
+typedef struct
+{
+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */
+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */
+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */
+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */
+} DCMI_SyncUnmaskTypeDef;
 /**
   * @brief   DCMI Init structure definition
   */
@@ -106,7 +116,7 @@ typedef struct
 
   uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd
                                             This parameter can be a value of @ref DCMI_Line_Select_Start     */
-}DCMI_InitTypeDef;
+} DCMI_InitTypeDef;
 
 /**
   * @brief  DCMI handle Structure definition
@@ -138,17 +148,14 @@ typedef struct
   __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */
 
 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-  void    (* LineEventCallback)  ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Line Event callback  */
-  void    (* FrameEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Frame Event callback */
-  void    (* VsyncEventCallback) ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Vsync Event callback */
-  void    (* ErrorCallback)      ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Error callback       */
-
-  void    (* MspInitCallback)    ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Msp Init callback    */
-  void    (* MspDeInitCallback)  ( struct __DCMI_HandleTypeDef * hdcmi);    /*!< DCMI Msp DeInit callback  */
-
-#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
-
-}DCMI_HandleTypeDef;
+  void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Frame Event Callback */
+  void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Vsync Event Callback */
+  void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Line Event Callback  */
+  void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi);            /*!< DCMI Error Callback       */
+  void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);          /*!< DCMI Msp Init callback    */
+  void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Msp DeInit callback  */
+#endif  /* USE_HAL_DCMI_REGISTER_CALLBACKS */
+} DCMI_HandleTypeDef;
 
 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
 /**
@@ -156,14 +163,14 @@ typedef struct
   */
 typedef enum
 {
-  HAL_DCMI_FRAME_EVENT_CB_ID = 0x00U,    /*!< DCMI Frame event Callback ID   */
-  HAL_DCMI_VSYNC_EVENT_CB_ID = 0x01U,    /*!< DCMI Vsync event Callback ID   */
-  HAL_DCMI_LINE_EVENT_CB_ID  = 0x02U,    /*!< DCMI Line event Callback ID    */
-  HAL_DCMI_ERROR_CB_ID       = 0x03U,    /*!< DCMI Error Callback ID         */
-  HAL_DCMI_MSPINIT_CB_ID     = 0x04U,    /*!< DCMI MspInit callback ID       */
-  HAL_DCMI_MSPDEINIT_CB_ID   = 0x05U     /*!< DCMI MspDeInit callback ID     */
+  HAL_DCMI_FRAME_EVENT_CB_ID    = 0x00U,    /*!< DCMI Frame Event Callback ID */
+  HAL_DCMI_VSYNC_EVENT_CB_ID    = 0x01U,    /*!< DCMI Vsync Event Callback ID */
+  HAL_DCMI_LINE_EVENT_CB_ID     = 0x02U,    /*!< DCMI Line Event Callback ID  */
+  HAL_DCMI_ERROR_CB_ID          = 0x03U,    /*!< DCMI Error Callback ID       */
+  HAL_DCMI_MSPINIT_CB_ID        = 0x04U,    /*!< DCMI MspInit callback ID     */
+  HAL_DCMI_MSPDEINIT_CB_ID      = 0x05U     /*!< DCMI MspDeInit callback ID   */
 
-}HAL_DCMI_CallbackIDTypeDef;
+} HAL_DCMI_CallbackIDTypeDef;
 
 /**
   * @brief  HAL DCMI Callback pointer definition
@@ -183,13 +190,13 @@ typedef  void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef * hdcmi); /*!< pointer
 /** @defgroup DCMI_Error_Code DCMI Error Code
   * @{
   */
-#define HAL_DCMI_ERROR_NONE      (0x00000000U)    /*!< No error              */
-#define HAL_DCMI_ERROR_OVR       (0x00000001U)    /*!< Overrun error         */
-#define HAL_DCMI_ERROR_SYNC      (0x00000002U)    /*!< Synchronization error */
-#define HAL_DCMI_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */
-#define HAL_DCMI_ERROR_DMA       (0x00000040U)    /*!< DMA error             */
+#define HAL_DCMI_ERROR_NONE             (0x00000000U)  /*!< No error              */
+#define HAL_DCMI_ERROR_OVR              (0x00000001U)  /*!< Overrun error         */
+#define HAL_DCMI_ERROR_SYNC             (0x00000002U)  /*!< Synchronization error */
+#define HAL_DCMI_ERROR_TIMEOUT          (0x00000020U)  /*!< Timeout error         */
+#define HAL_DCMI_ERROR_DMA              (0x00000040U)  /*!< DMA error             */
 #if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)
-#define  HAL_DCMI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */
+#define  HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U)    /*!< Invalid Callback error  */
 #endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */
 /**
   * @}
@@ -553,6 +560,7 @@ void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
 HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
 HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
 HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
+HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);
 
 /**
   * @}
@@ -578,8 +586,8 @@ uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
 /** @defgroup DCMI_Private_Constants DCMI Private Constants
   * @{
   */
-#define DCMI_MIS_INDEX        (0x1000) /*!< DCMI MIS register index */
-#define DCMI_SR_INDEX         (0x2000) /*!< DCMI SR register index  */
+#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */
+#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */
 /**
   * @}
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm.h

@@ -49,7 +49,7 @@ typedef enum
   HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
   HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
   HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */
-}HAL_DFSDM_Channel_StateTypeDef;
+} HAL_DFSDM_Channel_StateTypeDef;
 
 /**
   * @brief  DFSDM channel output clock structure definition
@@ -61,20 +61,20 @@ typedef struct
                                    This parameter can be a value of @ref DFSDM_Channel_OuputClock */
   uint32_t        Divider;    /*!< Output clock divider.
                                    This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
-}DFSDM_Channel_OutputClockTypeDef;
+} DFSDM_Channel_OutputClockTypeDef;
 
 /**
   * @brief  DFSDM channel input structure definition
   */
 typedef struct
 {
-  uint32_t Multiplexer; /*!< Input is external serial inputs ,internal register or ADC output.
+  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.
                              This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
   uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
                              This parameter can be a value of @ref DFSDM_Channel_DataPacking */
   uint32_t Pins;        /*!< Input pins are taken from same or following channel.
                              This parameter can be a value of @ref DFSDM_Channel_InputPins */
-}DFSDM_Channel_InputTypeDef;
+} DFSDM_Channel_InputTypeDef;
 
 /**
   * @brief  DFSDM channel serial interface structure definition
@@ -85,7 +85,7 @@ typedef struct
                           This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
   uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
                           This parameter can be a value of @ref DFSDM_Channel_SpiClock */
-}DFSDM_Channel_SerialInterfaceTypeDef;
+} DFSDM_Channel_SerialInterfaceTypeDef;
 
 /**
   * @brief  DFSDM channel analog watchdog structure definition
@@ -96,7 +96,7 @@ typedef struct
                               This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
   uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
                               This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
-}DFSDM_Channel_AwdTypeDef;
+} DFSDM_Channel_AwdTypeDef;
 
 /**
   * @brief  DFSDM channel init structure definition
@@ -111,7 +111,7 @@ typedef struct
                                                              This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
   uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.
                                                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-}DFSDM_Channel_InitTypeDef;
+} DFSDM_Channel_InitTypeDef;
 
 /**
   * @brief  DFSDM channel handle structure definition
@@ -131,7 +131,7 @@ typedef struct
   void (*MspInitCallback)   (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */
   void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */
 #endif
-}DFSDM_Channel_HandleTypeDef;
+} DFSDM_Channel_HandleTypeDef;
 
 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /**
@@ -143,7 +143,7 @@ typedef enum
   HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */
   HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */
   HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */
-}HAL_DFSDM_Channel_CallbackIDTypeDef;
+} HAL_DFSDM_Channel_CallbackIDTypeDef;
 
 /**
   * @brief  DFSDM channel callback pointer definition
@@ -162,7 +162,7 @@ typedef enum
   HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */
   HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
   HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */
-}HAL_DFSDM_Filter_StateTypeDef;
+} HAL_DFSDM_Filter_StateTypeDef;
 
 /**
   * @brief  DFSDM filter regular conversion parameters structure definition
@@ -173,7 +173,7 @@ typedef struct
                                  This parameter can be a value of @ref DFSDM_Filter_Trigger */
   FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
   FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */
-}DFSDM_Filter_RegularParamTypeDef;
+} DFSDM_Filter_RegularParamTypeDef;
 
 /**
   * @brief  DFSDM filter injected conversion parameters structure definition
@@ -188,7 +188,7 @@ typedef struct
                                        This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
   uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
                                        This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
-}DFSDM_Filter_InjectedParamTypeDef;
+} DFSDM_Filter_InjectedParamTypeDef;
 
 /**
   * @brief  DFSDM filter parameters structure definition
@@ -201,7 +201,7 @@ typedef struct
                                  This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
   uint32_t IntOversampling; /*!< Integrator oversampling ratio.
                                  This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
-}DFSDM_Filter_FilterParamTypeDef;
+} DFSDM_Filter_FilterParamTypeDef;
 
 /**
   * @brief  DFSDM filter init structure definition
@@ -211,7 +211,7 @@ typedef struct
   DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */
   DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
   DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */
-}DFSDM_Filter_InitTypeDef;
+} DFSDM_Filter_InitTypeDef;
 
 /**
   * @brief  DFSDM filter handle structure definition
@@ -265,7 +265,7 @@ typedef struct
                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
   uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.
                                  This parameter can be a values combination of @ref DFSDM_BreakSignals */
-}DFSDM_Filter_AwdParamTypeDef;
+} DFSDM_Filter_AwdParamTypeDef;
 
 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)
 /**
@@ -280,7 +280,7 @@ typedef enum
   HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */
   HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */
   HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */
-}HAL_DFSDM_Filter_CallbackIDTypeDef;
+} HAL_DFSDM_Filter_CallbackIDTypeDef;
 
 /**
   * @brief  DFSDM filter callback pointer definition
@@ -362,10 +362,10 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
   * @{
   */
-#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */
-#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0  /*!< Sinc 1 filter type */
-#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1  /*!< Sinc 2 filter type */
-#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD    /*!< Sinc 3 filter type */
+#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */
+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */
 /**
   * @}
   */
@@ -374,7 +374,7 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
   * @{
   */
 #define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */
-#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0  */
+#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */
 #define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */
 /**
   * @}
@@ -383,22 +383,28 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
   * @{
   */
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO       0x00000000U                                       /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2      DFSDM_FLTCR1_JEXTSEL_0                            /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO       DFSDM_FLTCR1_JEXTSEL_1                            /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2      (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0, 1 and 2 */
-#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO       DFSDM_FLTCR1_JEXTSEL_2                            /*!< For DFSDM 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)                         /*!< For DFSDM 0, 1 and 2 */
-#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1       (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)                        /*!< For DFSDM 3 */
-#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM 0 and 1 */
-#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO       DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO       0x00000000U                                       /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2      DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO       DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2      (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO       DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)                         /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1       (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)                        /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO       DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */
 #define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)
 #define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)
-#define DFSDM_FILTER_EXT_TRIG_EXTI11          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_EXTI15          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)                           /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)                           /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)  /*!< For DFSDM 0, 1, 2 and 3 */
-#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)                           /*!< For DFSDM 0, 1, 2 and 3 */
+#define DFSDM_FILTER_EXT_TRIG_EXTI11          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_EXTI15          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)                           /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)                           /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)  /*!< For all DFSDM filters */
+#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)                           /*!< For all DFSDM filters */
+#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
+#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
+                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)
+#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \
+                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)
+#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */
 /**
   * @}
   */
@@ -416,11 +422,11 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
   * @{
   */
-#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                              /*!< FastSinc filter type */
-#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                      /*!< Sinc 1 filter type */
-#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                      /*!< Sinc 2 filter type */
+#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */
+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */
+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */
 #define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
-#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                      /*!< Sinc 4 filter type */
+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */
 #define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
 /**
   * @}
@@ -429,8 +435,8 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
   * @{
   */
-#define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U    /*!< From digital filter */
-#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL       /*!< From analog watchdog channel */
+#define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */
+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */
 /**
   * @}
   */
@@ -545,6 +551,11 @@ typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdf
   */
 /* End of exported macros ----------------------------------------------------*/
 
+#if defined(DFSDM_CHDLYR_PLSSKP)
+/* Include DFSDM HAL Extension module */
+#include "stm32h7xx_hal_dfsdm_ex.h"
+#endif /* DFSDM_CHDLYR_PLSSKP */
+
 /* Exported functions --------------------------------------------------------*/
 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
   * @{
@@ -662,15 +673,15 @@ HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsd
 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
-                                              DFSDM_Filter_AwdParamTypeDef* awdParam);
+                                              DFSDM_Filter_AwdParamTypeDef *awdParam);
 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 
-int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
-int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);
 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
 
 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
@@ -739,6 +750,24 @@ uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
                                                        ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
+#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)
+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \
+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))
+#else
 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \
                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
@@ -755,6 +784,7 @@ uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \
                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \
                                                        ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))
+#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx  || STM32H7B0xxQ */
 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \
                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \
                                                        ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
@@ -781,9 +811,27 @@ uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDe
 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))
 #define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \
                                                        ((MODE) == DFSDM_CONTINUOUS_CONV_ON))
+#if defined(DFSDM2_Channel0)
+#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Channel0) || \
+                                                       ((INSTANCE) == DFSDM1_Channel1) || \
+                                                       ((INSTANCE) == DFSDM1_Channel2) || \
+                                                       ((INSTANCE) == DFSDM1_Channel3) || \
+                                                       ((INSTANCE) == DFSDM1_Channel4) || \
+                                                       ((INSTANCE) == DFSDM1_Channel5) || \
+                                                       ((INSTANCE) == DFSDM1_Channel6) || \
+                                                       ((INSTANCE) == DFSDM1_Channel7))
+#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE)           (((INSTANCE) == DFSDM1_Filter0) || \
+                                                       ((INSTANCE) == DFSDM1_Filter1) || \
+                                                       ((INSTANCE) == DFSDM1_Filter2) || \
+                                                       ((INSTANCE) == DFSDM1_Filter3) || \
+                                                       ((INSTANCE) == DFSDM1_Filter4) || \
+                                                       ((INSTANCE) == DFSDM1_Filter5) || \
+                                                       ((INSTANCE) == DFSDM1_Filter6) || \
+                                                       ((INSTANCE) == DFSDM1_Filter7))
+#endif /* DFSDM2_Channel0 */
 /**
-* @}
-*/
+  * @}
+  */
 /* End of private macros -----------------------------------------------------*/
 
 /**

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dfsdm_ex.h

@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dfsdm_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DFSDM HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_DFSDM_EX_H
+#define STM32H7xx_HAL_DFSDM_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(DFSDM_CHDLYR_PLSSKP)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DFSDMEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions
+  * @{
+  */
+
+/** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions
+  * @{
+  */
+
+HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);
+HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros
+  * @{
+  */
+
+#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE)   ((VALUE) < 64U)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DFSDM_CHDLYR_PLSSKP */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_DFSDM_EX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma.h

@@ -308,7 +308,12 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */
 #define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */
 
-#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request      */
+#if defined (PSSI)
+#define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */
+#define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */
+#else
+#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */
+#endif /* PSSI */
 
 #define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */
 #define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */
@@ -336,12 +341,14 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/
 #define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/
 
+#if defined(HRTIM1)
 #define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */
 #define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */
 #define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */
 #define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */
 #define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */
 #define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */
+#endif /* HRTIM1 */
 
 #define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */
 #define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */
@@ -359,10 +366,24 @@ typedef struct __DMA_HandleTypeDef
 #define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */
 #define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */
 
+#if defined(SAI3)
 #define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */
 #define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */
+#endif /* SAI3 */
 
+#if defined(ADC3)
 #define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */
+#endif /* ADC3 */
+
+#if defined(UART9)
+#define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */
+#define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */
+#endif /* UART9 */
+
+#if defined(USART10)
+#define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */
+#define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */
+#endif /* USART10 */
 
 
 /* DMAMUX2 requests */
@@ -381,9 +402,19 @@ typedef struct __DMA_HandleTypeDef
 #define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */
 #define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */
 #define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */
+#if defined(SAI4)
 #define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */
 #define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */
+#endif /* SAI4 */
+#if defined(ADC3)
 #define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */
+#endif /* ADC3 */
+#if defined(DAC2)
+#define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */
+#endif /* DAC2 */
+#if defined(DFSDM2_Channel0)
+#define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */
+#endif /* DFSDM1_Channel0 */
 
 /**
   * @}
@@ -649,6 +680,42 @@ typedef struct __DMA_HandleTypeDef
   * @param  __HANDLE__: DMA handle
   * @retval The specified transfer complete flag index.
   */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\
+ (uint32_t)0x00000000)
+#else
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
@@ -675,12 +742,49 @@ typedef struct __DMA_HandleTypeDef
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\
  (uint32_t)0x00000000)
+#endif /* BDMA1 */
 
 /**
   * @brief  Return the current DMA Stream half transfer complete flag.
   * @param  __HANDLE__: DMA handle
   * @retval The specified half transfer complete flag index.
   */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\
+ (uint32_t)0x00000000)
+#else
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
@@ -707,12 +811,49 @@ typedef struct __DMA_HandleTypeDef
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\
  (uint32_t)0x00000000)
+#endif /* BDMA1 */
 
 /**
   * @brief  Return the current DMA Stream transfer error flag.
   * @param  __HANDLE__: DMA handle
   * @retval The specified transfer error flag index.
   */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\
+ (uint32_t)0x00000000)
+#else
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
@@ -739,6 +880,7 @@ typedef struct __DMA_HandleTypeDef
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\
  (uint32_t)0x00000000)
+#endif /* BDMA1 */
 
 /**
   * @brief  Return the current DMA Stream FIFO error flag.
@@ -793,6 +935,26 @@ typedef struct __DMA_HandleTypeDef
   * @param  __HANDLE__: DMA handle
   * @retval The specified transfer error flag index.
   */
+#if defined(BDMA1)
+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\
+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\
+ (uint32_t)0x00000000)
+#else
 #define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\
 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\
@@ -803,6 +965,7 @@ typedef struct __DMA_HandleTypeDef
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\
  ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\
   (uint32_t)0x00000000)
+#endif /* BDMA1 */
 
 /**
   * @brief  Get the DMA Stream pending flags.
@@ -817,11 +980,20 @@ typedef struct __DMA_HandleTypeDef
   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
   * @retval The state of FLAG (SET or RESET).
   */
+#if defined(BDMA1)
+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#else
 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\
  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
+#endif /* BDMA1 */
 
 /**
   * @brief  Clear the DMA Stream pending flags.
@@ -836,11 +1008,20 @@ typedef struct __DMA_HandleTypeDef
   *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
   * @retval None
   */
+#if defined(BDMA1)
+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\
+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#else
 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\
  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
  ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
+#endif /* BDMA1 */
 
 #define DMA_TO_BDMA_IT(__DMA_IT__) \
 ((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\
@@ -1019,9 +1200,17 @@ uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
   * @{
   */
 
+#if defined(ADC3)
 #define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))
+#else
+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))
+#endif /* ADC3 */
 
+#if defined(ADC3)
 #define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))
+#else
+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))
+#endif /* ADC3 */
 
 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
                                      ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma2d.h

@@ -32,6 +32,8 @@
   * @{
   */
 
+#if defined (DMA2D)
+
 /** @addtogroup DMA2D DMA2D
   * @brief DMA2D HAL module driver
   * @{
@@ -78,7 +80,11 @@ typedef struct
                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
 
 
+  uint32_t             BytesSwap;         /*!< Select byte regular mode or bytes swap mode (two by two).
+                                               This parameter can be one value of @ref DMA2D_Bytes_Swap. */
 
+  uint32_t             LineOffsetMode;    /*!< Configures how is expressed the line offset for the foreground, background and output.
+                                               This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */
 
 } DMA2D_InitTypeDef;
 
@@ -199,7 +205,9 @@ typedef  void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
 #define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */
 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */
 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */
-#define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
+#define DMA2D_R2M                   (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */
+#define DMA2D_M2M_BLEND_FG          DMA2D_CR_MODE_2                     /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */
+#define DMA2D_M2M_BLEND_BG          (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */
 /**
   * @}
   */
@@ -266,7 +274,23 @@ typedef  void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Poin
 
 
 
+/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode
+  * @{
+  */
+#define DMA2D_LOM_PIXELS            0x00000000U   /*!< Line offsets expressed in pixels */
+#define DMA2D_LOM_BYTES             DMA2D_CR_LOM  /*!< Line offsets expressed in bytes */
+/**
+  * @}
+  */
 
+/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap
+  * @{
+  */
+#define DMA2D_BYTES_REGULAR         0x00000000U      /*!< Bytes in regular order in output FIFO */
+#define DMA2D_BYTES_SWAP            DMA2D_OPFCCR_SB  /*!< Bytes are swapped two by two in output FIFO */
+/**
+  * @}
+  */
 
 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling
   * @{
@@ -486,6 +510,8 @@ HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
@@ -607,8 +633,9 @@ uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
   */
 #define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))
 
-#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
-                                               ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
+#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)          || ((MODE) == DMA2D_M2M_PFC) || \
+                                               ((MODE) == DMA2D_M2M_BLEND)    || ((MODE) == DMA2D_R2M)     || \
+                                               ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))
 
 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
@@ -636,7 +663,11 @@ uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
                                    ((RB_Swap) == DMA2D_RB_SWAP))
 
+#define IS_DMA2D_LOM_MODE(LOM)          (((LOM) == DMA2D_LOM_PIXELS) || \
+                                         ((LOM) == DMA2D_LOM_BYTES))
 
+#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \
+                                         ((BYTES_SWAP) == DMA2D_BYTES_SWAP))
 
 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS)  || \
                                            ((CSS) == DMA2D_CSS_422) || \
@@ -659,11 +690,12 @@ uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
   * @}
   */
 
+#endif /* defined (DMA2D) */
+
 /**
   * @}
   */
 
-
 #ifdef __cplusplus
 }
 #endif

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dma_ex.h

@@ -177,8 +177,12 @@ typedef struct
 #define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */
 #define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */
 #define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */
+#if defined(LPTIM4)
 #define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */
+#endif /* LPTIM4 */
+#if defined(LPTIM5)
 #define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */
+#endif /* LPTIM5 */
 #define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */
 #define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */
 #define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */
@@ -190,8 +194,10 @@ typedef struct
 #define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */
 #define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */
 #define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */
+#if defined(ADC3)
 #define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */
 #define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
+#endif /* ADC3 */
 #define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */
 #define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */
 

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_dts.h

@@ -0,0 +1,483 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_dts.h
+  * @author  MCD Application Team
+  * @brief   Header file of DTS HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_DTS_H
+#define __STM32H7xx_HAL_DTS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(DTS)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup DTS
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup DTS_Exported_Types DTS Exported Types
+  * @{
+  */
+
+/**
+  * @brief  DTS Init structure definition
+  */
+typedef struct
+{
+  uint32_t QuickMeasure;  /*!< Specifies the quick measure option selection of the DTS sensor.
+                               This parameter can be a value of @ref DTS_Quick_Measurement */
+
+  uint32_t RefClock;      /*!< Specifies the reference clock selection of the DTS sensor.
+                               This parameter can be a value of @ref DTS_Reference_Clock_Selection */
+
+  uint32_t TriggerInput;  /*!< Specifies the trigger input of the DTS sensor.
+                               This parameter can be a value of @ref DTS_TriggerConfig */
+
+  uint32_t SamplingTime;  /*!< Specifies the sampling time configuration.
+                               This parameter can be a value of @ref DTS_Sampling_Time */
+
+  uint32_t Divider;       /*!< Specifies the high speed clock divider ratio.
+                               This parameter can be a value from 0 to 127 */
+
+  uint32_t HighThreshold;  /*!< Specifies the high threshold of the DTS sensor */
+
+  uint32_t LowThreshold;   /*!< Specifies the low threshold of the DTS sensor */
+
+} DTS_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_DTS_STATE_RESET       = 0x00UL,     /*!< DTS not yet initialized or disabled */
+  HAL_DTS_STATE_READY       = 0x01UL,     /*!< DTS initialized and ready for use   */
+  HAL_DTS_STATE_BUSY        = 0x02UL,     /*!< DTS is running                      */
+  HAL_DTS_STATE_TIMEOUT     = 0x03UL,     /*!< Timeout state                       */
+  HAL_DTS_STATE_ERROR       = 0x04UL      /*!< Internal Process error              */
+} HAL_DTS_StateTypeDef;
+
+/**
+  * @brief  DTS Handle Structure definition
+  */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+typedef struct __DTS_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+{
+  DTS_TypeDef         *Instance;    /*!< Register base address */
+  DTS_InitTypeDef     Init;         /*!< DTS required parameters */
+  HAL_LockTypeDef     Lock;         /*!< DTS Locking object */
+  __IO HAL_DTS_StateTypeDef  State; /*!< DTS peripheral state  */
+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)
+  void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< DTS Base Msp Init Callback                   */
+  void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts);       /*!< DTS Base Msp DeInit Callback                 */
+  void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< End measure Callback                         */
+  void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< low threshold Callback                       */
+  void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts);        /*!< high threshold Callback                      */
+  void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous end of measure Callback         */
+  void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous low threshold Callback          */
+  void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous high threshold Callback         */
+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */
+} DTS_HandleTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DTS_Exported_Constants DTS Exported Constants
+  * @{
+  */
+
+/** @defgroup DTS_TriggerConfig  DTS Trigger Configuration
+  * @{
+  */
+/* @brief No Hardware trigger detection */
+#define DTS_TRIGGER_HW_NONE   (0UL)
+
+/* @brief External Interrupt Mode with LPTIMER1 trigger detection */
+#define DTS_TRIGGER_LPTIMER1  DTS_CFGR1_TS1_INTRIG_SEL_0
+
+/* @brief External Interrupt Mode with LPTIMER2 trigger detection */
+#define DTS_TRIGGER_LPTIMER2  DTS_CFGR1_TS1_INTRIG_SEL_1
+
+/* @brief External Interrupt Mode with LPTIMER3 trigger detection */
+#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)
+
+/* @brief External Interrupt Mode with EXTI13 trigger detection */
+#define DTS_TRIGGER_EXTI13    DTS_CFGR1_TS1_INTRIG_SEL_2
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Quick_Measurement  DTS Quick Measurement
+  * @{
+  */
+#define DTS_QUICKMEAS_ENABLE    DTS_CFGR1_Q_MEAS_OPT      /*!< Enable the Quick Measure (Measure without calibration) */
+#define DTS_QUICKMEAS_DISABLE   (0x0UL)                   /*!< Disable the Quick Measure (Measure with calibration) */
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Reference_Clock_Selection   DTS Reference Clock Selection
+  * @{
+  */
+#define DTS_REFCLKSEL_LSE   DTS_CFGR1_REFCLK_SEL          /*!< Low speed REF clock (LSE) */
+#define DTS_REFCLKSEL_PCLK (0UL)                          /*!< High speed REF clock (PCLK) */
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Sampling_Time   DTS Sampling Time
+  * @{
+  */
+#define DTS_SMP_TIME_1_CYCLE     DTS_CFGR1_TS1_SMP_TIME_0                                                                                   /*!< 1 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_2_CYCLE     DTS_CFGR1_TS1_SMP_TIME_1                                                                                   /*!< 2 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_3_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1)                                                       /*!< 3 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_4_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_2)                                                                                 /*!< 4 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_5_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2)                                                       /*!< 5 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_6_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)                                                       /*!< 6 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_7_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)                            /*!< 7 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_8_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_3)                                                                                  /*!< 8 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_9_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 9 clock cycle for the sampling time  */
+#define DTS_SMP_TIME_10_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 10 clock cycle for the sampling time */
+#define DTS_SMP_TIME_11_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 11 clock cycle for the sampling time */
+#define DTS_SMP_TIME_12_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 12 clock cycle for the sampling time */
+#define DTS_SMP_TIME_13_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 13 clock cycle for the sampling time */
+#define DTS_SMP_TIME_14_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 14 clock cycle for the sampling time */
+#define DTS_SMP_TIME_15_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */
+/**
+  * @}
+  */
+/** @defgroup DTS_Flag_Definitions DTS Flag Definitions
+  * @{
+  */
+#define DTS_FLAG_TS1_ITE   DTS_SR_TS1_ITEF   /*!< Interrupt flag for end of measure for DTS1 */
+#define DTS_FLAG_TS1_ITL   DTS_SR_TS1_ITLF   /*!< Interrupt flag for low threshold for DTS1  */
+#define DTS_FLAG_TS1_ITH   DTS_SR_TS1_ITHF   /*!< Interrupt flag for high threshold for DTS1 */
+#define DTS_FLAG_TS1_AITE  DTS_SR_TS1_AITEF  /*!< Asynchronous Interrupt flag for end of measure for DTS1 */
+#define DTS_FLAG_TS1_AITL  DTS_SR_TS1_AITLF  /*!< Asynchronous Interrupt flag for low threshold for DTS1  */
+#define DTS_FLAG_TS1_AITH  DTS_SR_TS1_AITHF  /*!< Asynchronous Interrupt flag for high threshold for DTS1 */
+#define DTS_FLAG_TS1_RDY   DTS_SR_TS1_RDY    /*!< Ready flag for DTS1 */
+/**
+  * @}
+  */
+
+/** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions
+  * @{
+  */
+#define DTS_IT_TS1_ITE  DTS_ITENR_TS1_ITEEN   /*!< Enable interrupt flag for end of measure for DTS1 */
+#define DTS_IT_TS1_ITL  DTS_ITENR_TS1_ITLEN   /*!< Enable interrupt flag for low threshold for DTS1  */
+#define DTS_IT_TS1_ITH  DTS_ITENR_TS1_ITHEN   /*!< Enable interrupt flag for high threshold for DTS1 */
+#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN  /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */
+#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN  /*!< Enable asynchronous interrupt flag for low threshold for DTS1  */
+#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN  /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup DTS_Exported_Macros DTS Exported Macros
+  * @{
+  */
+
+/** @brief  Reset DTS handle state
+  * @param  __HANDLE__ DTS handle.
+  * @retval None
+  */
+#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__)    ((__HANDLE__)->State = HAL_DTS_STATE_RESET)
+
+/**
+  * @brief  Enable the specified DTS sensor
+  * @param  __HANDLE__ DTS handle.
+  * @retval None
+  */
+#define __HAL_DTS_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
+
+/**
+  * @brief  Disable the specified DTS sensor
+  * @param  __HANDLE__ DTS handle.
+  * @retval None
+  */
+#define __HAL_DTS_DISABLE(__HANDLE__)    CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)
+
+/**
+  * @brief  Enable the DTS EXTI line in interrupt mode
+  * @retval None
+  */
+#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT()  SET_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
+
+/**
+  * @brief  Disable the DTS EXTI line in interrupt mode
+  * @retval None
+  */
+#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT()  CLEAR_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)
+
+/**
+  * @brief  Enable the DTS EXTI Line in event mode
+  * @retval None
+  */
+#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
+
+/**
+  * @brief  Disable the DTS EXTI Line in event mode
+  * @retval None
+  */
+#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)
+
+/** @brief  Checks whether the specified DTS flag is set or not.
+  * @param  __HANDLE__ specifies the DTS Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
+  *            @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
+  *            @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
+  *            @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
+  *            @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
+  *            @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
+  *            @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1
+  *            @retval The new state of __FLAG__ (SET or RESET).
+  */
+#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__)  \
+        (((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)
+
+
+/** @brief  Clears the specified DTS pending flag.
+  * @param  __HANDLE__ specifies the DTS Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1
+  *            @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1
+  *            @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1
+  *            @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1
+  *            @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1
+  *            @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1
+  * @retval None
+  */
+#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__)  \
+        ((__HANDLE__)->Instance->ICIFR  = (__FLAG__))
+
+
+/** @brief  Enable the specified DTS interrupt.
+  * @param  __HANDLE__ specifies the DTS Handle.
+  * @param  __INTERRUPT__ specifies the DTS interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1
+  *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1
+  *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1
+  *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
+  *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
+  *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
+  * @retval None
+  */
+#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  \
+        SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
+
+
+/** @brief  Disable the specified DTS interrupt.
+  * @param  __HANDLE__ specifies the DTS Handle.
+  * @param  __INTERRUPT__ specifies the DTS interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1
+  *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1
+  *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1
+  *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
+  *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
+  *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
+  * @retval None
+  */
+#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__)  \
+        CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)
+
+
+/** @brief  Check whether the specified DTS interrupt source is enabled or not.
+  * @param __HANDLE__ DTS handle.
+  * @param __INTERRUPT__ DTS interrupt source to check
+  *          This parameter can be one of the following values:
+  *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1
+  *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1
+  *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1
+  *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1
+  *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1
+  *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  \
+        (( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__) \
+        )? SET : RESET)
+
+
+/** @brief  Check whether the specified DTS REFCLK is selected
+  * @param __HANDLE__ DTS handle.
+  * @param __REFCLK__ DTS reference clock to check
+  *          This parameter can be one of the following values:
+  * @arg DTS_REFCLKSEL_LSE:   Low speed REF clock
+  * @arg DTS_REFCLKSEL_PCLK:  High speed REF clock
+  * @retval State of the REF clock tested (SET or RESET)
+  */
+#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__)  ((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)
+
+/** @brief  Get Trigger
+  * @param __HANDLE__ DTS handle.
+  * @retval One of the following trigger
+  *     DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger)
+  *     DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger
+  *     DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger
+  *     DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger
+  *     DTS_TRIGGER_EXTI13  : EXTI13 trigger
+  */
+#define __HAL_DTS_GET_TRIGGER(__HANDLE__)  ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup DTS_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DTS_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);
+HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup DTS_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);
+HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);
+HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);
+HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);
+HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);
+HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts);
+/* Callback in Interrupt mode */
+void              HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);
+void              HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DTS_Private_Constants DTS Private Constants
+  * @{
+  */
+/** @defgroup DTS_ExtiLine DTS EXTI Lines
+  * @{
+  */
+#define DTS_EXTI_LINE_DTS1           (EXTI_IMR3_IM88)  /*!< EXTI line 88 connected to DTS1 output */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DTS_Private_Macros DTS Private Macros
+  * @{
+  */
+
+/** @defgroup DTS_IS_DTS_Definitions  DTS Private macros to check input parameters
+  * @{
+  */
+#define IS_DTS_QUICKMEAS(__SEL__)   (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \
+                                     ((__SEL__) == DTS_QUICKMEAS_ENABLE))
+
+#define IS_DTS_REFCLK(__SEL__)      (((__SEL__) == DTS_REFCLKSEL_LSE) || \
+                                     ((__SEL__) == DTS_REFCLKSEL_PCLK))
+
+#define IS_DTS_TRIGGERINPUT(__INPUT__)  (((__INPUT__) == DTS_TRIGGER_HW_NONE)   || \
+                                         ((__INPUT__) == DTS_TRIGGER_LPTIMER1)  || \
+                                         ((__INPUT__) == DTS_TRIGGER_LPTIMER2)  || \
+                                         ((__INPUT__) == DTS_TRIGGER_LPTIMER3)  || \
+                                         ((__INPUT__) == DTS_TRIGGER_EXTI13))
+
+#define IS_DTS_THRESHOLD(__THRESHOLD__)  ((__THRESHOLD__) <= 0xFFFFUL)
+
+#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL)))
+
+#define IS_DTS_SAMPLINGTIME(__CYCLE__)  (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE)  || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_3_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_4_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_5_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_6_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_7_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_8_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_9_CYCLE)    || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_10_CYCLE)   || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_11_CYCLE)   || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_12_CYCLE)   || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_13_CYCLE)   || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_14_CYCLE)   || \
+                                             ((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DTS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_DTS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth.h

@@ -25,6 +25,7 @@
  extern "C" {
 #endif
 
+#if defined(ETH)
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
@@ -1666,6 +1667,8 @@ uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
   * @}
   */
 
+#endif /* ETH */
+
 #ifdef __cplusplus
 }
 #endif

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_eth_ex.h

@@ -25,6 +25,8 @@
  extern "C" {
 #endif
 
+#if defined(ETH)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
@@ -344,6 +346,8 @@ uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);
   * @}
   */
 
+#endif /* ETH */
+
 #ifdef __cplusplus
 }
 #endif

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_exti.h

@@ -134,16 +134,32 @@ typedef struct
 #define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)
 #define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
 #define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#if !defined(USB2_OTG_FS)
+#define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)
+#else
 #define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
+#endif /* USB2_OTG_FS */
 #define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)
+#if defined(DSI)
 #define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)
+#else
+#define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)
+#endif /* DSI */
 #define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)
 #define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)
 #define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)
 #define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)
 #define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)
+#if !defined(UART9)
 #define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)
+#else
+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)
+#endif /* UART9 */
+#if !defined(USART10)
 #define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)
+#else
+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#endif /* USART10 */
 #define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
 #define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
 #define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)
@@ -165,21 +181,25 @@ typedef struct
 #define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)
 #define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)
 #define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)
+#if defined(ADC3)
 #define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)
+#else
+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)
+#endif /* ADC3 */
+#if defined(SAI4)
 #define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)
-#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
-
+#else
+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)
+#endif /* SAI4 */
 #if defined (DUAL_CORE)
+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)
 #define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)
-#else
-#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
-#endif /* DUAL_CORE */
-
 #define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)
-
-#if defined (DUAL_CORE)
 #define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)
 #else
+#define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)
+#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)
+#define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)
 #define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)
 #endif /* DUAL_CORE */
 
@@ -192,10 +212,21 @@ typedef struct
 #endif /* DUAL_CORE */
 
 #define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)
+#if defined (DUAL_CORE)
 #define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)
+#else
+#define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)
+#endif /* DUAL_CORE */
 #define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)
+#if defined(ETH)
 #define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)
+#else
+#define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)
+#endif /* ETH */
 #define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)
+#if defined(DTS)
+#define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)
+#endif /* DTS */
 
 /**
   * @}
@@ -255,8 +286,16 @@ typedef struct
 #define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */
 #define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */
 #define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/
+#if defined (LPTIM4)
 #define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
-#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
+#if defined (LPTIM5)
+#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#else
+#define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */
+#endif
 /**
   * @}
   */
@@ -339,7 +378,11 @@ typedef struct
 /**
   * @brief  EXTI Line number
   */
+#if defined (EXTI_LINE_88)
+#define EXTI_LINE_NB                        89UL
+#else
 #define EXTI_LINE_NB                        88UL
+#endif /* EXTI_LINE_88 */
 
 /**
   * @}
@@ -390,12 +433,19 @@ typedef struct
                                          ((__PORT__) == EXTI_GPIOK))
 
 #define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)
-
+#if defined (LPTIM4) && defined (LPTIM5)
 #define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \
                                          ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))
+#else
+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \
+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))
+#endif /* LPTIM4 && LPTIM5 */
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash.h

@@ -91,24 +91,28 @@ typedef struct
   * @brief    FLASH Error Code
   * @{
   */
-#define HAL_FLASH_ERROR_NONE         0x00000000U  /*!< No error                              */
-
-#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR   /*!< Write Protection Error         */
-#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR   /*!< Program Sequence Error         */
-#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR  /*!< Strobe Error                   */
-#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR   /*!< Inconsistency Error            */
-#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR    /*!< Operation Error                */
-#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR   /*!< Read Protection Error          */
-#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR   /*!< Read Secured Error             */
-#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR /*!< ECC Single Correction Error    */
-#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR /*!< ECC Double Detection Error     */
-#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR /*!< CRC Read Error                 */
+#define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */
+
+#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */
+#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */
+#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */
+#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */
+#if defined (FLASH_SR_OPERR)
+#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */
+#endif /* FLASH_SR_OPERR */
+#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */
+#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */
+#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */
+#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */
+#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */
 
 #define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */
 #define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */
 #define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */
 #define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */
+#if defined (FLASH_SR_OPERR)
 #define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */
+#endif /* FLASH_SR_OPERR */
 #define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */
 #define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */
 #define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */
@@ -119,7 +123,9 @@ typedef struct
 #define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */
 #define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */
 #define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */
+#if defined (FLASH_SR_OPERR)
 #define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */
+#endif /* FLASH_SR_OPERR */
 #define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */
 #define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */
 #define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */
@@ -134,7 +140,10 @@ typedef struct
 /** @defgroup FLASH_Type_Program FLASH Type Program
   * @{
   */
-#define FLASH_TYPEPROGRAM_FLASHWORD  0x03U        /*!< Program a flash word (256-bit) at a specified address */
+#define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */
+#if defined (FLASH_OPTCR_PG_OTP)
+#define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */
+#endif /* FLASH_OPTCR_PG_OTP */
 /**
   * @}
   */
@@ -144,77 +153,99 @@ typedef struct
   * @{
   */
 #define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */
-#define FLASH_FLAG_WDW                     FLASH_SR_WDW             /*!< Waiting for Data to Write on flag */
-#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Write Waiting in Operation Queue on flag */
-#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC module is working on flag */
+#define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */
+#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */
+#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */
 #define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */
 #define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */
 #define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */
-#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< strobe Error on flag */
+#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */
 #define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */
+#if defined (FLASH_SR_OPERR)
 #define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */
+#endif /* FLASH_SR_OPERR */
 #define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */
 #define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */
 #define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */
 #define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */
-#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC module completes on bank flag */
+#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */
 #define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */
 
 #define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */
-#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Waiting for Data to Write on Bank 1 flag */
-#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Write Waiting in Operation Queue on Bank 1 flag */
-#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC module is working on Bank 1 flag */
+#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */
+#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */
 #define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */
 #define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */
 #define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */
-#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< strobe Error on Bank 1 flag */
+#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */
 #define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */
+#if defined (FLASH_SR_OPERR)
 #define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */
+#endif /* FLASH_SR_OPERR */
 #define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */
 #define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */
 #define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */
 #define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */
-#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC module completes on bank Bank 1 flag */
+#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */
 #define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */
 
+#if defined (FLASH_SR_OPERR)
 #define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
                                            FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
                                            FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \
                                            FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \
-                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1)
+                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \
+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \
+                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \
+                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \
+                                           FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */
+#endif /* FLASH_SR_OPERR */
 
 #define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \
                                            FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \
                                            FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \
-                                           FLASH_FLAG_ALL_ERRORS_BANK1)
+                                           FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */
 
 #define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */
-#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Waiting for Data to Write on Bank 2 flag */
-#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Write Waiting in Operation Queue on Bank 2 flag */
-#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC module is working on Bank 2 flag */
+#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */
+#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */
+#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */
 #define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */
 #define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */
 #define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */
 #define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */
 #define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */
+#if defined (FLASH_SR_OPERR)
 #define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */
+#endif /* FLASH_SR_OPERR */
 #define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */
 #define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */
 #define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */
 #define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */
-#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC module completes on bank Bank 2 flag */
+#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */
 #define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */
 
+#if defined (FLASH_SR_OPERR)
 #define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
                                            FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
                                            FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \
                                            FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \
-                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2)
+                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#else
+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \
+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \
+                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \
+                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \
+                                           FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */
+#endif /* FLASH_SR_OPERR */
 
 #define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \
                                            FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \
                                            FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \
-                                           FLASH_FLAG_ALL_ERRORS_BANK2)
+                                           FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */
 /**
   * @}
   */
@@ -228,7 +259,9 @@ typedef struct
 #define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */
 #define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */
 #define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
 #define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
 #define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */
 #define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */
 #define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */
@@ -236,19 +269,30 @@ typedef struct
 #define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */
 #define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */
 
+#if defined (FLASH_CR_OPERRIE)
 #define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
                                             FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
                                             FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \
                                             FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \
                                             FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \
-                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1)
+                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \
+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \
+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \
+                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \
+                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \
+                                            FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
 
 #define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */
 #define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */
 #define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */
 #define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */
 #define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */
+#if defined (FLASH_CR_OPERRIE)
 #define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */
+#endif /* FLASH_CR_OPERRIE */
 #define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */
 #define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */
 #define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */
@@ -256,16 +300,26 @@ typedef struct
 #define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */
 #define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */
 
+#if defined (FLASH_CR_OPERRIE)
 #define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
                                             FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
                                             FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \
                                             FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \
                                             FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \
-                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2)
+                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#else
+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \
+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \
+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \
+                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \
+                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \
+                                            FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */
+#endif /* FLASH_CR_OPERRIE */
 /**
   * @}
   */
 
+#if defined (FLASH_CR_PSIZE)
 /** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
   * @{
   */
@@ -276,6 +330,7 @@ typedef struct
 /**
   * @}
   */
+#endif /* FLASH_CR_PSIZE */
 
 
 /** @defgroup FLASH_Keys FLASH Keys
@@ -300,6 +355,128 @@ typedef struct
 #define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */
 #define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */
 #define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */
+#define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */
+#define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */
+#define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */
+#define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */
+#define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */
+#define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */
+#define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */
+#define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */
+#define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */
+#define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */
+#define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */
+#define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */
+#define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */
+#define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */
+#define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */
+#define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */
+#define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */
+#define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */
+#define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */
+#define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */
+#define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */
+#define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */
+#define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */
+#define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */
+#define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */
+#define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */
+#define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */
+#define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */
+#define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */
+#define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */
+#define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */
+#define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */
+#define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */
+#define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */
+#define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */
+#define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */
+#define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */
+#define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */
+#define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */
+#define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */
+#define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */
+#define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */
+#define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */
+#define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */
+#define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */
+#define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */
+#define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */
+#define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */
+#define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */
+#define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */
+#define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */
+#define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */
+#define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */
+#define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */
+#define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */
+#define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */
+#define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */
+#define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */
+#define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */
+#define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */
+#define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */
+#define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */
+#define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */
+#define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */
+#define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */
+#define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */
+#define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */
+#define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */
+#define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */
+#define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */
+#define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */
+#define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */
+#define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */
+#define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */
+#define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */
+#define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */
+#define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */
+#define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */
+#define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */
+#define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */
+#define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */
+#define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */
+#define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */
+#define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */
+#define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */
+#define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */
+#define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */
+#define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */
+#define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */
+#define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */
+#define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */
+#define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */
+#define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */
+#define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */
+#define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */
+#define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */
+#define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */
+#define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */
+#define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */
+#define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */
+#define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */
+#define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */
+#define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */
+#define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */
+#define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */
+#define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */
+#define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */
+#define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */
+#define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */
+#define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */
+#define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */
+#define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */
+#define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */
+#define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */
+#define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */
+#define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */
+#define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */
+#define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */
+#define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
 /**
   * @}
   */
@@ -344,8 +521,9 @@ typedef struct
   *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
   *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
   *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
-
-  *   In case of Bank 2, this parameter can be any combination of the following values:  *
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
   *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
   *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
@@ -358,6 +536,7 @@ typedef struct
   *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
   *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
   *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
   * @retval none
   */
 
@@ -386,8 +565,9 @@ typedef struct
   *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source
   *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source
   *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source
-
-  *   In case of Bank 2, this parameter can be any combination of the following values:  *
+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources
+  *
+  *   In case of Bank 2, this parameter can be any combination of the following values:
   *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source
   *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source
   *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source
@@ -400,6 +580,7 @@ typedef struct
   *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source
   *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source
   *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source
+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources
   * @retval none
   */
 
@@ -415,10 +596,10 @@ typedef struct
 /**
   * @brief  Checks whether the specified FLASH flag is set or not.
   * @param  __FLAG__: specifies the FLASH flag to check.
-  *   In case of Bank 1 This parameter can be any combination of the following values :
+  *   In case of Bank 1 This parameter can be one of the following values :
   *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag
-  *     @arg FLASH_FLAG_WBNE_BANK1      : Waiting for Data to Write on Bank 1 flag
-  *     @arg FLASH_FLAG_QW_BANK1       : Write Waiting in Operation Queue on Bank 1 flag
+  *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag
+  *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag
   *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag
   *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
   *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
@@ -433,10 +614,10 @@ typedef struct
   *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
   *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
   *
-  *   In case of Bank 2 This parameter can be any combination of the following values :
+  *   In case of Bank 2 This parameter can be one of the following values :
   *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag
-  *     @arg FLASH_FLAG_WBNE_BANK2      : Waiting for Data to Write on Bank 2 flag
-  *     @arg FLASH_FLAG_QW_BANK2       : Write Waiting in Operation Queue on Bank 2 flag
+  *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag
+  *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag
   *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag
   *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
   *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
@@ -463,33 +644,37 @@ typedef struct
 /**
   * @brief  Clear the specified FLASH flag.
   * @param  __FLAG__: specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag
-  *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag
-  *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag
-  *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag
-  *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag
-  *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag
-  *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag
-  *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag
-  *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag
-  *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag
-  *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag
-  *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag
+  *    In case of Bank 1, this parameter can be any combination of the following values:
+  *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag
+  *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag
+  *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag
+  *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags
+  *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags
   *
-  *   In case of Bank 2 This parameter can be any combination of the following values :
-  *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag
-  *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag
-  *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag
-  *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag
-  *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag
-  *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag
-  *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag
-  *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag
-  *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag
-  *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag
-  *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag
-  *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag
+  *   In case of Bank 2, this parameter can be any combination of the following values :
+  *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag
+  *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag
+  *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag
+  *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag
+  *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag
+  *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag
+  *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag
+  *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag
+  *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag
+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags
+  *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags
   * @retval none
   */
 
@@ -575,36 +760,33 @@ extern FLASH_ProcessTypeDef pFlash;
   * @{
   */
 
-/** @defgroup FLASH_IS_FLASH_Definitions FLASH Definitions
-  * @{
-  */
-#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
-/**
-  * @}
-  */
-/** @defgroup FLASH_IS_BANK_IT_Definitions FLASH BANK IT Definitions
-  * @{
-  */
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \
+                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))
+#else
+#define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)
+#endif /* FLASH_OPTCR_PG_OTP */
 
-#define IS_FLASH_IT_BANK1(IT)              (((IT) & FLASH_IT_ALL_BANK1) == (IT))
+#define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))
 
-#define IS_FLASH_IT_BANK2(IT)              (((IT) & FLASH_IT_ALL_BANK2) == (IT))
+#define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))
 
-/**
-  * @}
-  */
-
-#define IS_FLASH_FLAG_BANK1(FLAG)          (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
+#define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))
 
-#define IS_FLASH_FLAG_BANK2(FLAG)          (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
-
-/** @defgroup FLASH_Address FLASH Address
-  * @{
-  */
+#define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))
 
 #define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))
 #define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))
-#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)  (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
+
+#if defined (FLASH_OPTCR_PG_OTP)
+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))
+#else
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \
+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))
+#endif /* FLASH_OPTCR_PG_OTP */
 
 #define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))
 
@@ -615,9 +797,6 @@ extern FLASH_ProcessTypeDef pFlash;
 #define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \
                                             ((BANK) == FLASH_BANK_2))
 
-/**
-  * @}
-  */
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_flash_ex.h

@@ -69,26 +69,26 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t OptionType;   /*!< Option byte to be configured.
-                              This parameter can be a value of @ref FLASHEx_Option_Type */
+  uint32_t OptionType;     /*!< Option byte to be configured.
+                                This parameter can be a value of @ref FLASHEx_Option_Type */
 
-  uint32_t WRPState;     /*!< Write protection activation or deactivation.
-                              This parameter can be a value of @ref FLASHEx_WRP_State */
+  uint32_t WRPState;       /*!< Write protection activation or deactivation.
+                                This parameter can be a value of @ref FLASHEx_WRP_State */
 
-  uint32_t WRPSector;    /*!< Specifies the sector(s) to be write protected.
-                              The value of this parameter depend on device used within the same series */
+  uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.
+                                The value of this parameter depend on device used within the same series */
 
-  uint32_t RDPLevel;     /*!< Set the read protection level.
-                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
+  uint32_t RDPLevel;       /*!< Set the read protection level.
+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
 
-  uint32_t BORLevel;     /*!< Set the BOR Level.
-                              This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
+  uint32_t BORLevel;       /*!< Set the BOR Level.
+                                This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
 
   uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).
                                 This parameter can be a combination of @ref FLASHEx_OB_USER_Type */
 
-  uint32_t USERConfig;   /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
-                              IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
+  uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /
+                                IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */
 
   uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .
                                 This parameter must be a value of @ref FLASHEx_Banks */
@@ -103,13 +103,13 @@ typedef struct
   uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).
                                 This parameter must be a value between PCROP Start address and end of a bank */
 
-  uint32_t BootConfig;  /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
+  uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1
                                 or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */
 
-  uint32_t BootAddr0;   /*!< Boot Address 0.
+  uint32_t BootAddr0;      /*!< Boot Address 0.
                                 This parameter must be a value between begin and end of a bank */
 
-  uint32_t BootAddr1;   /*!< Boot Address 1.
+  uint32_t BootAddr1;      /*!< Boot Address 1.
                                 This parameter must be a value between begin and end of a bank */
 #if defined(DUAL_CORE)
   uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1
@@ -123,16 +123,21 @@ typedef struct
                                 This parameter must be a value between begin and end of a bank */
 #endif /*DUAL_CORE*/
 
-  uint32_t SecureAreaConfig;  /*!< specifies if the bank secured area shall be erased or not
-                                   when RDP level decreased from Level 1 to Level 0 or during a mass erase.
-                                   This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
+  uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not
+                                     when RDP level decreased from Level 1 to Level 0 or during a mass erase.
+                                     This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */
 
   uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.
                                      This parameter must be a value between begin address and end address of bank1 */
 
-  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address .
+  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.
                                      This parameter must be a value between Secure Area Start address and end address of a bank1 */
 
+#if defined (FLASH_OTPBL_LOCKBL)
+  uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.
+                                This parameter must be a value of @ref FLASHEx_OTP_Blocks */
+#endif /* FLASH_OTPBL_LOCKBL */
+
 } FLASH_OBProgramInitTypeDef;
 
 /**
@@ -140,20 +145,20 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t TypeCRC;          /*!< CRC Selection Type.
-                             This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
+  uint32_t TypeCRC;      /*!< CRC Selection Type.
+                              This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */
 
-  uint32_t BurstSize;       /*!< CRC Burst Size.
-                             This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
+  uint32_t BurstSize;    /*!< CRC Burst Size.
+                              This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */
 
-  uint32_t Bank;             /*!< Select bank where CRC computation is enabled.
-                             This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
+  uint32_t Bank;         /*!< Select bank where CRC computation is enabled.
+                              This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */
 
-  uint32_t Sector;      /*!< Initial FLASH sector from which starts the CRC computation
-                             This parameter must be a value of @ref FLASH_Sectors */
+  uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation
+                              This parameter must be a value of @ref FLASH_Sectors */
 
-  uint32_t NbSectors;   /*!< Number of sectors to be computed.
-                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
+  uint32_t NbSectors;    /*!< Number of sectors to be computed.
+                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/
 
   uint32_t CRCStartAddr; /*!< CRC Start address.
                               This parameter must be a value between begin address and end address of a bank */
@@ -181,6 +186,7 @@ typedef struct
   * @}
   */
 
+#if defined (FLASH_CR_PSIZE)
 /** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
   * @{
   */
@@ -191,6 +197,7 @@ typedef struct
 /**
   * @}
   */
+#endif /* FLASH_CR_PSIZE */
 
 /** @defgroup FLASHEx_WRP_State FLASH WRP State
   * @{
@@ -210,13 +217,16 @@ typedef struct
 #define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */
 #define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */
 #define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 #define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */
 #define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */
 #define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */
-#else /* Single core*/
+#else /* Single core */
 #define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */
 #endif /*DUAL_CORE*/
+#if defined (FLASH_OTPBL_LOCKBL)
+#define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */
+#endif /* FLASH_OTPBL_LOCKBL */
 /**
   * @}
   */
@@ -272,8 +282,8 @@ typedef struct
 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
   * @{
   */
-#define OB_IWDG_STOP_FREEZE      0x00000000U /*!< Freeze IWDG counter in STOP mode */
-#define OB_IWDG_STOP_ACTIVE      FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
+#define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */
+#define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */
 /**
   * @}
   */
@@ -281,8 +291,8 @@ typedef struct
 /** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
   * @{
   */
-#define OB_IWDG_STDBY_FREEZE      0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
-#define OB_IWDG_STDBY_ACTIVE      FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */
+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */
 /**
   * @}
   */
@@ -290,10 +300,10 @@ typedef struct
 /** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
   * @{
   */
-#define OB_BOR_LEVEL0          0x00000000U                /*!< Reset level threshold is set to 1.6V */
-#define OB_BOR_LEVEL1          FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
-#define OB_BOR_LEVEL2          FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
-#define OB_BOR_LEVEL3          (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
+#define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */
+#define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */
+#define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */
+#define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */
 /**
   * @}
   */
@@ -303,13 +313,13 @@ typedef struct
 /** @defgroup FLASHEx_Boot_Address FLASH Boot Address
   * @{
   */
-#define OB_BOOTADDR_ITCM_RAM         0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
-#define OB_BOOTADDR_SYSTEM           0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
-#define OB_BOOTADDR_ITCM_FLASH       0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
-#define OB_BOOTADDR_AXIM_FLASH       0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
-#define OB_BOOTADDR_DTCM_RAM         0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
-#define OB_BOOTADDR_SRAM1            0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
-#define OB_BOOTADDR_SRAM2            0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
+#define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */
+#define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */
+#define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */
+#define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */
+#define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */
+#define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */
+#define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */
 /**
   * @}
   */
@@ -340,9 +350,9 @@ typedef struct
 /** @defgroup FLASHEx_Banks FLASH Banks
   * @{
   */
-#define FLASH_BANK_1          0x01U                         /*!< Bank 1   */
-#define FLASH_BANK_2          0x02U                         /*!< Bank 2   */
-#define FLASH_BANK_BOTH       (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
+#define FLASH_BANK_1             0x01U                         /*!< Bank 1   */
+#define FLASH_BANK_2             0x02U                         /*!< Bank 2   */
+#define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */
 /**
   * @}
   */
@@ -350,10 +360,10 @@ typedef struct
 /** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP
   * @{
   */
-#define OB_PCROP_RDP_NOT_ERASE    0x00000000U     /*!< PCROP area is not erased when the RDP level
-                                                       is decreased from Level 1 to Level 0 or during a mass erase */
-#define OB_PCROP_RDP_ERASE        FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
-                                                       decreased from Level 1 to Level 0 (full mass erase) */
+#define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level
+                                                      is decreased from Level 1 to Level 0 or during a mass erase */
+#define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is
+                                                      decreased from Level 1 to Level 0 (full mass erase) */
 
 /**
   * @}
@@ -362,15 +372,51 @@ typedef struct
 /** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
   * @{
   */
-#define OB_WRP_SECTOR_0       0x00000001U /*!< Write protection of Sector0     */
-#define OB_WRP_SECTOR_1       0x00000002U /*!< Write protection of Sector1     */
-#define OB_WRP_SECTOR_2       0x00000004U /*!< Write protection of Sector2     */
-#define OB_WRP_SECTOR_3       0x00000008U /*!< Write protection of Sector3     */
-#define OB_WRP_SECTOR_4       0x00000010U /*!< Write protection of Sector4     */
-#define OB_WRP_SECTOR_5       0x00000020U /*!< Write protection of Sector5     */
-#define OB_WRP_SECTOR_6       0x00000040U /*!< Write protection of Sector6     */
-#define OB_WRP_SECTOR_7       0x00000080U /*!< Write protection of Sector7     */
-#define OB_WRP_SECTOR_All     0x000000FFU /*!< Write protection of all Sectors */
+#if (FLASH_SECTOR_TOTAL == 128)
+#define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */
+#define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */
+#define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */
+#define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */
+#define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */
+#define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */
+#define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */
+#define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */
+#define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */
+#define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */
+#define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */
+#define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */
+#define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */
+#define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */
+#define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */
+#define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */
+#define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */
+#define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */
+#define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */
+#define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */
+#define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */
+#define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */
+#define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */
+#define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */
+#define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */
+#define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */
+#define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */
+#define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */
+#define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */
+#define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */
+#define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */
+#define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */
+#define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */
+#else
+#define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */
+#define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */
+#define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */
+#define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */
+#define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */
+#define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */
+#define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */
+#define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */
+#define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */
+#endif /* FLASH_SECTOR_TOTAL == 128 */
 /**
   * @}
   */
@@ -387,10 +433,10 @@ typedef struct
 /** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE
   * @{
   */
-#define OB_ST_RAM_SIZE_2KB   0x00000000U               /*!< 2 Kbytes reserved to ST code */
-#define OB_ST_RAM_SIZE_4KB   FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
-#define OB_ST_RAM_SIZE_8KB   FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
-#define OB_ST_RAM_SIZE_16KB  FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */
+#define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */
 /**
   * @}
   */
@@ -414,7 +460,7 @@ typedef struct
 /**
   * @}
   */
-#endif /*DUAL_CORE*/
+#endif /* DUAL_CORE */
 
 /** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW
   * @{
@@ -454,7 +500,7 @@ typedef struct
   * @}
   */
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2
   * @{
   */
@@ -472,7 +518,7 @@ typedef struct
 /**
   * @}
   */
-#endif
+#endif /* DUAL_CORE */
 
 /** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK
   * @{
@@ -486,18 +532,29 @@ typedef struct
 /** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV
   * @{
   */
-#define OB_IOHSLV_DISABLE     0x00000000U         /*!< IOHSLV disabled */
-#define OB_IOHSLV_ENABLE      FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
+#define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */
+#define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */
 /**
   * @}
   */
 
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV
+  * @{
+  */
+#define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */
+#define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */
+/**
+  * @}
+  */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
 /** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION
   * @{
   */
-#define OB_BOOT_ADD0          0x01U       /*!< Select Boot Address 0 */
-#define OB_BOOT_ADD1          0x02U       /*!< Select Boot Address 1 */
-#define OB_BOOT_ADD_BOTH      0x03U       /*!< Select Boot Address 0 and 1 */
+#define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */
+#define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */
+#define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */
 /**
   * @}
   */
@@ -514,7 +571,10 @@ typedef struct
 #define OB_USER_SECURITY          0x0040U /*!< security selection */
 #define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */
 #define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */
-#if defined(DUAL_CORE)
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+#if defined (DUAL_CORE)
 #define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */
 #define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */
 #define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */
@@ -533,7 +593,6 @@ typedef struct
                                                        is decreased from Level 1 to Level 0 or during a mass erase */
 #define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is
                                                        decreased from Level 1 to Level 0 (full mass erase) */
-
 /**
   * @}
   */
@@ -570,6 +629,32 @@ typedef struct
   * @}
   */
 
+#if defined (FLASH_OTPBL_LOCKBL)
+/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks
+  * @{
+  */
+#define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */
+#define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */
+#define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */
+#define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */
+#define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */
+#define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */
+#define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */
+#define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */
+#define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */
+#define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */
+#define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */
+#define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */
+#define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */
+#define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */
+#define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */
+#define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */
+#define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */
+/**
+  * @}
+  */
+#endif /* FLASH_OTPBL_LOCKBL */
+
 /* Exported macro ------------------------------------------------------------*/
 /** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros
   * @{
@@ -585,6 +670,7 @@ typedef struct
   * @}
   */
 
+#if defined (FLASH_CR_PSIZE)
 /**
   * @brief  Set the FLASH Program/Erase parallelism.
   * @param  __PSIZE__ FLASH Program/Erase parallelism
@@ -605,6 +691,7 @@ typedef struct
 #define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \
                               READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \
                               READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))
+#endif /* FLASH_CR_PSIZE */
 
 /**
   * @brief  Set the FLASH Programming Delay.
@@ -661,75 +748,75 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
   * @{
   */
 
-#define IS_FLASH_TYPEERASE(VALUE)    (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
-                                      ((VALUE) == FLASH_TYPEERASE_MASSERASE))
+#define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \
+                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))
 
-#define IS_VOLTAGERANGE(RANGE)    (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
-                                   ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
-                                   ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
-                                   ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+#if defined (FLASH_CR_PSIZE)
+#define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \
+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_4))
+#endif /* FLASH_CR_PSIZE */
 
-#define IS_WRPSTATE(VALUE)    (((VALUE) == OB_WRPSTATE_DISABLE) || \
-                               ((VALUE) == OB_WRPSTATE_ENABLE))
-#if defined(DUAL_CORE)
-#define IS_OPTIONBYTE(VALUE)    (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
+#define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \
+                                          ((VALUE) == OB_WRPSTATE_ENABLE))
+
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))
+#elif defined (DUAL_CORE)
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))
 #else
-#define IS_OPTIONBYTE(VALUE)    (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))
 #endif /*DUAL_CORE*/
 
-#define IS_OB_BOOT_ADDRESS(ADDRESS)     ((ADDRESS) <= 0x8013U)
-
-#define IS_OB_RDP_LEVEL(LEVEL)          (((LEVEL) == OB_RDP_LEVEL_0)   ||\
-                                         ((LEVEL) == OB_RDP_LEVEL_1)   ||\
-                                         ((LEVEL) == OB_RDP_LEVEL_2))
-
-#define IS_OB_WWDG_SOURCE(SOURCE) (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
+#define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)
 
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+#define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\
+                                          ((LEVEL) == OB_RDP_LEVEL_2))
 
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
+#define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))
 
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
+#define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
 
-#define IS_OB_IWDG_STOP_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
+#define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
 
-#define IS_OB_IWDG_STDBY_FREEZE(FREEZE) (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
+#define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
 
-#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
-                                ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
+#define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))
 
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0)  || \
-                                   ((LATENCY) == FLASH_LATENCY_1)  || \
-                                   ((LATENCY) == FLASH_LATENCY_2)  || \
-                                   ((LATENCY) == FLASH_LATENCY_3)  || \
-                                   ((LATENCY) == FLASH_LATENCY_4)  || \
-                                   ((LATENCY) == FLASH_LATENCY_5)  || \
-                                   ((LATENCY) == FLASH_LATENCY_6)  || \
-                                   ((LATENCY) == FLASH_LATENCY_7)  || \
-                                   ((LATENCY) == FLASH_LATENCY_8)  || \
-                                   ((LATENCY) == FLASH_LATENCY_9)  || \
-                                   ((LATENCY) == FLASH_LATENCY_10) || \
-                                   ((LATENCY) == FLASH_LATENCY_11) || \
-                                   ((LATENCY) == FLASH_LATENCY_12) || \
-                                   ((LATENCY) == FLASH_LATENCY_13) || \
-                                   ((LATENCY) == FLASH_LATENCY_14) || \
-                                   ((LATENCY) == FLASH_LATENCY_15))
+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))
 
-#define IS_FLASH_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) || \
-                                   (((ADDRESS) >= FLASH_OTP_BANK1_BASE) && ((ADDRESS) <= FLASH_OTP_BANK1_END)) || \
-                                   (((ADDRESS) >= FLASH_OTP_BANK2_BASE) && ((ADDRESS) <= FLASH_OTP_BANK2_END)))
+#define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \
+                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))
 
-#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
+#define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \
+                                          ((LATENCY) == FLASH_LATENCY_1)  || \
+                                          ((LATENCY) == FLASH_LATENCY_2)  || \
+                                          ((LATENCY) == FLASH_LATENCY_3)  || \
+                                          ((LATENCY) == FLASH_LATENCY_4)  || \
+                                          ((LATENCY) == FLASH_LATENCY_5)  || \
+                                          ((LATENCY) == FLASH_LATENCY_6)  || \
+                                          ((LATENCY) == FLASH_LATENCY_7)  || \
+                                          ((LATENCY) == FLASH_LATENCY_8)  || \
+                                          ((LATENCY) == FLASH_LATENCY_9)  || \
+                                          ((LATENCY) == FLASH_LATENCY_10) || \
+                                          ((LATENCY) == FLASH_LATENCY_11) || \
+                                          ((LATENCY) == FLASH_LATENCY_12) || \
+                                          ((LATENCY) == FLASH_LATENCY_13) || \
+                                          ((LATENCY) == FLASH_LATENCY_14) || \
+                                          ((LATENCY) == FLASH_LATENCY_15))
 
-#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0)   || ((SECTOR) == FLASH_SECTOR_1)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_2)   || ((SECTOR) == FLASH_SECTOR_3)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_4)   || ((SECTOR) == FLASH_SECTOR_5)   ||\
-                                 ((SECTOR) == FLASH_SECTOR_6)   || ((SECTOR) == FLASH_SECTOR_7))
+#define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)
 
-#define IS_OB_WRP_SECTOR(SECTOR)  ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#if (FLASH_SECTOR_TOTAL == 8U)
+#define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))
+#else
+#define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)
+#endif /* FLASH_SECTOR_TOTAL == 8U */
 
-#define IS_OB_PCROP_RDP(CONFIG)         (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
-                                         ((CONFIG) == OB_PCROP_RDP_ERASE))
+#define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \
+                                          ((CONFIG) == OB_PCROP_RDP_ERASE))
 
 #define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \
                                           ((CONFIG) == OB_SECURE_RDP_ERASE))
@@ -738,10 +825,14 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
 
 #define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))
 
+#if defined (FLASH_OPTSR_VDDMMC_HSLV)
+#define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))
+#endif /* FLASH_OPTSR_VDDMMC_HSLV */
+
 #define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 #define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))
-#endif /*DUAL_CORE*/
+#endif /* DUAL_CORE */
 #define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))
 
 #define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))
@@ -755,7 +846,7 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
 
 #define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 #define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))
 
 #define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))
@@ -763,12 +854,12 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
 #define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))
 
 #define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))
-#endif /*DUAL_CORE*/
-#if defined(DUAL_CORE)
+#endif /* DUAL_CORE */
+#if defined (DUAL_CORE)
 #define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))
 #else
 #define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))
-#endif
+#endif /* DUAL_CORE */
 
 #define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \
                                           ((VALUE) == OB_BOOT_ADD1)  || \
@@ -777,6 +868,10 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
 #define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \
                                           ((VALUE) == FLASH_CRC_SECTORS) || \
                                           ((VALUE) == FLASH_CRC_BANK))
+
+#if defined (FLASH_OTPBL_LOCKBL)
+#define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))
+#endif /* FLASH_OTPBL_LOCKBL */
 /**
   * @}
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gfxmmu.h

@@ -0,0 +1,453 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_gfxmmu.h
+  * @author  MCD Application Team
+  * @brief   Header file of GFXMMU HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_GFXMMU_H
+#define STM32H7xx_HAL_GFXMMU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+#if defined(GFXMMU)
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup GFXMMU
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL GFXMMU states definition
+  */
+typedef enum
+{
+  HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */
+  HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */
+}HAL_GFXMMU_StateTypeDef;
+
+/**
+  * @brief  GFXMMU buffers structure definition
+  */
+typedef struct
+{
+  uint32_t Buf0Address; /*!< Physical address of buffer 0. */
+  uint32_t Buf1Address; /*!< Physical address of buffer 1. */
+  uint32_t Buf2Address; /*!< Physical address of buffer 2. */
+  uint32_t Buf3Address; /*!< Physical address of buffer 3. */
+}GFXMMU_BuffersTypeDef;
+
+/**
+  * @brief  GFXMMU cache and pre-fetch structure definition
+  */
+typedef struct
+{
+  FunctionalState Activation;          /*!< Cache and pre-fetch enable/disable.
+                                            @note: All following parameters are usefull only if cache and pre-fetch are enabled. */
+  uint32_t        CacheLock;           /*!< Locking the cache to a buffer.
+                                            This parameter can be a value of @ref GFXMMU_CacheLock. */
+  uint32_t        CacheLockBuffer;     /*!< Buffer on which the cache is locked.
+                                            This parameter can be a value of @ref GFXMMU_CacheLockBuffer.
+                                            @note: Usefull only when lock of the cache is enabled. */
+  uint32_t        CacheForce;          /*!< Forcing the cache regardless MPU attributes.
+                                            This parameter can be a value of @ref GFXMMU_CacheForce.
+                                            @note: Usefull only when lock of the cache is enabled. */
+  uint32_t        OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.
+                                            This parameter can be a value of @ref GFXMMU_OutterBufferability. */
+  uint32_t        OutterCachability;   /*!< Cachability of an access generated by the GFXMMU cache.
+                                            This parameter can be a value of @ref GFXMMU_OutterCachability. */
+  uint32_t        Prefetch;            /*!< Pre-fetch enable/disable.
+                                            This parameter can be a value of @ref GFXMMU_Prefetch. */
+}GFXMMU_CachePrefetchTypeDef;
+
+/**
+  * @brief  GFXMMU interrupts structure definition
+  */
+typedef struct
+{
+  FunctionalState Activation;     /*!< Interrupts enable/disable */
+  uint32_t        UsedInterrupts; /*!< Interrupts used.
+                                       This parameter can be a values combination of @ref GFXMMU_Interrupts.
+                                       @note: Usefull only when interrupts are enabled. */
+}GFXMMU_InterruptsTypeDef;
+
+/**
+  * @brief  GFXMMU init structure definition
+  */
+typedef struct
+{
+  uint32_t                    BlocksPerLine; /*!< Number of blocks of 16 bytes per line.
+                                                  This parameter can be a value of @ref GFXMMU_BlocksPerLine. */
+  uint32_t                    DefaultValue;  /*!< Value returned when virtual memory location not physically mapped. */
+  GFXMMU_BuffersTypeDef       Buffers;       /*!< Physical buffers addresses. */
+  GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */
+  GFXMMU_InterruptsTypeDef    Interrupts;    /*!< Interrupts parameters. */
+}GFXMMU_InitTypeDef;
+
+/**
+  * @brief  GFXMMU handle structure definition
+  */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+typedef struct __GFXMMU_HandleTypeDef
+#else
+typedef struct
+#endif
+{
+  GFXMMU_TypeDef          *Instance; /*!< GFXMMU instance */
+  GFXMMU_InitTypeDef      Init;      /*!< GFXMMU init parameters */
+  HAL_GFXMMU_StateTypeDef State;     /*!< GFXMMU state */
+  __IO uint32_t           ErrorCode; /*!< GFXMMU error code */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+  void (*ErrorCallback)     (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */
+  void (*MspInitCallback)   (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */
+  void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */
+#endif
+}GFXMMU_HandleTypeDef;
+
+/**
+  * @brief  GFXMMU LUT line structure definition
+  */
+typedef struct
+{
+  uint32_t LineNumber;        /*!< LUT line number.
+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */
+  uint32_t LineStatus;        /*!< LUT line enable/disable.
+                                   This parameter can be a value of @ref GFXMMU_LutLineStatus. */
+  uint32_t FirstVisibleBlock; /*!< First visible block on this line.
+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
+  uint32_t LastVisibleBlock;  /*!< Last visible block on this line.
+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 255. */
+  int32_t  LineOffset;        /*!< Offset of block 0 of the current line in physical buffer.
+                                   This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.
+                                   @note: Line offset has to be computed with the following formula:
+                                          LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */
+}GFXMMU_LutLineTypeDef;
+
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  GFXMMU callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_GFXMMU_ERROR_CB_ID     = 0x00U, /*!< GFXMMU error callback ID */
+  HAL_GFXMMU_MSPINIT_CB_ID   = 0x01U, /*!< GFXMMU MSP init callback ID */
+  HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U  /*!< GFXMMU MSP de-init callback ID */
+}HAL_GFXMMU_CallbackIDTypeDef;
+
+/**
+  * @brief  GFXMMU callback pointer definition
+  */
+typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);
+#endif
+
+/**
+  * @}
+  */
+/* End of exported types -----------------------------------------------------*/
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants
+  * @{
+  */
+
+/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line
+  * @{
+  */
+#define GFXMMU_256BLOCKS 0x00000000U     /*!< 256 blocks of 16 bytes per line */
+#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_CacheLock GFXMMU cache lock
+  * @{
+  */
+#define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U  /*!< Cache not locked to a buffer */
+#define GFXMMU_CACHE_LOCK_ENABLE  GFXMMU_CR_CL /*!< Cache locked to a buffer */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer
+  * @{
+  */
+#define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U     /*!< Cache locked to buffer 0 */
+#define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */
+#define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */
+#define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB   /*!< Cache locked to buffer 3 */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_CacheForce GFXMMU cache force
+  * @{
+  */
+#define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U  /*!< Caching not forced */
+#define GFXMMU_CACHE_FORCE_ENABLE  GFXMMU_CR_FC /*!< Caching forced */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_OutterBufferability GFXMMU outter bufferability
+  * @{
+  */
+#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U  /*!< No bufferable */
+#define GFXMMU_OUTTER_BUFFERABILITY_ENABLE  GFXMMU_CR_OB /*!< Bufferable */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_OutterCachability GFXMMU outter cachability
+  * @{
+  */
+#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U  /*!< No cachable */
+#define GFXMMU_OUTTER_CACHABILITY_ENABLE  GFXMMU_CR_OC /*!< Cachable */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch
+  * @{
+  */
+#define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */
+#define GFXMMU_PREFETCH_ENABLE  0x00000000U  /*!< Pre-fetch enable */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Interrupts GFXMMU interrupts
+  * @{
+  */
+#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */
+#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */
+#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */
+#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */
+#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Error_Code GFXMMU Error Code
+  * @{
+  */
+#define GFXMMU_ERROR_NONE             0x00000000U    /*!< No error */
+#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */
+#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */
+#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */
+#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */
+#define GFXMMU_ERROR_AHB_MASTER       GFXMMU_SR_AMEF /*!< AHB master error */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U    /*!< Invalid callback error */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status
+  * @{
+  */
+#define GFXMMU_LUT_LINE_DISABLE 0x00000000U     /*!< LUT line disabled */
+#define GFXMMU_LUT_LINE_ENABLE  GFXMMU_LUTxL_EN /*!< LUT line enabled */
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter
+  * @{
+  */
+#define GFXMMU_CACHE_FORCE_FLUSH      GFXMMU_CCR_FF /*!< Force cache flush */
+#define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported constants -------------------------------------------------*/
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros
+ * @{
+ */
+
+/** @brief  Reset GFXMMU handle state.
+  * @param  __HANDLE__ GFXMMU handle.
+  * @retval None
+  */
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{                                               \
+                                                        (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \
+                                                        (__HANDLE__)->MspInitCallback = NULL;         \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;       \
+                                                      } while(0)
+#else
+#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)
+#endif
+
+/**
+  * @}
+  */
+/* End of exported macros ----------------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions
+  * @{
+  */
+
+/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);
+HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);
+void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);
+void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);
+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)
+/* GFXMMU callbacks register/unregister functions *****************************/
+HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
+                                              HAL_GFXMMU_CallbackIDTypeDef CallbackID,
+                                              pGFXMMU_CallbackTypeDef      pCallback);
+HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,
+                                                HAL_GFXMMU_CallbackIDTypeDef CallbackID);
+#endif
+/**
+  * @}
+  */
+
+/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions
+  * @{
+  */
+/* Operation functions ********************************************************/
+HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,
+                                       uint32_t FirstLine,
+                                       uint32_t LinesNumber,
+                                       uint32_t Address);
+
+HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,
+                                             uint32_t FirstLine,
+                                             uint32_t LinesNumber);
+
+HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine);
+
+HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam);
+
+HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers);
+
+HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,
+                                                 GFXMMU_CachePrefetchTypeDef *CachePrefetch);
+
+void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);
+
+void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);
+/**
+  * @}
+  */
+
+/** @defgroup GFXMMU_Exported_Functions_Group3 State functions
+  * @{
+  */
+/* State function *************************************************************/
+HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu);
+
+uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+/* End of exported functions -------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros
+* @{
+*/
+#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \
+                                          ((VALUE) == GFXMMU_192BLOCKS))
+
+#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)
+
+#define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \
+                                     ((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))
+
+#define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \
+                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \
+                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \
+                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))
+
+#define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \
+                                      ((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))
+
+#define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \
+                                               ((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))
+
+#define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \
+                                             ((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))
+
+#define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \
+                                   ((VALUE) == GFXMMU_PREFETCH_ENABLE))
+
+#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)
+
+#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)
+
+#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))
+
+#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \
+                                          ((VALUE) == GFXMMU_LUT_LINE_ENABLE))
+
+#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)
+
+#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))
+
+#define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \
+                                             ((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \
+                                             ((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))
+/**
+  * @}
+  */
+/* End of private macros -----------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* GFXMMU */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_GFXMMU_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio.h

@@ -173,7 +173,7 @@ typedef enum
   *         This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
 
 /**
   * @brief  Clears the EXTI's line pending flags.
@@ -181,7 +181,7 @@ typedef enum
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
 
 /**
   * @brief  Checks whether the specified EXTI line is asserted or not.
@@ -189,7 +189,7 @@ typedef enum
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI_D1->PR1 & (__EXTI_LINE__))
+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))
 
 /**
   * @brief  Clears the EXTI's line pending bits.
@@ -197,7 +197,7 @@ typedef enum
   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI_D1->PR1 = (__EXTI_LINE__))
+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))
 
 #if defined(DUAL_CORE)
 /**
@@ -206,7 +206,7 @@ typedef enum
   *         This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
-#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
 
 /**
   * @brief  Clears the EXTI's line pending flags.
@@ -214,7 +214,7 @@ typedef enum
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
-#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
 
 /**
   * @brief  Checks whether the specified EXTI line is asserted or not.
@@ -222,7 +222,7 @@ typedef enum
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
-#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI_D2->PR1 & (__EXTI_LINE__))
+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))
 
 /**
   * @brief  Clears the EXTI's line pending bits.
@@ -230,9 +230,9 @@ typedef enum
   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
-#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI_D2->PR1 = (__EXTI_LINE__))
-
+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))
 #endif
+
 /**
   * @brief  Generates a Software interrupt on selected EXTI line.
   * @param  __EXTI_LINE__: specifies the EXTI line to check.

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_gpio_ex.h

@@ -46,14 +46,16 @@ extern "C" {
 /** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection
   * @{
   */
+
 /**
   * @brief   AF 0 selection
   */
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                       */
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping            */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping             */
-#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                        */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                          */
+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */
+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */
+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */
+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */
+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */
+#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
 #define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
 #define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
 #define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */
@@ -62,26 +64,32 @@ extern "C" {
 #define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */
 #define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */
 #endif /* DUAL_CORE */
+#endif /* PWR_CPUCR_PDDS_D2 */
 
 /**
   * @brief   AF 1 selection
   */
-#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
-#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping */
-#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping */
+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */
+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */
+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */
+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */
 #define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */
+#if defined(HRTIM1)
 #define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
 
 /**
   * @brief   AF 2 selection
   */
-#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping */
-#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM2 Alternate Function mapping */
-#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping */
+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */
+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */
+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */
+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */
+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */
+#if defined(HRTIM1)
+#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
 
 /**
   * @brief   AF 3 selection
@@ -89,11 +97,17 @@ extern "C" {
 #define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */
 #define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */
 #define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */
-#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM3 Alternate Function mapping */
 #define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */
 #define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */
 #define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */
 #define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */
+#if defined(OCTOSPIM)
+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#if defined(HRTIM1)
+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */
+#endif /* HRTIM1 */
 
 /**
   * @brief   AF 4 selection
@@ -106,7 +120,13 @@ extern "C" {
 #define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */
 #define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */
 #define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */
-#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping   */
+#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(PSSI)
+#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */
+#endif /* PSSI */
 
 /**
   * @brief   AF 5 selection
@@ -119,17 +139,24 @@ extern "C" {
 #define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */
 #define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */
 
-
 /**
   * @brief   AF 6 selection
   */
-#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping  */
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping  */
-#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping  */
-#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping  */
-#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping  */
-#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping */
-#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping */
+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */
+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */
+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */
+#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */
+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */
+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */
+#endif /* DFSDM2_BASE */
+#if defined(SAI3)
+#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */
+#endif /* SAI3 */
+#if defined(OCTOSPIM)
+#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
 
 /**
   * @brief   AF 7 selection
@@ -148,83 +175,140 @@ extern "C" {
 /**
   * @brief   AF 8 selection
   */
-#define GPIO_AF8_SPI6         ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
-#define GPIO_AF8_SAI2         ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
-#define GPIO_AF8_SAI4         ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
-#define GPIO_AF8_UART4        ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5        ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-#define GPIO_AF8_UART8        ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
-#define GPIO_AF8_SPDIF        ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
-#define GPIO_AF8_LPUART       ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
-#define GPIO_AF8_SDMMC1       ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */
+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */
+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */
+#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */
+#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */
+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */
+#if defined(SAI4)
+#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */
+#endif /* SAI4 */
 
 /**
   * @brief   AF 9 selection
   */
-#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping    */
-#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping    */
-#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping   */
-#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping   */
-#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping   */
+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */
+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */
+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */
+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */
 #define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */
-#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping   */
-#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping   */
-#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping     */
-#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping   */
+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */
+#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */
+#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */
+#if defined(QUADSPI)
+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */
+#endif /* SAI4 */
+#if defined(OCTOSPIM)
+#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */
+#endif /* OCTOSPIM */
 
 /**
   * @brief   AF 10 selection
   */
-#define GPIO_AF10_QUADSPI       ((uint8_t)0xA)  /* QUADSPI Alternate Function mapping */
-#define GPIO_AF10_SAI2          ((uint8_t)0xA)  /* SAI2 Alternate Function mapping */
-#define GPIO_AF10_SAI4          ((uint8_t)0xA)  /* SAI4 Alternate Function mapping */
-#define GPIO_AF10_SDMMC2        ((uint8_t)0xA)  /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF10_OTG2_HS       ((uint8_t)0xA)  /* OTG2_HS Alternate Function mapping */
-#define GPIO_AF10_OTG1_FS       ((uint8_t)0xA)  /* OTG1_FS Alternate Function mapping */
-#define GPIO_AF10_COMP1         ((uint8_t)0xA)  /* COMP1 Alternate Function mapping */
-#define GPIO_AF10_COMP2         ((uint8_t)0xA)  /* COMP2 Alternate Function mapping */
-#define GPIO_AF10_LTDC          ((uint8_t)0xA)  /* LTDC Alternate Function mapping   */
-#define GPIO_AF10_CRS_SYNC      ((uint8_t)0xA)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
-
+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */
+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */
+#if defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */
+#endif /*USB2_OTG_FS*/
+#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */
+#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */
+#if defined(LTDC)
+#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */
+#endif /*LTDC*/
+#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */
+#if defined(QUADSPI)
+#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */
+#endif /* QUADSPI */
+#if defined(SAI4)
+#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */
+#endif /* SAI4 */
+#if !defined(USB2_OTG_FS)
+#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */
+#endif /* !USB2_OTG_FS */
+#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */
+#if defined(OCTOSPIM)
+#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
+#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */
 
 /**
   * @brief   AF 11 selection
   */
-#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping */
-#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping */
-#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)   /* MDIOS Alternate Function mapping   */
-#define GPIO_AF11_OTG1_HS       ((uint8_t)0x0B)  /* OTG1_HS Alternate Function mapping */
-#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping */
-#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping */
-#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM  Alternate Function mapping   */
-#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping */
-#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping */
-#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping  */
+#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */
+#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */
+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */
+#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */
+#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */
+#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */
+#if defined(DFSDM2_BASE)
+#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */
+#endif /* DFSDM2_BASE */
+#if defined(USART10)
+#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */
+#endif /* USART10 */
+#if defined(UART9)
+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */
+#endif /* UART9 */
+#if defined(ETH)
+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */
+#endif /* ETH */
+#if defined(LTDC)
+#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */
+#endif /*LTDC*/
+#if defined(OCTOSPIM)
+#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */
+#endif /* OCTOSPIM */
 
 /**
   * @brief   AF 12 selection
   */
-#define GPIO_AF12_FMC           ((uint8_t)0xC)  /* FMC Alternate Function mapping     */
-#define GPIO_AF12_SDMMC1        ((uint8_t)0xC)  /* SDMMC1 Alternate Function mapping  */
-#define GPIO_AF12_MDIOS         ((uint8_t)0xC)  /* MDIOS Alternate Function mapping   */
-#define GPIO_AF12_OTG2_FS       ((uint8_t)0xC)  /* OTG2_FS Alternate Function mapping   */
-#define GPIO_AF12_COMP1         ((uint8_t)0xC)  /* COMP1 Alternate Function mapping */
-#define GPIO_AF12_COMP2         ((uint8_t)0xC)  /* COMP2 Alternate Function mapping */
-#define GPIO_AF12_LTDC          ((uint8_t)0xC)  /* LTDC Alternate Function mapping   */
+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */
+#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */
+#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */
+#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */
+#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */
+#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */
+#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */
+#if defined(LTDC)
+#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */
+#endif /*LTDC*/
+#if defined(USB2_OTG_FS)
+#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */
+#endif /* USB2_OTG_FS */
 
 /**
   * @brief   AF 13 selection
   */
-#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping */
-#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping */
+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */
 #define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */
 #define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */
-#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping   */
+#if defined(LTDC)
+#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */
+#endif /*LTDC*/
+#if defined(DSI)
+#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */
+#endif /* DSI */
+#if defined(PSSI)
+#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */
+#endif /* PSSI */
+#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */
+#define GPIO_AF13_TIM8          ((uint8_t)0x0D)    /* TIM8 Alternate Function mapping : available on STM32H74xxx/STM32H75xxx  */
 
 /**
   * @brief   AF 14 selection
   */
-#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping   */
+#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */
 #define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */
 
 /**

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash.h

@@ -152,6 +152,8 @@ typedef struct
 
   __IO  uint32_t             ErrorCode;        /*!< HASH Error code */
 
+  __IO  uint32_t             Accumulation;     /*!< HASH multi buffers accumulation flag */
+
 #if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)
   void    (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash);    /*!< HASH input completion callback */
 
@@ -226,11 +228,11 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 /** @defgroup HASH_flags_definition  HASH flags definitions
   * @{
   */
-#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the IP */
-#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                             */
-#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing              */
-#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                       */
-#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data     */
+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */
+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                     */
+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                      */
+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                               */
+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data             */
 
 /**
   * @}
@@ -276,7 +278,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   */
 
 /** @brief  Check whether or not the specified HASH flag is set.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
   *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.
@@ -291,7 +293,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 
 
 /** @brief  Clear the specified HASH flag.
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __FLAG__ specifies the flag to clear.
   *        This parameter can be one of the following values:
   *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.
   *            @arg @ref HASH_FLAG_DCIS Digest calculation complete
@@ -301,7 +303,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 
 
 /** @brief  Enable the specified HASH interrupt.
-  * @param  __INTERRUPT__: specifies the HASH interrupt source to enable.
+  * @param  __INTERRUPT__ specifies the HASH interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
   *            @arg @ref HASH_IT_DCI   Digest calculation complete
@@ -310,7 +312,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 #define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))
 
 /** @brief  Disable the specified HASH interrupt.
-  * @param  __INTERRUPT__: specifies the HASH interrupt source to disable.
+  * @param  __INTERRUPT__ specifies the HASH interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)
   *            @arg @ref HASH_IT_DCI   Digest calculation complete
@@ -319,7 +321,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 #define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))
 
 /** @brief Reset HASH handle state.
-  * @param  __HANDLE__: HASH handle.
+  * @param  __HANDLE__ HASH handle.
   * @retval None
   */
 
@@ -335,7 +337,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 
 
 /** @brief Reset HASH handle status.
-  * @param  __HANDLE__: HASH handle.
+  * @param  __HANDLE__ HASH handle.
   * @retval None
   */
 #define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)
@@ -362,7 +364,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 
 /**
   * @brief Set the number of valid bits in the last word written in data register DIN.
-  * @param  __SIZE__: size in bytes of last data written in Data register.
+  * @param  __SIZE__ size in bytes of last data written in Data register.
   * @retval None
 */
 #define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))
@@ -397,7 +399,7 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
 
 /**
   * @brief Ensure that HASH input data type is valid.
-  * @param __DATATYPE__: HASH input data type.
+  * @param __DATATYPE__ HASH input data type.
   * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
   */
 #define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \
@@ -405,21 +407,11 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
                                         ((__DATATYPE__) == HASH_DATATYPE_8B) || \
                                         ((__DATATYPE__) == HASH_DATATYPE_1B))
 
-
-
-/**
-  * @brief Ensure that input data buffer size is valid for multi-buffer HASH
-  *        processing in polling mode.
-  * @note  This check is valid only for multi-buffer HASH processing in polling mode.
-  * @param __SIZE__: input data buffer size.
-  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
-  */
-#define IS_HASH_POLLING_MULTIBUFFER_SIZE(__SIZE__)  (((__SIZE__) % 4U) == 0U)
 /**
   * @brief Ensure that input data buffer size is valid for multi-buffer HASH
   *        processing in DMA mode.
   * @note  This check is valid only for multi-buffer HASH processing in DMA mode.
-  * @param __SIZE__: input data buffer size.
+  * @param __SIZE__ input data buffer size.
   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
   */
 #define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__)  ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))
@@ -428,21 +420,21 @@ typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer
   * @brief Ensure that input data buffer size is valid for multi-buffer HMAC
   *        processing in DMA mode.
   * @note  This check is valid only for multi-buffer HMAC processing in DMA mode.
-  * @param __HANDLE__: HASH handle.
-  * @param __SIZE__: input data buffer size.
+  * @param __HANDLE__ HASH handle.
+  * @param __SIZE__ input data buffer size.
   * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)
   */
 #define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))
 /**
   * @brief Ensure that handle phase is set to HASH processing.
-  * @param __HANDLE__: HASH handle.
+  * @param __HANDLE__ HASH handle.
   * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)
   */
 #define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)
 
 /**
   * @brief Ensure that handle phase is set to HMAC processing.
-  * @param __HANDLE__: HASH handle.
+  * @param __HANDLE__ HASH handle.
   * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)
   */
 #define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \
@@ -492,8 +484,11 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS
 /* HASH processing using polling  *********************************************/
 HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASH_MD5_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
-HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
+
 
 /**
   * @}
@@ -505,7 +500,11 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *p
 
 /* HASH processing using IT  **************************************************/
 HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
 HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
 void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);
 /**
   * @}
@@ -591,6 +590,7 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);
 /* Private functions */
 HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);
 HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
 HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);
 HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);
 HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hash_ex.h

@@ -52,9 +52,11 @@
   */
 
 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA224_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
-HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);
 
 /**
   * @}
@@ -65,7 +67,11 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accumulate(HASH_HandleTypeDef *hhash, uint8_
   */
 
 HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
 HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);
+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_hrtim.h

@@ -28,6 +28,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
+#if defined(HRTIM1)
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
@@ -961,90 +962,38 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
   * @brief Constants defining the events that can be selected to configure the
   *        set crossbar of a timer output
   */
-#define HRTIM_OUTPUTSET_NONE       0x00000000U             /*!< Reset the output set crossbar */
-#define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)       /*!< Timer period event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its active state */
-#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its active state */
-/* Timer Events mapping for Timer A */
-#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
-/* Timer Events mapping for Timer B */
-#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
-/* Timer Events mapping for Timer C */
-#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
-/* Timer Events mapping for Timer D */
-#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
-/* Timer Events mapping for Timer E */
-#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
-/* Timer Events mapping for Timer F */
-#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
-
-#define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces the output to its active state */
-#define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces the output to its active state */
-#define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces the output to its active state */
+#define HRTIM_OUTPUTSET_NONE       0x00000000U                      /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)                /*!< Timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)               /*!< Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)               /*!< Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)               /*!< Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)               /*!< Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)             /*!< The master timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)            /*!< External event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)            /*!< External event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)            /*!< External event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)            /*!< External event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)            /*!< External event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)            /*!< External event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)            /*!< External event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)            /*!< External event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)            /*!< External event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)           /*!< External event 10 forces the output to its active state */
+#define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)             /*!< Timer register update event forces the output to its active state */
 /**
   * @}
   */
@@ -1054,90 +1003,38 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
   * @brief Constants defining the events that can be selected to configure the
   *        set crossbar of a timer output
   */
-#define HRTIM_OUTPUTRESET_NONE       0x00000000U             /*!< Reset the output reset crossbar */
-#define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)       /*!< Timer period event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)      /*!< Timer compare 1 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)      /*!< Timer compare 2 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)      /*!< Timer compare 3 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)      /*!< Timer compare 4 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)    /*!< The master timer period event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its inactive state */
-/* Timer Events mapping for Timer A */
-#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
-/* Timer Events mapping for Timer B */
-#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
-/* Timer Events mapping for Timer C */
-#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
-/* Timer Events mapping for Timer D */
-#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
-/* Timer Events mapping for Timer E */
-#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
-/* Timer Events mapping for Timer F */
-#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
-
-#define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)   /*!< External event 1 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)   /*!< External event 2 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)   /*!< External event 3 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)   /*!< External event 4 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)   /*!< External event 5 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)   /*!< External event 6 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)   /*!< External event 7 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)   /*!< External event 8 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)   /*!< External event 9 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)  /*!< External event 10 forces the output to its inactive state */
-#define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)    /*!< Timer register update event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)                /*!< Timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)               /*!< Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)               /*!< Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)               /*!< Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)               /*!< Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)             /*!< The master timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)            /*!< External event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)            /*!< External event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)            /*!< External event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)            /*!< External event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)            /*!< External event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)            /*!< External event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)           /*!< External event 10 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)             /*!< Timer register update event forces the output to its inactive state */
 /**
   * @}
   */
@@ -1238,9 +1135,6 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
 /**
   * @}
   */
-/**
-  * @}
-  */
 
 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
   * @{
@@ -2115,7 +2009,7 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
   */
 
   /* Private macros --------------------------------------------------------*/
-/** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
+/** @addtogroup HRTIM_Private_Macros
   * @{
   */
 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
@@ -2830,18 +2724,13 @@ typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!<
      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114)  || \
      ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
 
-#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                       \
-   ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
-    ||                                                                                 \
-    (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
-    ||                                                                                 \
-    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
-    ||                                                                                 \
-    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
-    ||                                                                                 \
-    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
-    ||                                                                                 \
-    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                            \
+    ((((TIMER) == HRTIM_TIMERINDEX_MASTER)  && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
 
 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
     (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
@@ -3761,6 +3650,7 @@ HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *       h
   * @}
   */
 
+#endif /* HRTIM1 */
 
 #ifdef __cplusplus
 }

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s.h

@@ -179,15 +179,17 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
 /** @defgroup I2S_Error I2S Error
   * @{
   */
-#define HAL_I2S_ERROR_NONE               (0x00000000UL)  /*!< No error                    */
-#define HAL_I2S_ERROR_TIMEOUT            (0x00000001UL)  /*!< Timeout error               */
-#define HAL_I2S_ERROR_OVR                (0x00000002UL)  /*!< OVR error                   */
-#define HAL_I2S_ERROR_UDR                (0x00000004UL)  /*!< UDR error                   */
-#define HAL_I2S_ERROR_DMA                (0x00000008UL)  /*!< DMA transfer error          */
-#define HAL_I2S_ERROR_PRESCALER          (0x00000010UL)  /*!< Prescaler Calculation error */
-#define HAL_I2S_ERROR_FRE                (0x00000020UL)  /*!< FRE error                   */
+#define HAL_I2S_ERROR_NONE               (0x00000000UL)  /*!< No error                          */
+#define HAL_I2S_ERROR_TIMEOUT            (0x00000001UL)  /*!< Timeout error                     */
+#define HAL_I2S_ERROR_OVR                (0x00000002UL)  /*!< OVR error                         */
+#define HAL_I2S_ERROR_UDR                (0x00000004UL)  /*!< UDR error                         */
+#define HAL_I2S_ERROR_DMA                (0x00000008UL)  /*!< DMA transfer error                */
+#define HAL_I2S_ERROR_PRESCALER          (0x00000010UL)  /*!< Prescaler Calculation error       */
+#define HAL_I2S_ERROR_FRE                (0x00000020UL)  /*!< FRE error                         */
+#define HAL_I2S_ERROR_NO_OGT             (0x00000040UL)  /*!< No On Going Transfer error        */
+#define HAL_I2S_ERROR_NOT_SUPPORTED      (0x00000080UL)  /*!< Requested operation not supported */
 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)
-#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000040UL)  /*!< Invalid Callback error      */
+#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000100UL)  /*!< Invalid Callback error      */
 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */
 /**
   * @}
@@ -375,7 +377,7 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
   *            @arg I2S_IT_ERR : Error interrupt enable
   * @retval None
   */
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
 
 /** @brief  Disable the specified I2S interrupts.
   * @param  __HANDLE__ specifies the I2S Handle.
@@ -390,7 +392,7 @@ typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to
   *            @arg I2S_IT_ERR : Error interrupt enable
   * @retval None
   */
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->IER,(__INTERRUPT__)))
+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
 
 /** @brief  Check if the specified I2S interrupt source is enabled or disabled.
   * @param  __HANDLE__ specifies the I2S Handle.

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_i2s_ex.h

@@ -16,159 +16,5 @@
   *
   ******************************************************************************
   */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef STM32H7xx_HAL_I2S_EX_H
-#define STM32H7xx_HAL_I2S_EX_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32h7xx_hal_def.h"
-
-/** @addtogroup STM32H7xx_HAL_Driver
-  * @{
-  */
-#if defined(SPI_I2S_FULLDUPLEX_SUPPORT)
-/** @addtogroup I2SEx I2SEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup I2SEx_Exported_Macros I2S Extended Exported Macros
-  * @{
-  */
-
-#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
-
-/** @brief  Enable or disable the specified I2SExt peripheral.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
-#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
-
-/** @brief  Enable or disable the specified I2SExt interrupts.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
-  *        This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_I2SEXT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 |= (__INTERRUPT__))
-#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
-
-/** @brief  Checks if the specified I2SExt interrupt source is enabled or disabled.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2SExt flag is set or not.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__ specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2SExt OVR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{                                                 \
-                                                  __IO uint32_t tmpreg_ovr = 0x00U;                \
-                                                  tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->DR;\
-                                                  tmpreg_ovr = I2SxEXT((__HANDLE__)->Instance)->SR;\
-                                                  UNUSED(tmpreg_ovr);                              \
-                                                  }while(0U)
-/** @brief Clears the I2SExt UDR pending flag.
-  * @param  __HANDLE__ specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{                                                 \
-                                                  __IO uint32_t tmpreg_udr = 0x00U;                \
-                                                  tmpreg_udr = I2SxEXT((__HANDLE__)->Instance)->SR;\
-                                                  UNUSED(tmpreg_udr);                              \
-                                                  }while(0U)
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2SEx_Exported_Functions I2S Extended Exported Functions
-  * @{
-  */
-
-/** @addtogroup I2SEx_Exported_Functions_Group1 I2S Extended IO operation functions
-  * @{
-  */
-
-/* Extended features functions *************************************************/
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
-                                            uint16_t Size, uint32_t Timeout);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
-                                               uint16_t Size);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pTxData, uint16_t *pRxData,
-                                                uint16_t Size);
-/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
-void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private types -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private constants ---------------------------------------------------------*/
-/* Private macros ------------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
-  * @}
-  */
-
-#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* STM32H7xx_HAL_I2S_EX_H */
-
+  /* The I2S Full duplex feature is not supported by this HAL Driver          */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda.h

@@ -305,7 +305,7 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @}
   */
 
-/** @defgroup IRDA_ClockPrescaler Clock Prescaler
+/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler
   * @{
   */
 #define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
@@ -459,8 +459,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   */
 
 /**
- * @}
- */
+  * @}
+  */
 
 /* Exported macros -----------------------------------------------------------*/
 /** @defgroup IRDA_Exported_Macros IRDA Exported Macros
@@ -490,10 +490,10 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @retval None
   */
 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
-    do{                                                                    \
-         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
-         SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
-      } while(0U)
+  do{                                                                    \
+    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \
+  } while(0U)
 
 /** @brief  Clear the specified IRDA pending flag.
   * @param  __HANDLE__ specifies the IRDA Handle.
@@ -608,7 +608,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   *            @arg @ref IRDA_IT_PE Parity Error interrupt
   * @retval The new state of __IT__ (SET or RESET).
   */
-#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)
 
 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the IRDA Handle.
@@ -623,8 +624,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @retval The new state of __IT__ (SET or RESET).
   */
 #define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
-                                                               (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
-                                                               (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
+                                                                (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)
 
 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
   * @param  __HANDLE__ specifies the IRDA Handle.
@@ -662,7 +663,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
-#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART/USART associated to IRDA Handle.
   * @param  __HANDLE__ specifies the IRDA Handle.
@@ -709,7 +711,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @param __MODE__ IRDA communication mode.
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */
-#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\
+                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
 
 /** @brief Ensure that IRDA power mode is valid.
   * @param __MODE__ IRDA power mode.
@@ -723,17 +726,17 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
   */
 #define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
-              ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \
+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))
 
 /** @brief Ensure that IRDA state is valid.
   * @param __STATE__ IRDA state mode.
@@ -778,8 +781,8 @@ typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer
                                               ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \
                                               ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))
 /**
- * @}
- */
+  * @}
+  */
 
 /* Include IRDA HAL Extended module */
 #include "stm32h7xx_hal_irda_ex.h"
@@ -801,7 +804,8 @@ void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
 
 #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)
 /* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID, pIRDA_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,
+                                            pIRDA_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */
 

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_irda_ex.h

@@ -33,6 +33,7 @@ extern "C" {
   */
 
 /** @defgroup IRDAEx IRDAEx
+  * @brief IRDA Extended HAL module driver
   * @{
   */
 
@@ -69,12 +70,13 @@ extern "C" {
   * @param  __CLOCKSOURCE__ output variable.
   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
   */
+#if defined(UART9) && defined(USART10)
 #define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
   do {                                                        \
     if((__HANDLE__)->Instance == USART1)                      \
     {                                                         \
-       switch(__HAL_RCC_GET_USART1_SOURCE())                  \
-       {                                                      \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
         case RCC_USART1CLKSOURCE_D2PCLK2:                     \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
           break;                                              \
@@ -96,12 +98,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if((__HANDLE__)->Instance == USART2)                 \
     {                                                         \
-       switch(__HAL_RCC_GET_USART2_SOURCE())                  \
-       {                                                      \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
         case RCC_USART2CLKSOURCE_D2PCLK1:                     \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
           break;                                              \
@@ -123,12 +125,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if((__HANDLE__)->Instance == USART3)                 \
     {                                                         \
-       switch(__HAL_RCC_GET_USART3_SOURCE())                  \
-       {                                                      \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
         case RCC_USART3CLKSOURCE_D2PCLK1:                     \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
           break;                                              \
@@ -150,12 +152,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if((__HANDLE__)->Instance == UART4)                  \
     {                                                         \
-       switch(__HAL_RCC_GET_UART4_SOURCE())                   \
-       {                                                      \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
         case RCC_UART4CLKSOURCE_D2PCLK1:                      \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
           break;                                              \
@@ -177,12 +179,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if ((__HANDLE__)->Instance == UART5)                 \
     {                                                         \
-       switch(__HAL_RCC_GET_UART5_SOURCE())                   \
-       {                                                      \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
         case RCC_UART5CLKSOURCE_D2PCLK1:                      \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
           break;                                              \
@@ -204,12 +206,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if((__HANDLE__)->Instance == USART6)                 \
     {                                                         \
-       switch(__HAL_RCC_GET_USART6_SOURCE())                  \
-       {                                                      \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
         case RCC_USART6CLKSOURCE_D2PCLK2:                     \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
           break;                                              \
@@ -231,12 +233,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if((__HANDLE__)->Instance == UART7)                  \
     {                                                         \
-       switch(__HAL_RCC_GET_UART7_SOURCE())                   \
-       {                                                      \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
         case RCC_UART7CLKSOURCE_D2PCLK1:                      \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
           break;                                              \
@@ -258,12 +260,12 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
     }                                                         \
     else if((__HANDLE__)->Instance == UART8)                  \
     {                                                         \
-       switch(__HAL_RCC_GET_UART8_SOURCE())                   \
-       {                                                      \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
         case RCC_UART8CLKSOURCE_D2PCLK1:                      \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
           break;                                              \
@@ -285,13 +287,292 @@ extern "C" {
         default:                                              \
           (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
           break;                                              \
-       }                                                      \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART9)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \
+      {                                                       \
+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART10)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \
+      {                                                       \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#else
+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
     }                                                         \
     else                                                      \
     {                                                         \
       (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \
     }                                                         \
   } while(0U)
+#endif /* UART9 && USART10 */
 
 /** @brief  Compute the mask to apply to retrieve the received data
   *         according to the word length and to the parity bits activation.
@@ -300,44 +581,44 @@ extern "C" {
   */
 #define IRDA_MASK_COMPUTATION(__HANDLE__)                             \
   do {                                                                \
-  if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)            \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
-     {                                                                \
+    if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
+      {                                                               \
         (__HANDLE__)->Mask = 0x01FFU ;                                \
-     }                                                                \
-     else                                                             \
-     {                                                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
         (__HANDLE__)->Mask = 0x00FFU ;                                \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
-     {                                                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
+      {                                                               \
         (__HANDLE__)->Mask = 0x00FFU ;                                \
-     }                                                                \
-     else                                                             \
-     {                                                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
         (__HANDLE__)->Mask = 0x007FU ;                                \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)               \
-     {                                                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \
+      {                                                               \
         (__HANDLE__)->Mask = 0x007FU ;                                \
-     }                                                                \
-     else                                                             \
-     {                                                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
         (__HANDLE__)->Mask = 0x003FU ;                                \
-     }                                                                \
-  }                                                                   \
-  else                                                                \
-  {                                                                   \
-    (__HANDLE__)->Mask = 0x0000U;                                     \
-  }                                                                   \
-} while(0U)
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
 
 /** @brief Ensure that IRDA frame length is valid.
   * @param __LENGTH__ IRDA frame length.

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_lptim.h

@@ -4,7 +4,7 @@
   * @author  MCD Application Team
   * @brief   Header file of LPTIM HAL module.
   ******************************************************************************
-    * @attention
+  * @attention
   *
   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
   * All rights reserved.</center></h2>
@@ -13,7 +13,8 @@
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
   *                        opensource.org/licenses/BSD-3-Clause
-  *  ******************************************************************************
+  *
+  ******************************************************************************
   */
 
 /* Define to prevent recursive inclusion -------------------------------------*/
@@ -318,8 +319,8 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
 #define LPTIM_INPUT1SOURCE_COMP2         LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM2 */
 #define LPTIM_INPUT1SOURCE_COMP1_COMP2   (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */
 #define LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U                                   /*!< For LPTIM3 */
-#define LPTIM_INPUT1SOURCE_SAI1_FSA      LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM3 */
-#define LPTIM_INPUT1SOURCE_SAI1_FSB      LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM3 */
+#define LPTIM_INPUT1SOURCE_SAI4_FSA      LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM3 */
+#define LPTIM_INPUT1SOURCE_SAI4_FSB      LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM3 */
 /**
   * @}
   */
@@ -399,6 +400,8 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   * @note   The following sequence is required to solve LPTIM disable HW limitation.
   *         Please check Errata Sheet ES0335 for more details under "MCU may remain
   *         stuck in LPTIM interrupt when entering Stop mode" section.
+  * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
+  *         check for TIMEOUT.
   * @retval None
   */
 #define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)
@@ -435,6 +438,7 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   * @param  __HANDLE__ LPTIM handle
   * @param  __VALUE__ Autoreload value
   * @retval None
+  * @note   The ARR register can only be modified when the LPTIM instance is enabled.
   */
 #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))
 
@@ -443,6 +447,7 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   * @param  __HANDLE__ LPTIM handle
   * @param  __VALUE__ Compare value
   * @retval None
+  * @note   The CMP register can only be modified when the LPTIM instance is enabled.
   */
 #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))
 
@@ -491,6 +496,7 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
   * @retval None.
+  * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
   */
 #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))
 
@@ -507,6 +513,7 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.
   *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.
   * @retval None.
+  * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
   */
 #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))
 
@@ -536,6 +543,10 @@ typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< poin
   * @{
   */
 
+/** @addtogroup LPTIM_Exported_Functions_Group1
+ *  @brief    Initialization and Configuration functions.
+ * @{
+ */
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
 HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@@ -543,7 +554,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
 /* MSP functions  *************************************************************/
 void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
 void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
 
+/** @addtogroup LPTIM_Exported_Functions_Group2
+ *  @brief   Start-Stop operation functions.
+ * @{
+ */
 /* Start/Stop operation functions  *********************************************/
 /* ################################# PWM Mode ################################*/
 /* Blocking mode: Polling */
@@ -592,12 +610,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
 /* Non-Blocking mode: Interrupt */
 HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
 HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
 
+/** @addtogroup LPTIM_Exported_Functions_Group3
+ *  @brief  Read operation functions.
+ * @{
+ */
 /* Reading operation functions ************************************************/
 uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
 uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
 uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
 
+/** @addtogroup LPTIM_Exported_Functions_Group4
+ *  @brief  LPTIM IRQ handler and callback functions.
+ * @{
+ */
 /* LPTIM IRQ functions  *******************************************************/
 void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
 
@@ -615,9 +647,19 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
 HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
 
+/** @addtogroup LPTIM_Group5
+ *  @brief   Peripheral State functions.
+ * @{
+ */
 /* Peripheral State functions  ************************************************/
 HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
+/**
+  * @}
+  */
 
 /**
   * @}
@@ -728,8 +770,8 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
      ||                                                      \
      (((__INSTANCE__) == LPTIM3) &&                          \
      (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) ||  \
-      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSA) ||       \
-      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI1_FSB))))
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) ||       \
+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB))))
 
 #define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \
      ((((__INSTANCE__) == LPTIM1) ||                      \
@@ -745,7 +787,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
 /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
   * @{
   */
-void LPTIM_Disable(LPTIM_HandleTypeDef *lptim);
+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
 /**
   * @}
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdios.h

@@ -29,6 +29,8 @@
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
+#if defined (MDIOS)
+
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */
@@ -597,6 +599,7 @@ HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
   * @}
   */
 
+#endif /* MDIOS */
 
 #ifdef __cplusplus
 }

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mdma.h

@@ -292,20 +292,43 @@ typedef struct __MDMA_HandleTypeDef
 #define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */
 #define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */
 #define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */
+#if defined (LTDC)
 #define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */
+#endif /* LTDC */
+#if defined (JPEG)
 #define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */
 #define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */
 #define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */
 #define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */
 #define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */
+#endif /* JPEG */
+#if defined (OCTOSPI1)
+#define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */
+#endif /* OCTOSPI1 */
+#if defined (QUADSPI)
 #define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */
 #define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */
+#endif /* QUADSPI */
 #define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */
 #define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */
 #define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */
 
+#if defined (DSI)
+#define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */
+#define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */
+#endif /* DSI */
+
 #define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */
 
+#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */
+#define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */
+
+#if defined (OCTOSPI2)
+#define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */
+#define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */
+#endif /* OCTOSPI2 */
+
 #define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */
 
 /**
@@ -316,9 +339,9 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Transfer Trigger Mode
   * @{
   */
-#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer */
-#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer */
-#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */
+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */
+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */
+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */
 #define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */
 
 /**
@@ -343,10 +366,10 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Endianness
   * @{
   */
-#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve    */
-#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte  */
-#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD*/
-#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD */
+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */
+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */
+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */
+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */
 
 /**
   * @}
@@ -356,14 +379,14 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Source increment mode
   * @{
   */
-#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed */
-#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
 #define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
 #define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
 
 /**
@@ -374,14 +397,14 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Destination increment mode
   * @{
   */
-#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed */
-#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)*/
-#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits) */
-#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)*/
+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */
+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */
+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */
+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */
 #define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */
-#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)*/
-#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits) */
-#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)*/
+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */
+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */
+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */
 #define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */
 
 /**
@@ -392,9 +415,9 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Source data size
   * @{
   */
-#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte */
-#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word */
-#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word */
+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */
+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */
+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */
 #define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */
 
 /**
@@ -405,9 +428,9 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA Destination data size
   * @{
   */
-#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte */
-#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word */
-#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word */
+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */
+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */
+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */
 #define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */
 
 /**
@@ -419,11 +442,11 @@ typedef struct __MDMA_HandleTypeDef
   * @{
   */
 #define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size
-                                                                            All data are right aligned, in Little Endien mode. */
-#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default) */
+                                                                            All data are right aligned, in Little Endien mode.                                              */
+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */
 #define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,
                                                                             Note : this mode is allowed only if the Source data size is smaller than Destination data size  */
-#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s) */
+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */
 
 /**
   * @}
@@ -434,12 +457,12 @@ typedef struct __MDMA_HandleTypeDef
   * @{
   */
 #define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */
-#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats */
-#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats */
-#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats */
-#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats */
-#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats */
-#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats */
+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */
+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */
+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */
+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */
+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */
+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */
 #define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */
 
 /**
@@ -451,12 +474,12 @@ typedef struct __MDMA_HandleTypeDef
   * @{
   */
 #define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */
-#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats */
-#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats */
-#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats */
-#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats */
-#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats */
-#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats */
+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */
+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */
+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */
+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */
+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */
+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */
 #define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */
 
 /**
@@ -467,11 +490,11 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA interrupt enable definitions
   * @{
   */
-#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt */
+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */
 #define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */
-#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt */
-#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt */
-#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt */
+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */
+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */
+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */
 
 /**
   * @}
@@ -481,12 +504,12 @@ typedef struct __MDMA_HandleTypeDef
   * @brief    MDMA flag definitions
   * @{
   */
-#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag    */
-#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag */
+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */
+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */
 #define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */
-#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag */
-#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag */
-#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag */
+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */
+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */
+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */
 
 /**
   * @}
@@ -708,18 +731,22 @@ uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
                                            ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))
 
 
-#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )  || \
-                                       ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
-                                       ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
-                                       ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \
+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))
 
-#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )        || \
-                                              ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
-                                              ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
-                                              ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \
+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))
 
 
-#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_END_DATA))
+#if defined (OCTOSPI2)
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))
+#else
+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))
+#endif /* OCTOSPI2 */
 
 #define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \
                                      ((__INC__) == MDMA_SRC_INC_BYTE )      || \
@@ -752,9 +779,9 @@ uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
                                                 ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))
 
 #define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \
-                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
-                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
-                                                 ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \
+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))
 
 
 #define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \
@@ -777,9 +804,9 @@ uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);
                                               ((__BURST__) == MDMA_DEST_BURST_128BEATS))
 
  #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \
-                                         ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
-                                         ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
-                                         ((__MODE__) == MDMA_FULL_TRANSFER))
+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \
+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \
+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))
 
 #define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))
 

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc.h

@@ -92,7 +92,7 @@ typedef struct
 
   uint32_t Class;                        /*!< Specifies the class of the card class           */
 
-  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address            */
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
 
   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
 
@@ -115,29 +115,29 @@ typedef struct
 {
   MMC_TypeDef                  *Instance;        /*!< MMC registers base address           */
 
-  MMC_InitTypeDef              Init;             /*!< MMC required parameters                         */
+  MMC_InitTypeDef              Init;             /*!< MMC required parameters              */
 
-  HAL_LockTypeDef              Lock;             /*!< MMC locking object                              */
+  HAL_LockTypeDef              Lock;             /*!< MMC locking object                   */
 
-  uint8_t                      *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer              */
+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */
 
-  uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                           */
+  uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                 */
 
-  uint8_t                      *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer              */
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer    */
 
-  uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                           */
+  uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                 */
 
-  __IO uint32_t                Context;          /*!< MMC transfer context                           */
+  __IO uint32_t                Context;          /*!< MMC transfer context                 */
 
-  __IO HAL_MMC_StateTypeDef    State;           /*!< MMC card State                                   */
+  __IO HAL_MMC_StateTypeDef    State;            /*!< MMC card State                       */
 
-  __IO uint32_t                ErrorCode;       /*!< MMC Card Error codes                              */
+  __IO uint32_t                ErrorCode;        /*!< MMC Card Error codes                 */
 
-  HAL_MMC_CardInfoTypeDef      MmcCard;           /*!< MMC Card information                 */
+  HAL_MMC_CardInfoTypeDef      MmcCard;          /*!< MMC Card information                 */
 
-  uint32_t                     CSD[4];           /*!< MMC card specific data table         */
+  uint32_t                     CSD[4U];          /*!< MMC card specific data table         */
 
-  uint32_t                     CID[4];           /*!< MMC card identification number table */
+  uint32_t                     CID[4U];          /*!< MMC card identification number table */
 
   uint32_t                     Ext_CSD[128];
 
@@ -283,12 +283,12 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 #define HAL_MMC_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */
 #define HAL_MMC_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */
 #define HAL_MMC_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the
-                                                                                          number of transferred bytes does not match the block length   */
+                                                                                        number of transferred bytes does not match the block length   */
 #define HAL_MMC_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */
 #define HAL_MMC_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */
 #define HAL_MMC_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */
 #define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock
-                                                                                           command or if there was an attempt to access a locked card   */
+                                                                                        command or if there was an attempt to access a locked card    */
 #define HAL_MMC_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */
 #define HAL_MMC_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */
 #define HAL_MMC_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */
@@ -300,7 +300,7 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 #define HAL_MMC_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */
 #define HAL_MMC_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */
 #define HAL_MMC_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out
-                                                                                           of erase sequence command was received                       */
+                                                                                        of erase sequence command was received                        */
 #define HAL_MMC_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */
 #define HAL_MMC_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */
 #define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */
@@ -352,7 +352,7 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
   * @{
   */
 #define  MMC_LOW_CAPACITY_CARD     ((uint32_t)0x00000000U)   /*!< MMC Card Capacity <=2Gbytes   */
-#define  MMC_HIGH_CAPACITY_CARD     ((uint32_t)0x00000001U)  /*!< MMC Card Capacity >2Gbytes and <2Tbytes   */
+#define  MMC_HIGH_CAPACITY_CARD    ((uint32_t)0x00000001U)   /*!< MMC Card Capacity >2Gbytes and <2Tbytes   */
 
 /**
   * @}
@@ -368,7 +368,7 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
  * @{
  */
 /** @brief Reset MMC handle state.
-  * @param  __HANDLE__ : MMC handle.
+  * @param  __HANDLE__ MMC Handle.
   * @retval None
   */
 #if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)
@@ -383,8 +383,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 
 /**
   * @brief  Enable the MMC device interrupt.
-  * @param  __HANDLE__: MMC Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
   *         This parameter can be one or a combination of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -415,8 +415,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 
 /**
   * @brief  Disable the MMC device interrupt.
-  * @param  __HANDLE__: MMC Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -447,8 +447,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 
 /**
   * @brief  Check whether the specified MMC flag is set or not.
-  * @param  __HANDLE__: MMC Handle
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be one of the following values:
   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
@@ -462,8 +462,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
-  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
   *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
   *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
   *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
   *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
@@ -485,8 +485,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 
 /**
   * @brief  Clear the MMC's pending flags.
-  * @param  __HANDLE__: MMC Handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
@@ -514,8 +514,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 
 /**
   * @brief  Check whether the specified MMC interrupt has occurred or not.
-  * @param  __HANDLE__: MMC Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -529,22 +529,16 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
-  *            @arg SDMMC_IT_DPSMACT:    Data path state machine active interrupt
-  *            @arg SDMMC_IT_CPSMACT:    Command path state machine active interrupt
   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:    Transmit FIFO full interrupt
   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:    Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
-  *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
   * @retval The new state of MMC IT (SET or RESET).
   */
@@ -552,8 +546,8 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
 
 /**
   * @brief  Clear the MMC's interrupt pending bits.
-  * @param  __HANDLE__: MMC Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __HANDLE__ MMC Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -567,13 +561,16 @@ typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);
   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
   *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt
   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
-  *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
   * @retval None
   */
@@ -639,6 +636,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca
   * @{
   */
 HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);
 /**
   * @}
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_mmc_ex.h

@@ -75,10 +75,10 @@ HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, ui
 HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);
 HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
 
-void HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback(MMC_HandleTypeDef *hmmc);
-void HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMCEx_Write_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nand.h

@@ -6,7 +6,8 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the
@@ -211,7 +212,6 @@ void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
   */
 
 /* IO operation functions  ****************************************************/
-
 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 
 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
@@ -264,6 +264,7 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 /**
   * @}
   */
+
 /* Private types -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /* Private constants ---------------------------------------------------------*/
@@ -315,6 +316,11 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 
+/**
+  * @brief  NAND memory Column address computation.
+  * @param  __HANDLE__ NAND handle.
+  * @retval NAND Raw address value
+  */
 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 
 /**
@@ -332,7 +338,7 @@ uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
   * @param  __ADDRESS__ NAND memory address.
   * @retval NAND Column address cycling value.
   */
-#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
+#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */
 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 
 /**

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_nor.h

@@ -6,7 +6,8 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the
@@ -28,7 +29,6 @@ extern "C" {
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_ll_fmc.h"
 
-
 /** @addtogroup STM32H7xx_HAL_Driver
   * @{
   */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_opamp.h

@@ -81,7 +81,6 @@ typedef struct
                                              UserTrimming is either factory or user trimming.*/
 
   uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS) in Normal Mode
-
                                              i.e. when UserTrimming is OPAMP_TRIMMING_USER.
                                              This parameter must be a number between Min_Data = 0 and Max_Data = 31.
                                              16 is typical default value */
@@ -129,7 +128,7 @@ typedef struct __OPAMP_HandleTypeDef
 typedef struct
 #endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */
 {
-  OPAMP_TypeDef                 *Instance;                    /*!< OPAMP instance's registers base address   */
+  OPAMP_TypeDef                 *Instance;                    /*!< OPAMP instance's registers base address */
   OPAMP_InitTypeDef              Init;                         /*!< OPAMP required parameters */
   HAL_StatusTypeDef              Status;                       /*!< OPAMP peripheral status   */
   HAL_LockTypeDef                Lock;                         /*!< Locking object          */
@@ -157,9 +156,9 @@ typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;
   */
 typedef enum
 {
-  HAL_OPAMP_MSP_INIT_CB_ID                     = 0x01U,  /*!< OPAMP MspInit Callback ID           */
-  HAL_OPAMP_MSP_DEINIT_CB_ID                   = 0x02U,  /*!< OPAMP MspDeInit Callback ID         */
-  HAL_OPAMP_ALL_CB_ID                          = 0x03U   /*!< OPAMP All ID                        */
+  HAL_OPAMP_MSPINIT_CB_ID                     = 0x01U,  /*!< OPAMP MspInit Callback ID           */
+  HAL_OPAMP_MSPDEINIT_CB_ID                   = 0x02U,  /*!< OPAMP MspDeInit Callback ID         */
+  HAL_OPAMP_ALL_CB_ID                         = 0x03U   /*!< OPAMP All ID                        */
 }HAL_OPAMP_CallbackIDTypeDef;
 
 /**
@@ -191,6 +190,9 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
 
 #define OPAMP_NONINVERTINGINPUT_IO0         0x00000000U                /*!< OPAMP non-inverting input connected to dedicated IO pin */
 #define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL_0          /*!< OPAMP non-inverting input connected internally to DAC channel */
+#if defined(DAC2)
+#define OPAMP_NONINVERTINGINPUT_DAC2_CH     OPAMP_CSR_VPSEL_1         /*!< Only OPAMP2 non-inverting input connected internally to DAC2 channel */
+#endif /* DAC2 */
 
 /**
   * @}
@@ -332,9 +334,14 @@ typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);
 #define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \
                                                     ((INPUT) == OPAMP_INVERTINGINPUT_IO1))
 
-
+#if defined(DAC2)
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH) || \
+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC2_CH))
+#else
 #define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \
                                             ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))
+#endif /* DAC2 */
 
 #define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \
                                       ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_otfdec.h

@@ -0,0 +1,444 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_otfdec.h
+  * @author  MCD Application Team
+  * @brief   Header file of OTFDEC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H7xx_HAL_OTFDEC_H
+#define __STM32H7xx_HAL_OTFDEC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(OTFDEC1)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup OTFDEC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup OTFDEC_Exported_Types OTFDEC Exported Types
+  * @{
+  */
+
+/** @defgroup OTFDEC_Exported_Types_Group1 OTFDEC region configuration definitions
+  * @{
+  */
+
+/**
+  * @brief OTFDEC region configuration structure definition
+  */
+typedef struct
+{
+  uint32_t          Nonce[2];        /*!< OTFDEC region nonce */
+
+  uint32_t          StartAddress;    /*!< OTFDEC region start address */
+
+  uint32_t          EndAddress;      /*!< OTFDEC region end address */
+
+  uint16_t          Version;         /*!< OTFDEC region firmware version */
+
+}OTFDEC_RegionConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/** @defgroup OTFDEC_Exported_Types_Group2 OTFDEC Peripheral handle definitions
+  * @{
+  */
+
+/**
+  * @brief OTFDEC states structure definition
+  */
+typedef enum
+{
+  HAL_OTFDEC_STATE_RESET             = 0x00U,  /*!< OTFDEC not yet initialized or disabled */
+  HAL_OTFDEC_STATE_READY             = 0x01U,  /*!< OTFDEC initialized and ready for use   */
+  HAL_OTFDEC_STATE_BUSY              = 0x02U,  /*!< OTFDEC internal processing is ongoing  */
+}HAL_OTFDEC_StateTypeDef;
+
+/**
+  * @brief OTFDEC handle structure definition
+  */
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+typedef struct __OTFDEC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+{
+  OTFDEC_TypeDef             *Instance;  /*!< OTFDEC registers base address */
+
+  HAL_OTFDEC_StateTypeDef    State;      /*!< OTFDEC state */
+
+  HAL_LockTypeDef            Lock;       /*!< OTFDEC locking object */
+
+  __IO uint32_t              ErrorCode;  /*!< OTFDEC error code */
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+  void (* ErrorCallback)(struct __OTFDEC_HandleTypeDef *hotfdec);     /*!< OTFDEC error callback */
+
+  void (* MspInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec);   /*!< OTFDEC Msp Init callback */
+
+  void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+}OTFDEC_HandleTypeDef;
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL OTFDEC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_OTFDEC_ERROR_CB_ID       = 0x00U,  /*!< OTFDEC error callback ID      */
+  HAL_OTFDEC_MSPINIT_CB_ID     = 0x01U,  /*!< OTFDEC Msp DeInit callback ID */
+  HAL_OTFDEC_MSPDEINIT_CB_ID   = 0x02U   /*!< OTFDEC Msp DeInit callback ID */
+} HAL_OTFDEC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL OTFDEC Callback pointer definition
+  */
+typedef  void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< pointer to a OTFDEC callback function */
+
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup OTFDEC_Exported_Constants OTFDEC Exported Constants
+  * @{
+  */
+
+/** @defgroup OTFDEC_Interrupts    OTFDEC Interrupts
+  * @{
+  */
+#define OTFDEC_SEC_ERROR_INT     (OTFDEC_IER_SEIE                                  )  /*!< OTFDEC security error interrupt                  */
+#define OTFDEC_EXE_ERROR_INT     (               OTFDEC_IER_XONEIE                 )  /*!< OTFDEC execution error interrupt                 */
+#define OTFDEC_KEY_ERROR_INT     (                                  OTFDEC_IER_KEIE)  /*!< OTFDEC key error interrupt                       */
+#define OTFDEC_SEC_EXE_ERROR_INT (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE                )  /*!< OTFDEC security and execution errors interrupts  */
+#define OTFDEC_SEC_KEY_ERROR_INT (OTFDEC_IER_SEIE|                  OTFDEC_IER_KEIE)  /*!< OTFDEC security and key errors interrupts        */
+#define OTFDEC_EXE_KEY_ERROR_INT (                OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE)  /*!< OTFDEC execution and key errors interrupts       */
+#define OTFDEC_ALL_INT           (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE)  /*!< OTFDEC all interrupts                            */
+/**
+  * @}
+  */
+
+/** @defgroup OTFDEC_Region_Enable   OTFDEC Region Enable
+  * @{
+  */
+#define OTFDEC_REG_CONFIGR_REG_DISABLE   0x00000000U                /*!< OTFDEC region encryption or on-the-fly decryption disable */
+#define OTFDEC_REG_CONFIGR_REG_ENABLE    OTFDEC_REG_CONFIGR_REG_EN  /*!< OTFDEC region encryption or on-the-fly decryption enable  */
+/**
+  * @}
+  */
+
+/** @defgroup OTFDEC_Region_Configuration_Lock    OTFDEC Region Configuration Lock
+  * @{
+  */
+#define OTFDEC_REG_CONFIGR_LOCK_DISABLE   0x00000000U                     /*!< OTFDEC region configuration lock disable */
+#define OTFDEC_REG_CONFIGR_LOCK_ENABLE    OTFDEC_REG_CONFIGR_CONFIGLOCK   /*!< OTFDEC region configuration lock enable  */
+/**
+  * @}
+  */
+
+/** @defgroup OTFDEC_Region_Operating_Mode    OTFDEC Region Operating Mode
+  * @{
+  */
+#define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY              0x00000000U                /*!< Only instruction accesses are decrypted                                   */
+#define OTFDEC_REG_MODE_DATA_ACCESSES_ONLY                     OTFDEC_REG_CONFIGR_MODE_0  /*!< Only data accesses are decrypted                                          */
+#define OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES           OTFDEC_REG_CONFIGR_MODE_1  /*!< All read accesses are decrypted                                           */
+#define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER  OTFDEC_REG_CONFIGR_MODE    /*!< Only instruction accesses are decrypted with proprietary cipher activated */
+/**
+  * @}
+  */
+
+/** @defgroup OTFDEC_Error_Definition   OTFDEC Error Definition
+  * @{
+  */
+#define  HAL_OTFDEC_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                         */
+#define  HAL_OTFDEC_SECURITY_ERROR         ((uint32_t)0x00000001U)    /*!< Security error                   */
+#define  HAL_OTFDEC_EXECUTE_ERROR          ((uint32_t)0x00000002U)    /*!< Execute-only Execute-Never error */
+#define  HAL_OTFDEC_KEY_ERROR              ((uint32_t)0x00000004U)    /*!< Key error                        */
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+#define HAL_OTFDEC_ERROR_INVALID_CALLBACK  ((uint32_t)0x00000008U)   /*!< Invalid Callback error            */
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup OTFDEC_Regions_Index   OTFDEC Regions Index
+  * @{
+  */
+#define  OTFDEC_REGION1            ((uint32_t)0x00000000U)    /*!< OTFDEC region 1 */
+#define  OTFDEC_REGION2            ((uint32_t)0x00000001U)    /*!< OTFDEC region 2 */
+#define  OTFDEC_REGION3            ((uint32_t)0x00000002U)    /*!< OTFDEC region 3 */
+#define  OTFDEC_REGION4            ((uint32_t)0x00000003U)    /*!< OTFDEC region 4 */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup OTFDEC_Exported_Macros OTFDEC Exported Macros
+  * @{
+  */
+
+/** @brief  Reset OTFDEC handle state.
+  * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+  *         the configuration information for OTFDEC module
+  * @retval None
+  */
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+#define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__)                            \
+  do{                                                                          \
+    (__HANDLE__)->State = HAL_OTFDEC_STATE_RESET;                              \
+    (__HANDLE__)->MspInitCallback = NULL;                                      \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
+  } while(0)
+#else
+#define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__)                            \
+  ((__HANDLE__)->State = HAL_OTFDEC_STATE_RESET)
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+
+/**
+  * @brief  Enable OTFDEC peripheral interrupts combination
+  * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+  *         the configuration information for OTFDEC module
+  * @param  __INTERRUPT__ mask on enabled interrupts
+  *          This parameter can be one of the following values:
+  *            @arg @ref OTFDEC_SEC_ERROR_INT        OTFDEC security error interrupt
+  *            @arg @ref OTFDEC_EXE_ERROR_INT        OTFDEC execution error interrupt
+  *            @arg @ref OTFDEC_KEY_ERROR_INT        OTFDEC key error interrupt
+  *            @arg @ref OTFDEC_SEC_EXE_ERROR_INT    OTFDEC security and execution errors interrupts
+  *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts
+  *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts
+  *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts
+  * @retval None
+  */
+#define __HAL_OTFDEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
+
+/**
+  * @brief  Disable OTFDEC peripheral interrupts combination
+  * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains
+  *         the configuration information for OTFDEC module
+  * @param  __INTERRUPT__ mask on disabled interrupts
+  *          This parameter can be one of the following values:
+  *            @arg @ref OTFDEC_SEC_ERROR_INT        OTFDEC security error interrupt
+  *            @arg @ref OTFDEC_EXE_ERROR_INT        OTFDEC execution error interrupt
+  *            @arg @ref OTFDEC_KEY_ERROR_INT        OTFDEC key error interrupt
+  *            @arg @ref OTFDEC_SEC_EXE_ERROR_INT    OTFDEC security and execution errors interrupts
+  *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts
+  *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts
+  *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts
+  * @retval None
+  */
+#define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup OTFDEC_Exported_Functions OTFDEC Exported Functions
+  * @{
+  */
+
+/** @addtogroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec);
+HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec);
+void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec);
+void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec);
+
+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,
+                                           pOTFDEC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+
+/** @addtogroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management
+  * @{
+  */
+void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec);
+void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec);
+/**
+  * @}
+  */
+
+/** @addtogroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);
+HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);
+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);
+uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);
+HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+/**
+  * @}
+  */
+
+/** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions
+  * @{
+  */
+HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec);
+uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);
+HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Types OTFDEC Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Variables OTFDEC Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Constants OTFDEC Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Macros OTFDEC Private Macros
+  * @{
+  */
+
+/**
+  * @brief Verify the OTFDEC peripheral interrupts parameter.
+  * @param __INT__ OTFDEC peripheral set of interrupts parameter
+  * @retval SET (__INT__ is valid) or RESET (__INT__ is invalid)
+  */
+#define IS_OTFDEC_INTERRUPTS(__INT__) (((__INT__) == OTFDEC_SEC_ERROR_INT)     || \
+                                       ((__INT__) == OTFDEC_EXE_ERROR_INT)     || \
+                                       ((__INT__) == OTFDEC_KEY_ERROR_INT)     || \
+                                       ((__INT__) == OTFDEC_SEC_EXE_ERROR_INT) || \
+                                       ((__INT__) == OTFDEC_SEC_KEY_ERROR_INT) || \
+                                       ((__INT__) == OTFDEC_EXE_KEY_ERROR_INT) || \
+                                       ((__INT__) == OTFDEC_ALL_INT)  )
+
+/**
+  * @brief Verify the OTFDEC region configuration lock parameter.
+  * @param __LOCK__ OTFDEC region lock parameter.
+  * @retval SET (__LOCK__ is valid) or RESET (__LOCK__ is invalid)
+  */
+#define IS_OTFDEC_REGION_CONFIG_LOCK(__LOCK__) (((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_DISABLE) || \
+                                                ((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)  )
+
+/**
+  * @brief Verify the OTFDEC region operating mode.
+  * @param __MODE__ OTFDEC region operating mode parameter.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY)    || \
+                                                   ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY)           || \
+                                                   ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \
+                                                   ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))
+
+/**
+  * @brief Verify the OTFDEC region index.
+  * @param __INDEX__ OTFDEC region index
+  * @retval SET (__INDEX__ is valid) or RESET (__INDEX__ is invalid)
+  */
+#define IS_OTFDEC_REGIONINDEX(__INDEX__) (((__INDEX__) == OTFDEC_REGION1)     || \
+                                          ((__INDEX__) == OTFDEC_REGION2)     || \
+                                          ((__INDEX__) == OTFDEC_REGION3)     || \
+                                          ((__INDEX__) == OTFDEC_REGION4)  )
+
+/**
+  * @brief Verify the OTFDEC configuration attributes.
+  * @param __ATTRIBUTE__ OTFDEC region index
+  * @retval SET (__ATTRIBUTE__ is valid) or RESET (__ATTRIBUTE__ is invalid)
+  */
+#define IS_OTFDEC_ATTRIBUTE(__ATTRIBUTE__) (((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_PRIV)   || \
+                                            ((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_NPRIV)  )
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup OTFDEC_Private_Functions OTFDEC Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/**
+  * @}
+  */
+#endif /* OTFDEC1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H7xx_HAL_OTFDEC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pssi.h

@@ -0,0 +1,489 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_pssi.h
+  * @author  MCD Application Team
+  * @brief   Header file of PSSI HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_PSSI_H
+#define STM32H7xx_HAL_PSSI_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+#if defined(PSSI)
+/** @addtogroup PSSI PSSI
+  * @brief PSSI HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Types PSSI Exported Types
+  * @{
+  */
+
+
+/**
+  * @brief PSSI Init structure definition
+  */
+typedef struct
+{
+  uint32_t  DataWidth;          /* !< Configures the parallel bus width 8 lines or 16 lines */
+  uint32_t  BusWidth;           /* !< Configures the parallel bus width 8 lines or 16 lines */
+  uint32_t  ControlSignal;      /* !< Configures Data enable and Data ready */
+  uint32_t  ClockPolarity;      /* !< Configures the PSSI Input Clock polarity */
+  uint32_t  DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */
+  uint32_t  ReadyPolarity;      /* !< Configures the PSSI Ready polarity */
+
+} PSSI_InitTypeDef;
+
+
+/**
+  * @brief  HAL PSSI State structures definition
+  */
+typedef enum
+{
+  HAL_PSSI_STATE_RESET   = 0x00U, /* !< PSSI not yet initialized or disabled     */
+  HAL_PSSI_STATE_READY   = 0x01U, /* !< Peripheral initialized and ready for use */
+  HAL_PSSI_STATE_BUSY    = 0x02U, /* !< An internal process is ongoing           */
+  HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing              */
+  HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing               */
+  HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state                            */
+  HAL_PSSI_STATE_ERROR   = 0x06U, /* !< PSSI state error                         */
+  HAL_PSSI_STATE_ABORT   = 0x07U, /* !< PSSI process is aborted                  */
+
+} HAL_PSSI_StateTypeDef;
+
+/**
+  * @brief  PSSI handle Structure definition
+  */
+typedef struct __PSSI_HandleTypeDef
+{
+  PSSI_TypeDef         *Instance;    /*!< PSSI register base address.    */
+  PSSI_InitTypeDef      Init;        /*!< PSSI Initialization Structure. */
+  uint32_t             *pBuffPtr;    /*!< PSSI Data buffer.              */
+  uint32_t              XferCount;   /*!< PSSI transfer count            */
+  uint32_t              XferSize;    /*!< PSSI  transfer size            */
+  DMA_HandleTypeDef    *hdmatx;      /*!< PSSI Tx DMA Handle parameters  */
+  DMA_HandleTypeDef    *hdmarx;      /*!< PSSI Rx DMA Handle parameters  */
+
+  void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
+  void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */
+  void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi);     /*!< PSSI transfer complete callback. */
+  void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback.    */
+
+  void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi);   /*!< PSSI Msp Init callback.          */
+  void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback.        */
+
+  HAL_LockTypeDef             Lock;                               /*!< PSSI lock.                       */
+  __IO HAL_PSSI_StateTypeDef State;                               /*!< PSSI transfer state.             */
+  __IO uint32_t               ErrorCode;                          /*!< PSSI error code.                 */
+
+} PSSI_HandleTypeDef;
+
+
+/**
+  * @brief  HAL PSSI Callback pointer definition
+  */
+typedef  void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi);  /*!< Pointer to a PSSI common callback function */
+
+/**
+  * @}
+  */
+/**
+  * @brief  HAL PSSI Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID  */
+  HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID  */
+  HAL_PSSI_ERROR_CB_ID       = 0x03U, /*!< PSSI Error callback ID                  */
+  HAL_PSSI_ABORT_CB_ID       = 0x04U, /*!< PSSI Abort callback ID                  */
+
+  HAL_PSSI_MSPINIT_CB_ID     = 0x05U, /*!< PSSI Msp Init callback ID               */
+  HAL_PSSI_MSPDEINIT_CB_ID   = 0x06U  /*!< PSSI Msp DeInit callback ID             */
+
+} HAL_PSSI_CallbackIDTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Constants PSSI Exported Constants
+  * @{
+  */
+
+/** @defgroup PSSI_Error_Code PSSI Error Code
+  * @{
+  */
+#define HAL_PSSI_ERROR_NONE             0x00000000U /*!< No error                */
+#define HAL_PSSI_ERROR_NOT_SUPPORTED    0x00000001U /*!< Not supported operation */
+#define HAL_PSSI_ERROR_UNDER_RUN        0x00000002U /*!< FIFO Under-run error    */
+#define HAL_PSSI_ERROR_OVER_RUN         0x00000004U /*!< FIFO Over-run  error    */
+#define HAL_PSSI_ERROR_DMA              0x00000008U /*!< Dma     error           */
+#define HAL_PSSI_ERROR_TIMEOUT          0x00000010U /*!< Timeout error           */
+#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error  */
+
+
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_DATA_WIDTH PSSI Data Width
+  * @{
+  */
+
+#define HAL_PSSI_8BITS                  0x00000000U   /*!<  8 Bits  */
+#define HAL_PSSI_16BITS                 0x00000001U   /*!< 16 Bits  */
+#define HAL_PSSI_32BITS                 0x00000002U   /*!< 32 Bits  */
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_BUS_WIDTH PSSI Bus Width
+  * @{
+  */
+
+#define HAL_PSSI_8LINES                 0x00000000U   /*!< 8 data lines  */
+#define HAL_PSSI_16LINES                PSSI_CR_EDM   /*!< 16 data lines */
+/**
+  * @}
+  */
+/** @defgroup PSSI_MODE PSSI mode
+  * @{
+  */
+#define HAL_PSSI_UNIDIRECTIONAL         0x00000000U /*!< Uni-directional mode */
+#define HAL_PSSI_BIDIRECTIONAL          0x00000001U /*!< Bi-directional mode  */
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_ControlSignal Configuration
+  * @{
+  */
+#define HAL_PSSI_DE_RDY_DISABLE           (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */
+#define HAL_PSSI_RDY_ENABLE               (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */
+#define HAL_PSSI_DE_ENABLE                (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */
+#define HAL_PSSI_DE_RDY_ALT_ENABLE        (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */
+#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE     (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */
+#define HAL_PSSI_RDY_MAP_ENABLE           (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */
+#define HAL_PSSI_DE_MAP_ENABLE            (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */
+#define HAL_PSSI_MAP_DE_BIDIR_ENABLE      (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */
+
+/**
+  * @}
+  */
+
+
+/** @defgroup PSSI_Data_Enable_Polarity Data Enable Polarity
+  * @{
+  */
+#define HAL_PSSI_DEPOL_ACTIVE_LOW         0x0U            /*!< Active Low */
+#define HAL_PSSI_DEPOL_ACTIVE_HIGH        PSSI_CR_DEPOL   /*!< Active High */
+/**
+  * @}
+  */
+/** @defgroup PSSI_Reday_Polarity Reday Polarity
+  * @{
+  */
+#define HAL_PSSI_RDYPOL_ACTIVE_LOW        0x0U            /*!< Active Low */
+#define HAL_PSSI_RDYPOL_ACTIVE_HIGH       PSSI_CR_RDYPOL  /*!< Active High */
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_Clock_Polarity Clock Polarity
+  * @{
+  */
+#define HAL_PSSI_FALLING_EDGE             0x0U            /*!< Fallling Edge */
+#define HAL_PSSI_RISING_EDGE              0x1U            /*!< Rising Edge */
+
+
+/**
+  * @}
+  */
+
+
+/** @defgroup PSSI_DEFINITION PSSI definitions
+  * @{
+  */
+
+#define PSSI_MAX_NBYTE_SIZE         0x10000U         /* 64 KB */
+#define PSSI_TIMEOUT_TRANSMIT       0x0000FFFFU      /*!< Timeout Value   */
+
+#define PSSI_CR_OUTEN_INPUT         0x00000000U      /*!< Input Mode      */
+#define PSSI_CR_OUTEN_OUTPUT        PSSI_CR_OUTEN    /*!< Output Mode     */
+
+#define PSSI_CR_DMA_ENABLE          PSSI_CR_DMAEN    /*!< DMA Mode Enable */
+#define PSSI_CR_DMA_DISABLE         (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */
+
+#define PSSI_CR_16BITS              PSSI_CR_EDM      /*!< 16 Lines Mode   */
+#define PSSI_CR_8BITS               (~PSSI_CR_EDM)   /*!< 8 Lines Mode    */
+
+#define PSSI_FLAG_RTT1B             PSSI_SR_RTT1B    /*!< 1 Byte Fifo Flag*/
+#define PSSI_FLAG_RTT4B             PSSI_SR_RTT4B    /*!< 4 Bytes Fifo Flag*/
+/**
+  * @}
+  */
+
+/** @defgroup PSSI_Interrupts PSSI Interrupts
+  * @{
+  */
+
+#define PSSI_FLAG_OVR_RIS            PSSI_RIS_OVR_RIS     /*!< Overrun, Underrun errors flag */
+#define PSSI_FLAG_MASK               PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */
+#define PSSI_FLAG_OVR_MIS            PSSI_MIS_OVR_MIS     /*!< Overrun, Underrun masked errors flag */
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+/* Exported macros ------------------------------------------------------------*/
+/** @defgroup PSSI_Exported_Macros PSSI Exported Macros
+  * @{
+  */
+
+/** @brief Reset PSSI handle state
+  * @param  __HANDLE__ specifies the PSSI handle.
+  * @retval None
+  */
+
+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \
+                                                      (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\
+                                                      (__HANDLE__)->MspInitCallback = NULL;       \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \
+                                                     }while(0)
+
+
+/**
+  * @brief  Enable the PSSI.
+  * @param  __HANDLE__ PSSI handle
+  * @retval None.
+  */
+#define HAL_PSSI_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)
+/**
+  * @brief  Disable the PSSI.
+  * @param  __HANDLE__ PSSI handle
+  * @retval None.
+  */
+#define HAL_PSSI_DISABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))
+
+/* PSSI pripheral STATUS */
+/**
+  * @brief  Get the PSSI pending flags.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __FLAG__ flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_RTT1B:  FIFO is ready to transfer one byte
+  *            @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes
+  * @retval The state of FLAG.
+  */
+
+#define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
+
+
+
+/* Interrupt & Flag management */
+/**
+  * @brief  Get the PSSI pending flags.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __FLAG__ flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
+  * @retval The state of FLAG.
+  */
+#define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))
+
+/**
+  * @brief  Clear the PSSI pending flags.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __FLAG__ specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag
+  * @retval None
+  */
+#define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/**
+  * @brief  Enable the specified PSSI interrupts.
+  * @param  __HANDLE__ PSSI handle
+  * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_FLAG_OVR_RIS: Configuration error mask
+  * @retval None
+  */
+#define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
+
+/**
+  * @brief  Disable the specified PSSI interrupts.
+  * @param  __HANDLE__ PSSI handle
+  * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg PSSI_IT_OVR_IE: Configuration error mask
+  * @retval None
+  */
+#define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))
+
+/**
+  * @brief  Check whether the specified PSSI interrupt source is enabled or not.
+  * @param  __HANDLE__ PSSI handle
+  * @param  __INTERRUPT__ specifies the PSSI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask
+  * @retval The state of INTERRUPT source.
+  */
+#define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
+
+/**
+  * @brief  Check whether the PSSI Control signal is valid.
+  * @param  __CONTROL__ Control signals configuration
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE        ) || \
+                                             ((__CONTROL__) == HAL_PSSI_RDY_ENABLE            ) || \
+                                             ((__CONTROL__) == HAL_PSSI_DE_ENABLE             ) || \
+                                             ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE     ) || \
+                                             ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE  ) || \
+                                             ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE        ) || \
+                                             ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE         ) || \
+                                             ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE   ))
+/**
+  * @brief  Check whether the PSSI Bus Width is valid.
+  * @param  __BUSWIDTH__ PSSI Bush width
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES    ) || \
+                                        ((__BUSWIDTH__) == HAL_PSSI_16LINES   ))
+
+/**
+  * @brief  Check whether the PSSI Clock Polarity is valid.
+  * @param  __CLOCKPOL__ PSSI Clock Polarity
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE   ) || \
+                                              ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE    ))
+/**
+  * @brief  Check whether the PSSI Data Enable Polarity is valid.
+  * @param  __DEPOL__ PSSI DE Polarity
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW    ) || \
+                                        ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH   ))
+/**
+  * @brief  Check whether the PSSI Ready Polarity is valid.
+  * @param  __RDYPOL__ PSSI RDY Polarity
+  * @retval Valid or not.
+  */
+
+#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW   ) || \
+                                         ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup PSSI_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *******************************/
+HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);
+HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);
+void              HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);
+void              HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);
+/* Callbacks Register/UnRegister functions  ***********************************/
+
+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *******************************************************/
+HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);
+HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group3
+  * @{
+  */
+void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);
+void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);
+/**
+  * @}
+  */
+
+/** @addtogroup PSSI_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State functions ***************************************************/
+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);
+uint32_t              HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+
+
+/* Private macros ------------------------------------------------------------*/
+
+
+/**
+  * @}
+  */
+#endif /* PSSI */
+
+/**
+  * @}
+  */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32H7xx_HAL_PSSI_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr.h

@@ -23,7 +23,7 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif
+#endif /* __cplusplus */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
@@ -47,11 +47,15 @@
   */
 typedef struct
 {
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode             */
+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This
+                                    parameter can be a value of @ref
+                                    PWR_PVD_detection_level.
+                     */
+
+  uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD
+                                event. This parameter can be a value of @ref
+                                PWR_PVD_Mode.
+                     */
 }PWR_PVDTypeDef;
 
 /**
@@ -66,14 +70,22 @@ typedef struct
 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
   * @{
   */
-#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector level 0 selection : 1V95        */
-#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector level 1 selection : 2V1         */
-#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector level 2 selection : 2V25        */
-#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector level 3 selection : 2V4         */
-#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector level 4 selection : 2V55        */
-#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector level 5 selection : 2V7         */
-#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector level 6 selection : 2V85        */
-#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage (Compare internally to VREFINT) */
+#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector
+                                               level 0 selection : 1V95       */
+#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector
+                                               level 1 selection : 2V1        */
+#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector
+                                               level 2 selection : 2V25       */
+#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector
+                                               level 3 selection : 2V4        */
+#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector
+                                               level 4 selection : 2V55       */
+#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector
+                                               level 5 selection : 2V7        */
+#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector
+                                               level 6 selection : 2V85       */
+#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage
+                                               (Compare internally to VREF)   */
 /**
   * @}
   */
@@ -81,13 +93,13 @@ typedef struct
 /** @defgroup PWR_PVD_Mode PWR PVD Mode
   * @{
   */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000U)   /*!< Basic mode is used                                                 */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
+#define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */
+#define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */
+#define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */
+#define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */
+#define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */
+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */
 /**
   * @}
   */
@@ -95,7 +107,7 @@ typedef struct
 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
   * @{
   */
-#define PWR_MAINREGULATOR_ON      ((uint32_t)0x00000000U)
+#define PWR_MAINREGULATOR_ON      (0U)
 #define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS
 /**
   * @}
@@ -104,8 +116,8 @@ typedef struct
 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
   * @{
   */
-#define PWR_SLEEPENTRY_WFI  ((uint8_t)0x01U)
-#define PWR_SLEEPENTRY_WFE  ((uint8_t)0x02U)
+#define PWR_SLEEPENTRY_WFI  (0x01U)
+#define PWR_SLEEPENTRY_WFE  (0x02U)
 /**
   * @}
   */
@@ -113,8 +125,8 @@ typedef struct
 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
   * @{
   */
-#define PWR_STOPENTRY_WFI  ((uint8_t)0x01U)
-#define PWR_STOPENTRY_WFE  ((uint8_t)0x02U)
+#define PWR_STOPENTRY_WFI  (0x01U)
+#define PWR_STOPENTRY_WFE  (0x02U)
 /**
   * @}
   */
@@ -122,10 +134,17 @@ typedef struct
 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
   * @{
   */
-#define PWR_REGULATOR_VOLTAGE_SCALE0  ((uint32_t)0x00000000)
+#if defined(PWR_SRDCR_VOS)
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)
+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)
+#define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)
+#else
+#define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)
 #define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)
 #define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)
 #define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)
+#endif /* PWR_SRDCR_VOS */
 /**
   * @}
   */
@@ -133,29 +152,48 @@ typedef struct
 /** @defgroup PWR_Flag PWR Flag
   * @{
   */
-#define PWR_FLAG_STOP       ((uint8_t)0x01U)
-#define PWR_FLAG_SB_D1      ((uint8_t)0x02U)
-#define PWR_FLAG_SB_D2      ((uint8_t)0x03U)
-#define PWR_FLAG_SB         ((uint8_t)0x04U)
-#if defined(DUAL_CORE)
-#define PWR_FLAG_CPU_HOLD   ((uint8_t)0x05U)
-#define PWR_FLAG_CPU2_HOLD  ((uint8_t)0x06U)
-#define PWR_FLAG2_STOP      ((uint8_t)0x07U)
-#define PWR_FLAG2_SB_D1     ((uint8_t)0x08U)
-#define PWR_FLAG2_SB_D2     ((uint8_t)0x09U)
-#define PWR_FLAG2_SB        ((uint8_t)0x0AU)
-#endif /*DUAL_CORE*/
-#define PWR_FLAG_PVDO       ((uint8_t)0x0BU)
-#define PWR_FLAG_AVDO       ((uint8_t)0x0CU)
-#define PWR_FLAG_ACTVOSRDY  ((uint8_t)0x0DU)
-#define PWR_FLAG_ACTVOS     ((uint8_t)0x0EU)
-#define PWR_FLAG_BRR        ((uint8_t)0x0FU)
-#define PWR_FLAG_VOSRDY     ((uint8_t)0x10U)
-#if defined(SMPS)
-#define PWR_FLAG_SMPSEXTRDY ((uint8_t)0x11U)
+/* PWR CPU flag */
+#define PWR_FLAG_STOP       (0x01U)
+#if defined (PWR_CPUCR_SBF_D2)
+#define PWR_FLAG_SB_D1      (0x02U)
+#define PWR_FLAG_SB_D2      (0x03U)
+#endif /* defined (PWR_CPUCR_SBF_D2) */
+#define PWR_FLAG_SB         (0x04U)
+#if defined (DUAL_CORE)
+#define PWR_FLAG_CPU_HOLD   (0x05U)
+#define PWR_FLAG_CPU2_HOLD  (0x06U)
+#define PWR_FLAG2_STOP      (0x07U)
+#define PWR_FLAG2_SB_D1     (0x08U)
+#define PWR_FLAG2_SB_D2     (0x09U)
+#define PWR_FLAG2_SB        (0x0AU)
+#endif /* defined (DUAL_CORE) */
+#define PWR_FLAG_PVDO       (0x0BU)
+#define PWR_FLAG_AVDO       (0x0CU)
+#define PWR_FLAG_ACTVOSRDY  (0x0DU)
+#define PWR_FLAG_ACTVOS     (0x0EU)
+#define PWR_FLAG_BRR        (0x0FU)
+#define PWR_FLAG_VOSRDY     (0x10U)
+#if defined (SMPS)
+#define PWR_FLAG_SMPSEXTRDY (0x11U)
 #else
-#define PWR_FLAG_SCUEN      ((uint8_t)0x11U)
-#endif /* SMPS */
+#define PWR_FLAG_SCUEN      (0x11U)
+#endif /* defined (SMPS) */
+#if defined (PWR_CSR1_MMCVDO)
+#define PWR_FLAG_MMCVDO     (0x12U)
+#endif /* defined (PWR_CSR1_MMCVDO) */
+#define PWR_FLAG_USB33RDY   (0x13U)
+#define PWR_FLAG_TEMPH      (0x14U)
+#define PWR_FLAG_TEMPL      (0x15U)
+#define PWR_FLAG_VBATH      (0x16U)
+#define PWR_FLAG_VBATL      (0x17U)
+
+/* PWR Wake up flag */
+#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1
+#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2
+#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3
+#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4
+#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5
+#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6
 /**
   * @}
   */
@@ -163,7 +201,7 @@ typedef struct
 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask
   * @{
   */
-#define  PWR_EWUP_MASK  ((uint32_t)0x0FFF3F3FU)
+#define  PWR_EWUP_MASK  (0x0FFF3F3FU)
 /**
   * @}
   */
@@ -176,141 +214,254 @@ typedef struct
   * @{
   */
 
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
+/** @brief  Configure the main internal regulator output voltage.
+  * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a
+  *                         trade-off between performance and power consumption
+  *                         when the device does not operate at the maximum
+  *                         frequency (refer to the datasheet for more details).
   *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0: Regulator voltage output Scale 0 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode
-  * @note  PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when Vcore is supplied from LDO.
-  *        the SYSCFG Clock must be enabled before selecting PWR_REGULATOR_VOLTAGE_SCALE0
-  *        using macro   __HAL_RCC_SYSCFG_CLK_ENABLE().
-  *        Transition to PWR_REGULATOR_VOLTAGE_SCALE0 is only possible when the system is already in
-  *        PWR_REGULATOR_VOLTAGE_SCALE1.
-  *        transition from PWR_REGULATOR_VOLTAGE_SCALE0 is only possible to PWR_REGULATOR_VOLTAGE_SCALE1
-  *        then once in PWR_REGULATOR_VOLTAGE_SCALE1 it is possible to switch to another voltage scale.
-  *        After each regulator voltage setting, wait on PWR_FLAG_VOSRDY to be set using macro __HAL_PWR_GET_FLAG
-  *        To enter low power mode , and if current regulator voltage is PWR_REGULATOR_VOLTAGE_SCALE0 then first
-  *        switch to PWR_REGULATOR_VOLTAGE_SCALE1 before entering low power mode.
-  *
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)  \
-do { \
-    __IO uint32_t tmpreg = 0x00; \
-    if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \
-    { \
-      MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \
-      /* Delay after setting the voltage scaling */  \
-      tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
-      MODIFY_REG(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN, SYSCFG_PWRCR_ODEN); \
-      /* Delay after setting the syscfg boost setting */  \
-      tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
-    } \
-    else \
-    { \
-      CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
-      /* Delay after setting the syscfg boost setting */  \
-      tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \
-      MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \
-      tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \
-    } \
-    UNUSED(tmpreg); \
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output
+  *                                                Scale 0 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output
+  *                                                Scale 1 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output
+  *                                                Scale 2 mode.
+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output
+  *                                                Scale 3 mode.
+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,
+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied
+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through
+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale
+  *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().
+  *         Transition to Voltage Scale 0 is only possible when the system is
+  *         already in Voltage Scale 1.
+  *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1
+  *         then once in Voltage Scale 1 it is possible to switch to another
+  *         voltage scale.
+  *         After each regulator voltage setting, wait on VOSRDY flag to be set
+  *         using macro __HAL_PWR_GET_FLAG().
+  *         To enter low power mode , and if current regulator voltage is
+  *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering
+  *         low power mode.
+  * @retval None.
+  */
+#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \
+      /* Delay after setting the voltage scaling */                            \
+      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \
+      UNUSED(tmpreg);                                                          \
 } while(0)
+#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */
+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \
+do {                                                                           \
+      __IO uint32_t tmpreg = 0x00;                                             \
+      /* Check the voltage scaling to be configured */                         \
+      if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \
+      {                                                                        \
+        /* Configure the Voltage Scaling 1 */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+        /* Enable the PWR overdrive */                                         \
+        SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+      }                                                                        \
+      else                                                                     \
+      {                                                                        \
+        /* Disable the PWR overdrive */                                        \
+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \
+        /* Delay after setting the syscfg boost setting */                     \
+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \
+        /* Configure the Voltage Scaling x */                                  \
+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \
+        /* Delay after setting the voltage scaling */                          \
+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \
+      }                                                                        \
+      UNUSED(tmpreg);                                                          \
+} while(0)
+#endif /* PWR_SRDCR_VOS */
 
-#if defined(DUAL_CORE)
-/** @brief  Check PWR PVD/AVD and VOSflags are set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
-  *                  by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the AVDE bit is set.
-  *            @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
-  *                 scaling output selection is ready.
-  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
-  *                 scaling output selection is ready.
-  *            @arg PWR_FLAG_SMPSEXTRDY: SMPS External supply ready flag.
-  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
-  *                  when the device wakes up from Standby mode or by a system reset
-  *                  or power reset.
-  *            @arg PWR_FLAG_SB: StandBy flag
-  *            @arg PWR_FLAG_STOP: STOP flag
-  *            @arg PWR_FLAG_SB_D1: StandBy D1 flag
-  *            @arg PWR_FLAG_SB_D2: StandBy D2 flag
-  *            @arg PWR_FLAG_CPU1_HOLD: CPU1 system wake up with hold
-  *            @arg PWR_FLAG_CPU2_HOLD: CPU2 system wake up with hold
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
-((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
-((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
-((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
-((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
-((__FLAG__) == PWR_FLAG_SMPSEXTRDY)?((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) : \
-((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
-((__FLAG__) == PWR_FLAG_CPU_HOLD)?((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) : \
-((__FLAG__) == PWR_FLAG_CPU2_HOLD)?((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) : \
-((__FLAG__) == PWR_FLAG_SB)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
-((__FLAG__) == PWR_FLAG2_SB)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) : \
-((__FLAG__) == PWR_FLAG_STOP)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
-((__FLAG__) == PWR_FLAG2_STOP)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) : \
-((__FLAG__) == PWR_FLAG_SB_D1)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
-((__FLAG__) == PWR_FLAG2_SB_D1)?(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) : \
-((__FLAG__) == PWR_FLAG_SB_D2)?(READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) : \
-(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2))
-#else
-/** @brief  Check PWR PVD/AVD and VOSflags are set or not.
-  * @param  __FLAG__: specifies the flag to check.
+/** @brief  Check PWR flags are set or not.
+  * @param  __FLAG__ : Specifies the flag to check.
   *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode.
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_AVDO: AVD Output. This flag is valid only if AVD is enabled
-  *                  by the HAL_PWREx_EnableAVD() function. The AVD is stopped by Standby mode.
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the AVDE bit is set.
-  *            @arg PWR_FLAG_ACTVOSRDY: This flag indicates that the Regulator voltage
-  *                 scaling output selection is ready.
-  *            @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
-  *                 scaling output selection is ready.
-  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
-  *                  when the device wakes up from Standby mode or by a system reset
-  *                  or power reset.
-  *            @arg PWR_FLAG_SB: StandBy flag
-  *            @arg PWR_FLAG_STOP: STOP flag
-  *            @arg PWR_FLAG_SB_D1: StandBy D1 flag
-  *            @arg PWR_FLAG_SB_D2: StandBy D2 flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ( \
-((__FLAG__) == PWR_FLAG_PVDO)?((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) : \
-((__FLAG__) == PWR_FLAG_AVDO)?((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) : \
-((__FLAG__) == PWR_FLAG_ACTVOSRDY)?((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) : \
-((__FLAG__) == PWR_FLAG_VOSRDY)?((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) : \
-((__FLAG__) == PWR_FLAG_SCUEN)?((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) : \
-((__FLAG__) == PWR_FLAG_BRR)?((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) : \
-((__FLAG__) == PWR_FLAG_SB)?((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) : \
-((__FLAG__) == PWR_FLAG_STOP)?((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) : \
-((__FLAG__) == PWR_FLAG_SB_D1)?((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) : \
-((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2))
-#endif /*DUAL_CORE*/
-
-
-#if defined(DUAL_CORE)
-/** @brief  Clear PWR flags.
-  * @param  __FLAG__: specifies the flag to clear.
+  *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD
+  *                                 is enabled by the HAL_PWR_EnablePVD()
+  *                                 function.
+  *                                 The PVD is stopped by STANDBY mode. For this
+  *                                 reason, this bit is equal to 0 after STANDBY
+  *                                 or reset until the PVDE bit is set.
+  *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD
+  *                                 is enabled by the HAL_PWREx_EnableAVD()
+  *                                 function. The AVD is stopped by STANDBY mode.
+  *                                 For this reason, this bit is equal to 0
+  *                                 after STANDBY or reset until the AVDE bit
+  *                                 is set.
+  *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator
+  *                                      voltage scaling output selection is
+  *                                      ready.
+  *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
+  *                                reset when the device wakes up from STANDBY
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator
+  *                                   voltage scaling output selection is ready.
+  *                                mode or by a system reset or power-on reset.
+  *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply
+  *                                     from regulator is ready.
+  *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature
+  *                                  equal or above high threshold level.
+  *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature
+  *                                  equal or below low threshold level.
+  *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal
+  *                                  or above high threshold level.
+  *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal
+  *                                  or below low threshold level.
+  *            @arg PWR_FLAG_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG_SB : This flag indicates that the system entered in
+  *                               STANDBY mode.
+  *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain
+  *                                  entered in STANDBY mode.
+  *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered
+  *                                 in STOP mode.
+  *            @arg PWR_FLAG2_SB : This flag indicates that the system entered
+  *                                in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain
+  *                                   entered in STANDBY mode.
+  *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes
+  *                                     up with hold.
+  *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes
+  *                                      up with hold.
+  *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS
+  *                                       External supply is sready.
+  *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply
+  *                                  configuration update is enabled.
+  *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is
+  *                                   above or equal to 1.2 V.
+  * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,
+  *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,
+  *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags
+  *         are used for all H7 family lines.
+  *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,
+  *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7
+  *         dual core lines.
+  *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7
+  *         family except STM32H7Axxx and STM32H7Bxxx lines.
+  *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and
+  *         STM32H7Bxxx lines.
+  *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,
+  *         STM32H750, STM32H7Axx and STM32H7Bxx lines.
+  *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,
+  *         STM32H7BxxQ lines.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#if defined (DUAL_CORE) /* Dual core lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\
+ ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* Single core lines */
+#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\
+ ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axxx and STM32H7Bxxx lines */
+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \
+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#else /* STM32H7Axx and STM32H7Bxx LDO lines */
+#define __HAL_PWR_GET_FLAG(__FLAG__)                                    \
+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
+ ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))
+#endif /* SMPS */
+#endif /* PWR_CPUCR_SBF_D2 */
+#endif /* DUAL_CORE */
+
+/** @brief  Check PWR wake up flags are set or not.
+  * @param  __FLAG__: specifies the wake up flag to check.
   *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_SB: Standby flag.
-  *            @arg PWR_CPU_FLAGS: Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval The (__FLAG__) state (TRUE or FALSE).
+  */
+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
+
+#if defined (DUAL_CORE)
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2
+  *                                 CPU flags.
   * @retval None.
   */
 #define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \
@@ -319,157 +470,168 @@ do {                                        \
      SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \
 } while(0)
 #else
-/** @brief  Clear PWR flags.
-  * @param  __FLAG__: specifies the flag to clear.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_SB: Standby flag.
-  *            @arg PWR_CPU_FLAGS: Clear STOPF, SBF, SBF_D1, and SBF_D2 CPU flags.
+/** @brief  Clear CPU PWR flags.
+  * @param  __FLAG__ : Specifies the flag to clear.
+  * @note   This parameter is not used for the STM32H7 family and is kept as
+  *         parameter just to maintain compatibility with other families.
+  * @note   This macro clear all CPU flags.
+  *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.
+  *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.
   * @retval None.
   */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__)  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
+#endif /* defined (DUAL_CORE) */
+
+/** @brief  Clear PWR wake up flags.
+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.
+  *           This parameter can be one of the following values :
+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.
+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.
+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.
+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.
+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.
+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.
+  * @retval None.
+  */
+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))
 
 /**
   * @brief Enable the PVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()  SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
   * @brief Enable the PVD EXTI D2 Line 16.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTID2_ENABLE_IT()  SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief Disable the PVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
   * @brief Disable the PVD EXTI D2 Line 16.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTID2_DISABLE_IT()  CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief   Enable event on PVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()  SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
-  * @brief   Enable event on PVD EXTI D2 Line.
+  * @brief Enable event on PVD EXTI D2 Line.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT()  SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief   Disable event on PVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
-  * @brief   Disable event on PVD EXTI D2 Line.
+  * @brief Disable event on PVD EXTI D2 Line.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT()  CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
-  * @brief Enable the PVD Extended Interrupt Rising Trigger.
+  * @brief Enable the PVD Rising Interrupt Trigger.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()  SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
 
 /**
-  * @brief Disable the PVD Extended Interrupt Rising Trigger.
+  * @brief Disable the PVD Rising Interrupt Trigger.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
 
 /**
-  * @brief Enable the PVD Extended Interrupt Falling Trigger.
+  * @brief Enable the PVD Falling Interrupt Trigger.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
 
 /**
-  * @brief Disable the PVD Extended Interrupt Falling Trigger.
+  * @brief Disable the PVD Falling Interrupt Trigger.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
-
+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
 
 /**
-  * @brief  PVD EXTI line configuration: set rising & falling edge trigger.
+  * @brief Enable the PVD Rising & Falling Interrupt Trigger.
   * @retval None.
   */
 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
-do { \
-      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
-      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
+do {                                                    \
+      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
 } while(0);
 
 /**
-  * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
+  * @brief Disable the PVD Rising & Falling Interrupt Trigger.
   * @retval None.
   */
 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
-do { \
-      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
-      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
+do {                                                     \
+      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
+      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
 } while(0);
 
 /**
-  * @brief  Check whether the specified PVD EXTI interrupt flag is set or not.
+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
   * @retval EXTI PVD Line Status.
   */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()  ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
-
+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
-  * @brief checks whether the specified PVD Exti interrupt flag is set or not.
+  * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.
   * @retval EXTI D2 PVD Line Status.
   */
-#define __HAL_PWR_PVD_EXTID2_GET_FLAG()  ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? SET : RESET)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief Clear the PVD EXTI flag.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()  SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
   * @brief Clear the PVD EXTI D2 flag.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG()    SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief  Generates a Software interrupt on PVD EXTI line.
   * @retval None.
   */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()    SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
 /**
   * @}
   */
 
-
 /* Include PWR HAL Extension module */
 #include "stm32h7xx_hal_pwr_ex.h"
 
@@ -534,8 +696,8 @@ void HAL_PWR_DisableSEVOnPend(void);
 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
   * @{
   */
-/*!< External interrupt line 16 Connected to the PVD EXTI Line */
-#define PWR_EXTI_LINE_PVD      ((uint32_t)EXTI_IMR1_IM16)
+#define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                               Connected to the PVD EXTI Line */
 /**
   * @}
   */
@@ -551,26 +713,42 @@ void HAL_PWR_DisableSEVOnPend(void);
 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
   * @{
   */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL))
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
+/* Check PVD level parameter */
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\
+                                 ((LEVEL) == PWR_PVDLEVEL_7))
+
+/* Check PVD mode parameter */
+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\
+                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\
+                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\
+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\
+                               ((MODE) == PWR_PVD_MODE_NORMAL))
+
+/* Check low power regulator parameter */
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\
                                      ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
 
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
+/* Check low power mode entry parameter */
+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\
+                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))
+
+/* Check low power mode entry parameter */
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\
+                                  ((ENTRY) == PWR_STOPENTRY_WFE))
 
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
-#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
+/* Check voltage scale level parameter */
+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \
+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
                                            ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-
 /**
   * @}
   */
@@ -589,8 +767,7 @@ void HAL_PWR_DisableSEVOnPend(void);
 
 #ifdef __cplusplus
 }
-#endif
-
+#endif /* __cplusplus */
 
 #endif /* STM32H7xx_HAL_PWR_H */
 

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_pwr_ex.h

@@ -23,7 +23,7 @@
 
 #ifdef __cplusplus
  extern "C" {
-#endif
+#endif /* __cplusplus */
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
@@ -45,11 +45,15 @@
   */
 typedef struct
 {
-  uint32_t AVDLevel;       /*!< AVDLevel: Specifies the AVD detection level.
-                                 This parameter can be a value of @ref PWREx_AVD_detection_level */
-
-  uint32_t Mode;            /*!< Mode: Specifies the operating mode for the selected pins.
-                                  This parameter can be a value of @ref PWREx_AVD_Mode */
+  uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This
+                          parameter can be a value of @ref
+                          PWREx_AVD_detection_level
+                     */
+
+  uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD
+                                 event. This parameter can be a value of @ref
+                                 PWREx_AVD_Mode.
+                     */
 }PWREx_AVDTypeDef;
 
 /**
@@ -57,19 +61,37 @@ typedef struct
   */
 typedef struct
 {
-  uint32_t WakeUpPin;     /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
-                                This parameter can be a value of @ref PWREx_WakeUp_Pins */
-
-  uint32_t PinPolarity;   /*!< PinPolarity: Specifies the Wake-Up pin polarity.
-                                This parameter can be a value of @ref PWREx_PIN_Polarity */
-
-  uint32_t PinPull;       /*!< PinPull: Specifies the Wake-Up pin pull.
-                                This parameter can be a value of @ref PWREx_PIN_Pull */
+  uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
+                                        This parameter can be a value of @ref
+                                        PWREx_WakeUp_Pins
+                        */
+
+  uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
+                                          This parameter can be a value of @ref
+                                          PWREx_PIN_Polarity
+                        */
+
+  uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This
+                                      parameter can be a value of @ref
+                                      PWREx_PIN_Pull
+                        */
 }PWREx_WakeupPinTypeDef;
 
+#if defined (PWR_CSR1_MMCVDO)
+/**
+  * @brief  PWR VDDMMC voltage level enum definition
+  */
+typedef enum
+{
+  PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */
+  PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */
+} PWREx_MMC_VoltageLevel;
+#endif /* defined (PWR_CSR1_MMCVDO) */
+
 /**
   * @}
   */
+
 /* Exported constants --------------------------------------------------------*/
 
 /** @defgroup PWREx_Exported_Constants PWREx Exported Constants
@@ -78,26 +100,29 @@ typedef struct
 /** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
   * @{
   */
-#define PWR_WAKEUP_PIN6  PWR_WKUPEPR_WKUPEN6
-#define PWR_WAKEUP_PIN5  PWR_WKUPEPR_WKUPEN5
-#define PWR_WAKEUP_PIN4  PWR_WKUPEPR_WKUPEN4
-#define PWR_WAKEUP_PIN3  PWR_WKUPEPR_WKUPEN3
-#define PWR_WAKEUP_PIN2  PWR_WKUPEPR_WKUPEN2
-#define PWR_WAKEUP_PIN1  PWR_WKUPEPR_WKUPEN1
+/* High level and No pull (default configuration) */
+#define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1
+
 /* High level and No pull */
-#define PWR_WAKEUP_PIN6_HIGH  PWR_WKUPEPR_WKUPEN6
-#define PWR_WAKEUP_PIN5_HIGH  PWR_WKUPEPR_WKUPEN5
-#define PWR_WAKEUP_PIN4_HIGH  PWR_WKUPEPR_WKUPEN4
-#define PWR_WAKEUP_PIN3_HIGH  PWR_WKUPEPR_WKUPEN3
-#define PWR_WAKEUP_PIN2_HIGH  PWR_WKUPEPR_WKUPEN2
-#define PWR_WAKEUP_PIN1_HIGH  PWR_WKUPEPR_WKUPEN1
+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6
+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5
+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4
+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3
+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2
+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1
+
 /* Low level and No pull */
-#define PWR_WAKEUP_PIN6_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
-#define PWR_WAKEUP_PIN5_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
-#define PWR_WAKEUP_PIN4_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
-#define PWR_WAKEUP_PIN3_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
-#define PWR_WAKEUP_PIN2_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
-#define PWR_WAKEUP_PIN1_LOW  (uint32_t)(PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
+#define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)
+#define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)
+#define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)
+#define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)
+#define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)
+#define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)
 /**
   * @}
   */
@@ -105,8 +130,8 @@ typedef struct
 /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
   * @{
   */
-#define PWR_PIN_POLARITY_HIGH  ((uint32_t)0x00000000U)
-#define PWR_PIN_POLARITY_LOW   ((uint32_t)0x00000001U)
+#define PWR_PIN_POLARITY_HIGH (0x00000000U)
+#define PWR_PIN_POLARITY_LOW  (0x00000001U)
 /**
   * @}
   */
@@ -114,44 +139,48 @@ typedef struct
 /** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
   * @{
   */
-#define PWR_PIN_NO_PULL    ((uint32_t)0x00000000U)
-#define PWR_PIN_PULL_UP    ((uint32_t)0x00000001U)
-#define PWR_PIN_PULL_DOWN  ((uint32_t)0x00000002U)
+#define PWR_PIN_NO_PULL   (0x00000000U)
+#define PWR_PIN_PULL_UP   (0x00000001U)
+#define PWR_PIN_PULL_DOWN (0x00000002U)
 /**
   * @}
   */
 
-
 /** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.
   * @{
   */
-#define PWR_WAKEUP_FLAG1  PWR_WKUPFR_WKUPF1 /*!< Wakeup event on pin 1 */
-#define PWR_WAKEUP_FLAG2  PWR_WKUPFR_WKUPF2 /*!< Wakeup event on pin 2 */
-#define PWR_WAKEUP_FLAG3  PWR_WKUPFR_WKUPF3 /*!< Wakeup event on pin 3 */
-#define PWR_WAKEUP_FLAG4  PWR_WKUPFR_WKUPF4 /*!< Wakeup event on pin 4 */
-#define PWR_WAKEUP_FLAG5  PWR_WKUPFR_WKUPF5 /*!< Wakeup event on pin 5 */
-#define PWR_WAKEUP_FLAG6  PWR_WKUPFR_WKUPF6 /*!< Wakeup event on pin 6 */
+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */
+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */
+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */
+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */
+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\
+                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\
+                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)
 /**
   * @}
   */
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /** @defgroup PWREx_Core_Select PWREx Core definition
   * @{
   */
-#define PWR_CORE_CPU1  ((uint32_t)0x00000000U)
-#define PWR_CORE_CPU2  ((uint32_t)0x00000001U)
+#define PWR_CORE_CPU1 (0x00000000U)
+#define PWR_CORE_CPU2 (0x00000001U)
 /**
   * @}
   */
-#endif /*DUAL_CORE*/
+#endif /* defined (DUAL_CORE) */
 
 /** @defgroup PWREx_Domains PWREx Domains definition
   * @{
   */
-#define PWR_D1_DOMAIN  ((uint32_t)0x00000000U)
-#define PWR_D2_DOMAIN  ((uint32_t)0x00000001U)
-#define PWR_D3_DOMAIN  ((uint32_t)0x00000002U)
+#define PWR_D1_DOMAIN (0x00000000U)
+#if defined (PWR_CPUCR_PDDS_D2)
+#define PWR_D2_DOMAIN (0x00000001U)
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+#define PWR_D3_DOMAIN (0x00000002U)
 /**
   * @}
   */
@@ -159,12 +188,13 @@ typedef struct
 /** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition
   * @{
   */
-#if defined(DUAL_CORE)
-#define PWR_D1_DOMAIN_FLAGS  ((uint32_t)0x00000000U)
-#define PWR_D2_DOMAIN_FLAGS  ((uint32_t)0x00000001U)
+#if defined (DUAL_CORE)
+#define PWR_D1_DOMAIN_FLAGS  (0x00000000U)
+#define PWR_D2_DOMAIN_FLAGS  (0x00000001U)
+#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)
 #else
-#define PWR_CPU_FLAGS        ((uint32_t)0x00000000U)
-#endif /*DUAL_CORE*/
+#define PWR_CPU_FLAGS       (0x00000000U)
+#endif /* defined (DUAL_CORE) */
 /**
   * @}
   */
@@ -172,8 +202,8 @@ typedef struct
 /** @defgroup PWREx_D3_State PWREx D3 Domain State
   * @{
   */
-#define PWR_D3_DOMAIN_STOP  ((uint32_t)0x00000000U)
-#define PWR_D3_DOMAIN_RUN   ((uint32_t)0x00000800U)
+#define PWR_D3_DOMAIN_STOP (0x00000000U)
+#define PWR_D3_DOMAIN_RUN  (0x00000800U)
 
 /**
   * @}
@@ -183,23 +213,23 @@ typedef struct
   * @{
   */
 #define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */
-#if defined(SMPS)
+#if defined (SMPS)
 #define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */
-#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
-#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */
+#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */
 #define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
 #define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
 #define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */
 #define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */
-#endif /* SMPS */
+#endif /* defined (SMPS) */
 #define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */
 
-#if defined(SMPS)
-#define PWR_SUPPLY_CONFIG_MASK               (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
-                                              PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#if defined (SMPS)
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \
+                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
 #else
-#define PWR_SUPPLY_CONFIG_MASK               (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
-#endif /* SMPS */
+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)
+#endif /* defined (SMPS) */
 /**
   * @}
   */
@@ -208,10 +238,14 @@ typedef struct
 /** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
   * @{
   */
-#define PWR_AVDLEVEL_0  PWR_CR1_ALS_LEV0
-#define PWR_AVDLEVEL_1  PWR_CR1_ALS_LEV1
-#define PWR_AVDLEVEL_2  PWR_CR1_ALS_LEV2
-#define PWR_AVDLEVEL_3  PWR_CR1_ALS_LEV3
+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0
+                                             selection : 1V7                 */
+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1
+                                             selection : 2V1                 */
+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2
+                                             selection : 2V5                 */
+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3
+                                             selection : 2V8                 */
 /**
   * @}
   */
@@ -219,13 +253,13 @@ typedef struct
 /** @defgroup PWREx_AVD_Mode PWREx AVD Mode
   * @{
   */
-#define PWR_AVD_MODE_NORMAL                ((uint32_t)0x00000000U)   /*!< Basic mode is used                                                 */
-#define PWR_AVD_MODE_IT_RISING             ((uint32_t)0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
-#define PWR_AVD_MODE_IT_FALLING            ((uint32_t)0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
-#define PWR_AVD_MODE_IT_RISING_FALLING     ((uint32_t)0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_AVD_MODE_EVENT_RISING          ((uint32_t)0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
-#define PWR_AVD_MODE_EVENT_FALLING         ((uint32_t)0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
-#define PWR_AVD_MODE_EVENT_RISING_FALLING  ((uint32_t)0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
+#define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */
+#define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */
+#define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */
+#define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
+#define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */
+#define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */
+#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */
 /**
   * @}
   */
@@ -233,9 +267,9 @@ typedef struct
 /** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
   * @{
   */
-#define PWR_REGULATOR_SVOS_SCALE5  (PWR_CR1_SVOS_0)
-#define PWR_REGULATOR_SVOS_SCALE4  (PWR_CR1_SVOS_1)
-#define PWR_REGULATOR_SVOS_SCALE3  (uint32_t)(PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)
+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)
+#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)
 /**
   * @}
   */
@@ -243,8 +277,8 @@ typedef struct
 /** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection
   * @{
   */
-#define PWR_BATTERY_CHARGING_RESISTOR_5    ((uint32_t)0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
-#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS            /*!< VBAT charging through a 1.5 kOhms resistor */
+#define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */
+#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */
 /**
   * @}
   */
@@ -252,7 +286,7 @@ typedef struct
 /** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds
   * @{
   */
-#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  ((uint32_t)0x00000000U)
+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
 #define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL
 #define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH
 /**
@@ -262,7 +296,7 @@ typedef struct
 /** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds
   * @{
   */
-#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  ((uint32_t)0x00000000U)
+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)
 #define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL
 #define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH
 /**
@@ -271,14 +305,37 @@ typedef struct
 /** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
   * @{
   */
-#define PWR_EXTI_LINE_AVD  ((uint32_t)EXTI_IMR1_IM16) /*!< External interrupt line 16 Connected to the AVD EXTI Line */
+#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
+                                              Connected to the AVD EXTI Line */
 /**
   * @}
   */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
+  * @{
+  */
+#define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */
+#define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */
+#define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */
+#define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */
+#define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */
+#define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */
+#define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */
+#define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */
+/**
+  * @}
+  */
+#endif /* defined (PWR_CR1_SRDRAMSO) */
 /**
   * @}
   */
+
 /* Exported macro ------------------------------------------------------------*/
+
 /** @defgroup PWREx_Exported_Macro PWREx Exported Macro
   *  @{
   */
@@ -287,147 +344,150 @@ typedef struct
   * @brief Enable the AVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_ENABLE_IT()  SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
   * @brief Enable the AVD EXTI D2 Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTID2_ENABLE_IT()  SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief Disable the AVD EXTI Line 16
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_DISABLE_IT()  CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
   * @brief Disable the AVD EXTI D2 Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTID2_DISABLE_IT()  CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
-  * @brief   Enable event on AVD EXTI Line 16.
+  * @brief Enable event on AVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT()  SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
-  * @brief   Enable event on AVD EXTI D2 Line 16.
+  * @brief Enable event on AVD EXTI D2 Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT()  SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
-  * @brief   Disable event on AVD EXTI Line 16.
+  * @brief Disable event on AVD EXTI Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
-  * @brief   Disable event on AVD EXTI D2 Line 16.
+  * @brief Disable event on AVD EXTI D2 Line 16.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT()  CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
 
 /**
-  * @brief  Enable the AVD Extended Interrupt Rising Trigger.
+  * @brief Enable the AVD Extended Interrupt Rising Trigger.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE()  SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
 
 /**
-  * @brief  Disable the AVD Extended Interrupt Rising Trigger.
+  * @brief Disable the AVD Extended Interrupt Rising Trigger.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
 
 /**
-  * @brief  Enable the AVD Extended Interrupt Falling Trigger.
+  * @brief Enable the AVD Extended Interrupt Falling Trigger.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
-
+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
 
 /**
-  * @brief  Disable the AVD Extended Interrupt Falling Trigger.
+  * @brief Disable the AVD Extended Interrupt Falling Trigger.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
-
+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
 
 /**
-  * @brief  AVD EXTI line configuration: set rising & falling edge trigger.
+  * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \
-  __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
-  __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
+do {                                                    \
+     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \
 } while(0);
 
 /**
-  * @brief  Disable the AVD Extended Interrupt Rising & Falling Trigger.
+  * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE()  \
-do { \
-  __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
-  __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
+do {                                                     \
+     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \
+     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \
 } while(0);
 
 /**
-  * @brief  Check whether the specified AVD EXTI interrupt flag is set or not.
+  * @brief Check whether the specified AVD EXTI interrupt flag is set or not.
   * @retval EXTI AVD Line Status.
   */
-#define __HAL_PWR_AVD_EXTI_GET_FLAG()  ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
-  * @brief  Check whether the specified AVD EXTI D2 interrupt flag is set or not.
+  * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.
   * @retval EXTI D2 AVD Line Status.
   */
-#define __HAL_PWR_AVD_EXTID2_GET_FLAG()  ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? SET : RESET)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
+#endif /* defined (DUAL_CORE) */
 
 /**
   * @brief  Clear the AVD EXTI flag.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG()  SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
 /**
   * @brief  Clear the AVD EXTI D2 flag.
   * @retval None.
   */
-#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG()  SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
-#endif /*DUAL_CORE*/
+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)
+#endif /* defined (DUAL_CORE) */
 
+/**
+  * @brief  Generates a Software interrupt on AVD EXTI line.
+  * @retval None.
+  */
+#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
 /**
   * @}
   */
 
 /* Exported functions --------------------------------------------------------*/
+
 /** @addtogroup PWREx_Exported_Functions PWREx Exported Functions
   * @{
   */
 
-/** @addtogroup PWREx_Exported_Functions_Group1 Power supply control functions
+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions
   * @{
   */
-/* Power supply control functions */
 HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
 uint32_t HAL_PWREx_GetSupplyConfig(void);
-/* Power volatge scaling functions */
 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
 uint32_t HAL_PWREx_GetVoltageRange(void);
 HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
@@ -436,35 +496,38 @@ uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
   * @}
   */
 
-/** @addtogroup PWREx_Exported_Functions_Group2 Low power control functions
+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions
   * @{
   */
 /* System low power control functions */
+#if defined (PWR_CPUCR_RETDS_CD)
+void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);
+#endif /* defined (PWR_CPUCR_RETDS_CD) */
 void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);
 void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);
 void HAL_PWREx_ConfigD3Domain(uint32_t D3State);
-
-#if defined(DUAL_CORE)
+/* Clear Cortex-Mx pending flag */
+void HAL_PWREx_ClearPendingEvent(void);
+#if defined (DUAL_CORE)
+/* Clear domain flags */
 void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);
-
-/* Power core holding functions */
+/* Core Hold/Release functions */
 HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);
 void HAL_PWREx_ReleaseCore(uint32_t CPU);
-
-#endif /*DUAL_CORE*/
-
-/* Clear pending event function */
-void HAL_PWREx_ClearPendingEvent(void);
-
+#endif /* defined (DUAL_CORE) */
 /* Flash low power control functions */
 void HAL_PWREx_EnableFlashPowerDown(void);
 void HAL_PWREx_DisableFlashPowerDown(void);
+#if defined (PWR_CR1_SRDRAMSO)
+/* Memory shut-off functions */
+void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
+void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
+#endif /* defined(PWR_CR1_SRDRAMSO) */
 /* Wakeup Pins control functions */
 void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);
 void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);
 uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);
 HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);
-
 /* Power Wakeup PIN IRQ Handler */
 void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);
 void HAL_PWREx_WKUP1_Callback(void);
@@ -477,22 +540,25 @@ void HAL_PWREx_WKUP6_Callback(void);
   * @}
   */
 
-/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals control functions
+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions
   * @{
   */
 /* Backup regulator control functions */
 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
-
 /* USB regulator control functions */
 HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);
 HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);
 void HAL_PWREx_EnableUSBVoltageDetector(void);
 void HAL_PWREx_DisableUSBVoltageDetector(void);
-
 /* Battery control functions */
 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
 void HAL_PWREx_DisableBatteryCharging(void);
+#if defined(PWR_CR1_BOOSTE)
+/* Analog Booster functions */
+void HAL_PWREx_EnableAnalogBooster(void);
+void HAL_PWREx_DisableAnalogBooster(void);
+#endif /* PWR_CR1_BOOSTE */
 /**
   * @}
   */
@@ -505,16 +571,16 @@ void HAL_PWREx_EnableMonitoring(void);
 void HAL_PWREx_DisableMonitoring(void);
 uint32_t HAL_PWREx_GetTemperatureLevel(void);
 uint32_t HAL_PWREx_GetVBATLevel(void);
-
+#if defined(PWR_CSR1_MMCVDO)
+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);
+#endif /* PWR_CSR1_MMCVDO */
 /* Power AVD configuration functions */
 void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);
 void HAL_PWREx_EnableAVD(void);
 void HAL_PWREx_DisableAVD(void);
-
 /* Power PVD/AVD IRQ Handler */
 void HAL_PWREx_PVD_AVD_IRQHandler(void);
 void HAL_PWREx_AVDCallback(void);
-
 /**
   * @}
   */
@@ -533,87 +599,126 @@ void HAL_PWREx_AVDCallback(void);
 /** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters
   * @{
   */
-#if defined(SMPS)
-#define IS_PWR_SUPPLY(PWR_SOURCE)  (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    || \
-                                    ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            || \
-                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         || \
-                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         || \
-                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
-                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
-                                    ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         || \
-                                    ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         || \
-                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+/* Check PWR regulator configuration parameter */
+#if defined (SMPS)
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\
+                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
 
 #else
-#define IS_PWR_SUPPLY(PWR_SOURCE)  (((PWR_SOURCE) == PWR_LDO_SUPPLY) || \
-                                    ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
-#endif /*SMPS*/
-
-#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE)  (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  || \
-                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  || \
-                                                      ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
-
-#define IS_PWR_DOMAIN(DOMAIN)  (((DOMAIN) == PWR_D1_DOMAIN) || \
-                                ((DOMAIN) == PWR_D2_DOMAIN) || \
-                                ((DOMAIN) == PWR_D3_DOMAIN))
-
-#define IS_D3_STATE(STATE)  (((STATE) == PWR_D3_DOMAIN_STOP) || ((STATE) == PWR_D3_DOMAIN_RUN))
-
-#define IS_PWR_WAKEUP_PIN(PIN)  (((PIN) == PWR_WAKEUP_PIN1)       || \
-                                 ((PIN) == PWR_WAKEUP_PIN2)       || \
-                                 ((PIN) == PWR_WAKEUP_PIN3)       || \
-                                 ((PIN) == PWR_WAKEUP_PIN4)       || \
-                                 ((PIN) == PWR_WAKEUP_PIN5)       || \
-                                 ((PIN) == PWR_WAKEUP_PIN6)       || \
-                                 ((PIN) == PWR_WAKEUP_PIN1_HIGH)  || \
-                                 ((PIN) == PWR_WAKEUP_PIN2_HIGH)  || \
-                                 ((PIN) == PWR_WAKEUP_PIN3_HIGH)  || \
-                                 ((PIN) == PWR_WAKEUP_PIN4_HIGH)  || \
-                                 ((PIN) == PWR_WAKEUP_PIN5_HIGH)  || \
-                                 ((PIN) == PWR_WAKEUP_PIN6_HIGH)  || \
-                                 ((PIN) == PWR_WAKEUP_PIN1_LOW)   || \
-                                 ((PIN) == PWR_WAKEUP_PIN2_LOW)   || \
-                                 ((PIN) == PWR_WAKEUP_PIN3_LOW)   || \
-                                 ((PIN) == PWR_WAKEUP_PIN4_LOW)   || \
-                                 ((PIN) == PWR_WAKEUP_PIN5_LOW)    || \
-                                 ((PIN) == PWR_WAKEUP_PIN6_LOW))
-
-#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY)  (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
-                                               ((POLARITY) == PWR_PIN_POLARITY_LOW))
-
-#define IS_PWR_WAKEUP_PIN_PULL(PULL)  (((PULL) == PWR_PIN_NO_PULL)  || \
-                                       ((PULL) == PWR_PIN_PULL_UP)  || \
-                                       ((PULL) == PWR_PIN_PULL_DOWN))
-
-#define IS_PWR_WAKEUP_FLAG(FLAG)  (((FLAG) == PWR_WAKEUP_FLAG1)  || \
-                                   ((FLAG) == PWR_WAKEUP_FLAG2)  || \
-                                   ((FLAG) == PWR_WAKEUP_FLAG3)  || \
-                                   ((FLAG) == PWR_WAKEUP_FLAG4)  || \
-                                   ((FLAG) == PWR_WAKEUP_FLAG5)  || \
-                                   ((FLAG) == PWR_WAKEUP_FLAG6))
-
-#define IS_PWR_AVD_LEVEL(LEVEL)  (((LEVEL) == PWR_AVDLEVEL_0) || ((LEVEL) == PWR_AVDLEVEL_1) || \
-                                  ((LEVEL) == PWR_AVDLEVEL_2) || ((LEVEL) == PWR_AVDLEVEL_3))
-
-#define IS_PWR_AVD_MODE(MODE)  (((MODE) == PWR_AVD_MODE_IT_RISING)|| ((MODE) == PWR_AVD_MODE_IT_FALLING) || \
-                                ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING) || \
-                                ((MODE) == PWR_AVD_MODE_EVENT_FALLING) || ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING) || \
-                                ((MODE) == PWR_AVD_MODE_NORMAL))
-
-#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR)  (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
-                                                   ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
-
+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\
+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))
+#endif /* defined (SMPS) */
+
+/* Check PWR regulator configuration in STOP mode parameter */
+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\
+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
+
+/* Check PWR domain parameter */
+#if defined (PWR_CPUCR_PDDS_D2)
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D2_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#else
+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\
+                               ((DOMAIN) == PWR_D3_DOMAIN))
+#endif /* defined (PWR_CPUCR_PDDS_D2) */
+
+/* Check D3/SRD domain state parameter */
+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\
+                            ((STATE) == PWR_D3_DOMAIN_RUN))
+
+/* Check wake up pin parameter */
+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN2)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN3)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN4)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN5)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN6)      ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
+                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\
+                                ((PIN) == PWR_WAKEUP_PIN6_LOW))
+
+/* Check wake up pin polarity parameter */
+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
+                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))
+
+/* Check wake up pin pull configuration parameter */
+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
+                                      ((PULL) == PWR_PIN_PULL_UP) ||\
+                                      ((PULL) == PWR_PIN_PULL_DOWN))
+
+/* Check wake up flag parameter */
+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\
+                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))
+
+/* Check wake up flag parameter */
+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\
+                                 ((LEVEL) == PWR_AVDLEVEL_3))
+
+/* Check AVD mode parameter */
+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\
+                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\
+                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\
+                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\
+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
+
+/* Check resistor battery parameter */
+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
+/* Check D1/CD CPU ID parameter */
 #define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)
 
-#if defined(DUAL_CORE)
+#if defined (DUAL_CORE)
+/* Check CPU parameter */
 #define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
 
+/* Check D2 CPU ID parameter */
 #define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)
 
+/* Check PWR domain flag parameter */
 #define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \
-                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS))
-#endif /*DUAL_CORE*/
-
+                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \
+                                   ((FLAG) == PWR_ALL_DOMAIN_FLAGS))
+#endif /* defined (DUAL_CORE) */
+
+#if defined (PWR_CR1_SRDRAMSO)
+/* Check memory block parameter */
+#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \
+                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \
+                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \
+                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \
+                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))
+#endif /* defined (PWR_CR1_SRDRAMSO) */
 /**
   * @}
   */
@@ -630,7 +735,7 @@ void HAL_PWREx_AVDCallback(void);
   */
 #ifdef __cplusplus
 }
-#endif
+#endif /* __cplusplus */
 
 
 #endif /* STM32H7xx_HAL_PWR_EX_H */

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_qspi.h

@@ -25,6 +25,8 @@
  extern "C" {
 #endif
 
+#if defined(QUADSPI)
+
 /* Includes ------------------------------------------------------------------*/
 #include "stm32h7xx_hal_def.h"
 
@@ -733,6 +735,9 @@ HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint3
 /**
   * @}
   */
+
+#endif /* QUADSPI */
+
 #ifdef __cplusplus
 }
 #endif

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_ramecc.h

@@ -61,8 +61,9 @@ typedef enum
 
 typedef struct __RAMECC_HandleTypeDef
 {
-  RAMECC_MonitorTypeDef           *Instance;                                                             /*!< Register base address        */
-  __IO HAL_RAMECC_StateTypeDef    State;                                                                 /*!< RAMECC state                 */
+  RAMECC_MonitorTypeDef           *Instance;                                                            /*!< Register base address        */
+  __IO HAL_RAMECC_StateTypeDef    State;                                                                /*!< RAMECC state                 */
+  __IO uint32_t                   ErrorCode;                                                            /*!< RAMECC Error Code            */
   void                            (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc);     /*!< RAMECC error detect callback */
 }RAMECC_HandleTypeDef;
 
@@ -73,6 +74,17 @@ typedef struct __RAMECC_HandleTypeDef
 
 /* Exported constants --------------------------------------------------------*/
 
+/** @defgroup RAMECC_Error_Codes RAMECC Error Codes
+  * @{
+  */
+#define HAL_RAMECC_ERROR_NONE              0x00000000U  /*!< RAMECC No Error         */
+#define HAL_RAMECC_ERROR_TIMEOUT           0x00000001U  /*!< RAMECC Timeout Error    */
+#define HAL_RAMECC_ERROR_BUSY              0x00000002U  /*!< RAMECC Busy Error       */
+#define HAL_RAMECC_ERROR_INVALID_CALLBACK  0x00000003U  /*!< Invalid Callback error  */
+/**
+  * @}
+  */
+
 /** @defgroup RAMECC_Interrupt RAMECC interrupts
   * @{
   */
@@ -135,8 +147,7 @@ typedef struct __RAMECC_HandleTypeDef
 (__HAL_RAMECC_ENABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))
 
 
-
-#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)&(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
+#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))
 #define __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))
 
 /**
@@ -160,6 +171,30 @@ typedef struct __RAMECC_HandleTypeDef
 (__HAL_RAMECC_DISABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))
 
 
+#define __HAL_RAMECC_GET_GLOBAL_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
+#define __HAL_RAMECC_GET_MONITOR_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)
+
+/**
+  * @brief  Check whether the specified RAMECC interrupt source is enabled or not.
+  * @param  __HANDLE__    : Specifies the RAMECC Handle.
+  * @param  __INTERRUPT__ : Specifies the RAMECC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.
+  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.
+  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.
+  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (  \
+(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_GET_GLOBAL_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\
+(__HAL_RAMECC_GET_MONITOR_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))
+
+
 /**
   * @brief  Get the RAMECC pending flags.
   * @param  __HANDLE__   : RAMECC handle.
@@ -169,7 +204,7 @@ typedef struct __RAMECC_HandleTypeDef
   *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.
   *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.
   *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.
-  * @retval None.
+  * @retval The state of __FLAG__ (SET or RESET).
   */
 #define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))
 
@@ -187,6 +222,12 @@ typedef struct __RAMECC_HandleTypeDef
   */
 #define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))
 
+/**
+  * @brief  Reset the RAMECC handle state.
+  * @param  __HANDLE__    : Specifies the RAMECC Handle.
+  * @retval None.
+  */
+#define __HAL_RAMECC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET)
 /**
   * @}
   */
@@ -198,16 +239,12 @@ typedef struct __RAMECC_HandleTypeDef
   * @{
   */
 
-
-
-
-
 /** @defgroup RAMECC_Exported_Functions_Group1 Initialization and de-initialization functions
   * @brief    Initialization and de-initialization functions
   * @{
   */
-HAL_StatusTypeDef HAL_RAMECC_Init(RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_Init   (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);
 /**
   * @}
   */
@@ -216,13 +253,27 @@ HAL_StatusTypeDef HAL_RAMECC_DeInit(RAMECC_HandleTypeDef *hramecc);
   * @brief    monitoring operation functions
   * @{
   */
-HAL_StatusTypeDef HAL_RAMECC_StartMonitor(RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_StopMonitor(RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_EnableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
-HAL_StatusTypeDef HAL_RAMECC_DisableNotification(RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
-void              HAL_RAMECC_IRQHandler(RAMECC_HandleTypeDef *hramecc);
-HAL_StatusTypeDef HAL_RAMECC_RegisterCallback(RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
-HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_StartMonitor        (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_StopMonitor         (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_EnableNotification  (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
+HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);
+void              HAL_RAMECC_IRQHandler          (RAMECC_HandleTypeDef *hramecc);
+HAL_StatusTypeDef HAL_RAMECC_RegisterCallback    (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));
+HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback  (RAMECC_HandleTypeDef *hramecc);
+/**
+  * @}
+  */
+
+/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions
+  * @brief    Error informations functions
+  * @{
+  */
+uint32_t HAL_RAMECC_GetFailingAddress        (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingDataLow        (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetFailingDataHigh       (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_GetHammingErrorCode      (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc);
+uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc);
 /**
   * @}
   */
@@ -231,10 +282,8 @@ HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback(RAMECC_HandleTypeDef *hramecc);
   * @brief    Error informations functions
   * @{
   */
-uint32_t HAL_RAMECC_GetFailingAddress(RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetFailingDataLow(RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetFailingDataHigh(RAMECC_HandleTypeDef *hramecc);
-uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc);
+HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);
+uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);
 /**
   * @}
   */
@@ -257,17 +306,17 @@ uint32_t HAL_RAMECC_GetHammingErrorCode(RAMECC_HandleTypeDef *hramecc);
   * @{
   */
 
-#define IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT) ((((INTERRUPT) & RAMECC_IT_GLOBAL_ENABLE)      == RAMECC_IT_GLOBAL_ENABLE)      || \
-                                               (((INTERRUPT) & RAMECC_IT_GLOBAL_SINGLEERR_R) == RAMECC_IT_GLOBAL_SINGLEERR_R) || \
-                                               (((INTERRUPT) & RAMECC_IT_GLOBAL_DOUBLEERR_R) == RAMECC_IT_GLOBAL_DOUBLEERR_R) || \
-                                               (((INTERRUPT) & RAMECC_IT_GLOBAL_DOUBLEERR_W) == RAMECC_IT_GLOBAL_DOUBLEERR_W) || \
-                                               (((INTERRUPT) & RAMECC_IT_GLOBAL_ALL)         == RAMECC_IT_GLOBAL_ALL))
+#define IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_GLOBAL_ENABLE)      || \
+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_SINGLEERR_R) || \
+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_R) || \
+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_W) || \
+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_ALL))
 
 
-#define IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT) ((((INTERRUPT) & RAMECC_IT_MONITOR_SINGLEERR_R) == RAMECC_IT_MONITOR_SINGLEERR_R) || \
-                                                (((INTERRUPT) & RAMECC_IT_MONITOR_DOUBLEERR_R) == RAMECC_IT_MONITOR_DOUBLEERR_R) || \
-                                                (((INTERRUPT) & RAMECC_IT_MONITOR_DOUBLEERR_W) == RAMECC_IT_MONITOR_DOUBLEERR_W) || \
-                                                (((INTERRUPT) & RAMECC_IT_MONITOR_ALL)         == RAMECC_IT_MONITOR_ALL))
+#define IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_MONITOR_SINGLEERR_R) || \
+                                                ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_R) || \
+                                                ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_W) || \
+                                                ((INTERRUPT) == RAMECC_IT_MONITOR_ALL))
 
 #define IS_RAMECC_INTERRUPT(INTERRUPT) ((IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)) || \
                                         (IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT)))

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng.h

@@ -22,7 +22,7 @@
 #define STM32H7xx_HAL_RNG_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -176,7 +176,9 @@ typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
 #define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */
 #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
 #define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error        */
-
+#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */
+#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */
+#define  HAL_RNG_ERROR_CLOCK            0x00000010U   /*!< Clock error        */
 /**
   * @}
   */
@@ -282,6 +284,10 @@ typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
   * @}
   */
 
+#if defined (RNG_CR_CONDRST)
+/* Include HASH HAL Extended module */
+#include "stm32h7xx_hal_rng_ex.h"
+#endif  /* CONDRST */
 /* Exported functions --------------------------------------------------------*/
 /** @defgroup RNG_Exported_Functions RNG Exported Functions
   * @{

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rng_ex.h

@@ -0,0 +1,241 @@
+/**
+  ******************************************************************************
+  * @file    stm32h7xx_hal_rng_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of RNG HAL Extension module.
+  ******************************************************************************
+  * @attention
+  *
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
+  *
+  * This software component is licensed by ST under BSD 3-Clause license,
+  * the "License"; You may not use this file except in compliance with the
+  * License. You may obtain a copy of the License at:
+  *                        opensource.org/licenses/BSD-3-Clause
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32H7xx_HAL_RNG_EX_H
+#define STM32H7xx_HAL_RNG_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h7xx_hal_def.h"
+
+/** @addtogroup STM32H7xx_HAL_Driver
+  * @{
+  */
+
+#if defined (RNG)
+#if defined (RNG_CR_CONDRST)
+
+/** @defgroup RNGEx RNGEx
+  * @brief RNG Extension HAL module driver
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup RNGEx_Exported_Types RNGEx Exported Types
+  * @brief RNGEx Exported types
+  * @{
+  */
+
+/**
+  * @brief RNGEX Configuration Structure definition
+  */
+
+typedef struct
+{
+  uint32_t        Config1;           /*!< Config1 must be a value between 0 and 0x3F */
+  uint32_t        Config2;           /*!< Config2 must be a value between 0 and 0x7 */
+  uint32_t        Config3;           /*!< Config3 must be a value between 0 and 0xF */
+  uint32_t        ClockDivider;      /*!< Clock Divider factor.This parameter can
+                                          be a value of @ref RNGEX_Clock_Divider_Factor   */
+  uint32_t        NistCompliance;    /*!< NIST compliance.This parameter can be a
+                                          value of @ref RNGEX_NIST_Compliance   */
+} RNG_ConfigTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants
+  * @{
+  */
+
+/** @defgroup RNGEX_Clock_Divider_Factor  Value used to configure an internal
+ *            programmable divider acting on the incoming RNG clock
+  * @{
+  */
+#define RNG_CLKDIV_BY_1       (0x00000000UL)      /*!< No clock division  */
+#define RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)
+/*!< 2 RNG clock cycles per internal RNG clock    */
+#define RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)
+/*!< 4 RNG clock cycles per internal RNG clock    */
+#define RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 8 RNG clock cycles per internal RNG clock    */
+#define RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)
+/*!< 16 RNG clock cycles per internal RNG clock   */
+#define RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
+/*!< 32 RNG clock cycles per internal RNG clock   */
+#define RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
+/*!< 64 RNG clock cycles per internal RNG clock   */
+#define RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 128 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)
+/*!< 256 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)
+/*!< 512 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)
+/*!< 1024 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 2048 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)
+/*!< 4096 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)
+/*!< 8192 RNG clock cycles per internal RNG clock  */
+#define RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)
+/*!< 16384 RNG clock cycles per internal RNG clock */
+#define RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)
+/*!< 32768 RNG clock cycles per internal RNG clock */
+/**
+  * @}
+  */
+
+/** @defgroup RNGEX_NIST_Compliance  NIST Compliance configuration
+  * @{
+  */
+#define RNG_NIST_COMPLIANT     (0x00000000UL) /*!< NIST compliant configuration*/
+#define RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Types RNGEx Private Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Variables RNGEx Private Variables
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Macros RNGEx Private Macros
+  * @{
+  */
+
+#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8)     || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16)    || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32)    || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64)    || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128)   || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256)   || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512)   || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192)  || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \
+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))
+
+
+#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \
+                                                     ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))
+
+#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)
+
+#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)
+
+#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)
+
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup RNGEx_Private_Functions RNGEx Private Functions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions
+  * @{
+  */
+
+/** @addtogroup RNGEx_Exported_Functions_Group1
+  * @{
+  */
+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);
+HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif  /* CONDRST */
+#endif /* RNG */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32H7xx_HAL_RNGEX_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_rtc.h

@@ -22,7 +22,7 @@
 #define STM32H7xx_HAL_RTC_H
 
 #ifdef __cplusplus
- extern "C" {
+extern "C" {
 #endif
 
 /* Includes ------------------------------------------------------------------*/
@@ -32,7 +32,7 @@
   * @{
   */
 
-/** @addtogroup RTC
+/** @defgroup RTC RTC
   * @{
   */
 
@@ -40,18 +40,19 @@
 /** @defgroup RTC_Exported_Types RTC Exported Types
   * @{
   */
+
 /**
   * @brief  HAL State structures definition
   */
 typedef enum
 {
-  HAL_RTC_STATE_RESET             = 0x00u,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01u,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02u,  /*!< RTC process is ongoing              */
-  HAL_RTC_STATE_TIMEOUT           = 0x03u,  /*!< RTC timeout state                   */
-  HAL_RTC_STATE_ERROR             = 0x04u   /*!< RTC error state                     */
+  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */
+  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */
+  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */
+  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */
+  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */
 
-}HAL_RTCStateTypeDef;
+} HAL_RTCStateTypeDef;
 
 /**
   * @brief  RTC Configuration Structure definition
@@ -70,7 +71,7 @@ typedef struct
   uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.
                                  This parameter can be a value of @ref RTCEx_Output_selection_Definitions */
 
-  uint32_t OutPutRemap;    /*!< Specifies the remap for RTC output.
+  uint32_t OutPutRemap;     /*!< Specifies the remap for RTC output.
                                  This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */
 
   uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.
@@ -78,8 +79,11 @@ typedef struct
 
   uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.
                                  This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */
-
-}RTC_InitTypeDef;
+#if defined(RTC_CR_TAMPALRM_PU)
+  uint32_t OutPutPullUp;    /*!< Specifies the RTC Output Pull-Up mode.
+                                 This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */
+#endif /* RTC_CR_TAMPALRM_PU */
+} RTC_InitTypeDef;
 
 /**
   * @brief  RTC Time structure definition
@@ -115,7 +119,7 @@ typedef struct
   uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BKP bit
                                  in CR register to store the operation.
                                  This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef;
+} RTC_TimeTypeDef;
 
 /**
   * @brief  RTC Date structure definition
@@ -134,7 +138,7 @@ typedef struct
   uint8_t Year;     /*!< Specifies the RTC Date Year.
                          This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
 
-}RTC_DateTypeDef;
+} RTC_DateTypeDef;
 
 /**
   * @brief  RTC Alarm structure definition
@@ -158,7 +162,7 @@ typedef struct
 
   uint32_t Alarm;                /*!< Specifies the alarm .
                                       This parameter can be a value of @ref RTC_Alarms_Definitions */
-}RTC_AlarmTypeDef;
+} RTC_AlarmTypeDef;
 
 /**
   * @brief  RTC Handle Structure definition
@@ -178,27 +182,55 @@ typedef struct
   __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */
 
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-  void  (* AlarmAEventCallback)      ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Alarm A Event callback         */
+  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm A Event callback         */
 
-  void  (* AlarmBEventCallback)      ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Alarm B Event callback         */
+  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm B Event callback         */
 
-  void  (* TimeStampEventCallback)   ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC TimeStamp Event callback       */
+  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC TimeStamp Event callback       */
 
-  void  (* WakeUpTimerEventCallback) ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC WakeUpTimer Event callback     */
+  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);       /*!< RTC WakeUpTimer Event callback     */
 
-  void  (* Tamper1EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Tamper 1 Event callback        */
+  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 1 Event callback        */
 
-  void  (* Tamper2EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Tamper 2 Event callback        */
+  void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 2 Event callback        */
 
-  void  (* Tamper3EventCallback)     ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Tamper 3 Event callback        */
+  void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 3 Event callback        */
 
-  void  (* MspInitCallback)          ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Msp Init callback              */
+#if defined(TAMP_CR1_ITAMP1E)
+  void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 1 Event callback  */
+#endif /* TAMP_CR1_ITAMP1E */
 
-  void  (* MspDeInitCallback)        ( struct __RTC_HandleTypeDef * hrtc);  /*!< RTC Msp DeInit callback            */
+#if defined(TAMP_CR1_ITAMP2E)
+  void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 2 Event callback  */
+#endif /* TAMP_CR1_ITAMP2E */
 
-#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */
+#if defined(TAMP_CR1_ITAMP3E)
+  void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 3 Event callback  */
+#endif /* TAMP_CR1_ITAMP3E */
+
+#if defined(TAMP_CR1_ITAMP4E)
+  void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 4 Event callback  */
+#endif /* TAMP_CR1_ITAMP4E */
+
+#if defined(TAMP_CR1_ITAMP5E)
+  void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 5 Event callback  */
+#endif /* TAMP_CR1_ITAMP5E */
+
+#if defined(TAMP_CR1_ITAMP6E)
+  void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 6 Event callback  */
+#endif /* TAMP_CR1_ITAMP6E */
 
-}RTC_HandleTypeDef;
+#if defined(TAMP_CR1_ITAMP8E)
+  void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 8 Event callback  */
+#endif /* TAMP_CR1_ITAMP8E */
+
+  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                /*!< RTC Msp Init callback              */
+
+  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);              /*!< RTC Msp DeInit callback            */
+
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
+
+} RTC_HandleTypeDef;
 
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
 /**
@@ -206,22 +238,44 @@ typedef struct
   */
 typedef enum
 {
-  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0x00u,    /*!< RTC Alarm A Event Callback ID      */
-  HAL_RTC_ALARM_B_EVENT_CB_ID           = 0x01u,    /*!< RTC Alarm B Event Callback ID      */
-  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 0x02u,    /*!< RTC TimeStamp Event Callback ID    */
-  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 0x03u,    /*!< RTC WakeUp Timer Event Callback ID */
-  HAL_RTC_TAMPER1_EVENT_CB_ID           = 0x04u,    /*!< RTC Tamper 1 Callback ID           */
-  HAL_RTC_TAMPER2_EVENT_CB_ID           = 0x05u,    /*!< RTC Tamper 2 Callback ID           */
-  HAL_RTC_TAMPER3_EVENT_CB_ID           = 0x06u,    /*!< RTC Tamper 3 Callback ID           */
-  HAL_RTC_MSPINIT_CB_ID                 = 0x0Eu,    /*!< RTC Msp Init callback ID           */
-  HAL_RTC_MSPDEINIT_CB_ID               = 0x0Fu     /*!< RTC Msp DeInit callback ID         */
-}HAL_RTC_CallbackIDTypeDef;
+  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0u,    /*!< RTC Alarm A Event Callback ID      */
+  HAL_RTC_ALARM_B_EVENT_CB_ID           = 1u,    /*!< RTC Alarm B Event Callback ID      */
+  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 2u,    /*!< RTC TimeStamp Event Callback ID    */
+  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 3u,    /*!< RTC WakeUp Timer Event Callback ID */
+  HAL_RTC_TAMPER1_EVENT_CB_ID           = 4u,    /*!< RTC Tamper 1 Callback ID           */
+  HAL_RTC_TAMPER2_EVENT_CB_ID           = 5u,    /*!< RTC Tamper 2 Callback ID           */
+  HAL_RTC_TAMPER3_EVENT_CB_ID           = 6u,    /*!< RTC Tamper 3 Callback ID           */
+
+#if defined(TAMP_CR1_ITAMP1E)
+  HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID  = 12u,   /*!< RTC Internal Tamper 1 Callback ID  */
+#endif /* TAMP_CR1_ITAMP1E */
+#if defined(TAMP_CR1_ITAMP2E)
+  HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID  = 13u,   /*!< RTC Internal Tamper 2 Callback ID  */
+#endif /* TAMP_CR1_ITAMP2E */
+#if defined(TAMP_CR1_ITAMP3E)
+  HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 14u,   /*!< RTC Internal Tamper 3 Callback ID  */
+#endif /* TAMP_CR1_ITAMP3E */
+#if defined(TAMP_CR1_ITAMP4E)
+  HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 15u,   /*!< RTC Internal Tamper 4 Callback ID  */
+#endif /* TAMP_CR1_ITAMP4E */
+#if defined(TAMP_CR1_ITAMP5E)
+  HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 16u,   /*!< RTC Internal Tamper 5 Callback ID  */
+#endif /* TAMP_CR1_ITAMP5E */
+#if defined(TAMP_CR1_ITAMP6E)
+  HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 17u,   /*!< RTC Internal Tamper 6 Callback ID  */
+#endif /* TAMP_CR1_ITAMP6E */
+#if defined(TAMP_CR1_ITAMP8E)
+  HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID  = 19u,   /*!< RTC Internal Tamper 8 Callback ID  */
+#endif /* TAMP_CR1_ITAMP8E */
+  HAL_RTC_MSPINIT_CB_ID                 = 20u,   /*!< RTC Msp Init callback ID           */
+  HAL_RTC_MSPDEINIT_CB_ID               = 21u    /*!< RTC Msp DeInit callback ID         */
+} HAL_RTC_CallbackIDTypeDef;
 
 /**
   * @brief  HAL RTC Callback pointer definition
   */
-typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to an RTC callback function */
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
 
 /**
   * @}
@@ -232,7 +286,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   * @{
   */
 
-/** @defgroup RTC_Hour_Formats RTC Hour Formats
+/** @defgroup RTC_Hour_Formats_Definitions RTC Hour Formats Definitions
   * @{
   */
 #define RTC_HOURFORMAT_24              0x00000000u
@@ -241,6 +295,20 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   * @}
   */
 
+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions
+  * @{
+  */
+#define RTC_OUTPUT_DISABLE             0x00000000u
+#define RTC_OUTPUT_ALARMA              RTC_CR_OSEL_0
+#define RTC_OUTPUT_ALARMB              RTC_CR_OSEL_1
+#define RTC_OUTPUT_WAKEUP              RTC_CR_OSEL
+#if defined(RTC_CR_TAMPOE)
+#define RTC_OUTPUT_TAMPER              RTC_CR_TAMPOE
+#endif /* RTC_CR_TAMPOE */
+/**
+  * @}
+  */
+
 /** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
   * @{
   */
@@ -253,8 +321,28 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 /** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
   * @{
   */
-#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000u
+#if defined(RTC_CR_TAMPALRM_TYPE)
+#define RTC_OUTPUT_TYPE_PUSHPULL       0x00000000u
+#define RTC_OUTPUT_TYPE_OPENDRAIN      RTC_CR_TAMPALRM_TYPE
+#define RTC_ALARM_OUTPUT_TYPE          RTC_CR_TAMPALRM_TYPE
+#endif /* RTC_CR_TAMPALRM_TYPE */
+
+#if defined(RTC_OR_ALARMOUTTYPE)
 #define RTC_OUTPUT_TYPE_PUSHPULL       RTC_OR_ALARMOUTTYPE
+#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000u
+#define RTC_ALARM_OUTPUT_TYPE          RTC_OR_ALARMOUTTYPE
+#endif /* RTC_OR_ALARMOUTTYPE */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT
+  * @{
+  */
+#if defined(RTC_CR_TAMPALRM_PU)
+#define RTC_OUTPUT_PULLUP_NONE         0x00000000u
+#define RTC_OUTPUT_PULLUP_ON           RTC_CR_TAMPALRM_PU
+#endif /* RTC_CR_TAMPALRM_PU */
 /**
   * @}
   */
@@ -262,8 +350,15 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 /** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap
   * @{
   */
-#define RTC_OUTPUT_REMAP_NONE               0x00000000u
-#define RTC_OUTPUT_REMAP_POS1               RTC_OR_OUT_RMP
+#if defined(RTC_CR_OUT2EN)
+#define RTC_OUTPUT_REMAP_NONE          0x00000000u
+#define RTC_OUTPUT_REMAP_POS1          RTC_CR_OUT2EN
+#endif /* RTC_CR_OUT2EN */
+
+#if defined(RTC_OR_OUT_RMP)
+#define RTC_OUTPUT_REMAP_NONE          0x00000000u
+#define RTC_OUTPUT_REMAP_POS1          RTC_OR_OUT_RMP
+#endif /* RTC_OR_OUT_RMP */
 /**
   * @}
   */
@@ -308,18 +403,19 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 /** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)
   * @{
   */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
+#define RTC_MONTH_JANUARY                   ((uint8_t)0x01)
+#define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02)
+#define RTC_MONTH_MARCH                     ((uint8_t)0x03)
+#define RTC_MONTH_APRIL                     ((uint8_t)0x04)
+#define RTC_MONTH_MAY                       ((uint8_t)0x05)
+#define RTC_MONTH_JUNE                      ((uint8_t)0x06)
+#define RTC_MONTH_JULY                      ((uint8_t)0x07)
+#define RTC_MONTH_AUGUST                    ((uint8_t)0x08)
+#define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09)
+#define RTC_MONTH_OCTOBER                   ((uint8_t)0x10)
+#define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11)
+#define RTC_MONTH_DECEMBER                  ((uint8_t)0x12)
+
 /**
   * @}
   */
@@ -334,6 +430,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 #define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05)
 #define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06)
 #define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07)
+
 /**
   * @}
   */
@@ -343,11 +440,11 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   */
 #define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000u
 #define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   RTC_ALRMAR_WDSEL
+
 /**
   * @}
   */
 
-
 /** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
   * @{
   */
@@ -420,10 +517,6 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 #define RTC_IT_WUT                        RTC_CR_WUTIE        /*!< Enable Wakeup timer Interrupt            */
 #define RTC_IT_ALRA                       RTC_CR_ALRAIE       /*!< Enable Alarm A Interrupt                 */
 #define RTC_IT_ALRB                       RTC_CR_ALRBIE       /*!< Enable Alarm B Interrupt                 */
-#define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE   /*!< Enable all Tamper Interrupt              */
-#define RTC_IT_TAMP1                      RTC_TAMPCR_TAMP1IE  /*!< Enable Tamper 1 Interrupt                */
-#define RTC_IT_TAMP2                      RTC_TAMPCR_TAMP2IE  /*!< Enable Tamper 2 Interrupt                */
-#define RTC_IT_TAMP3                      RTC_TAMPCR_TAMP3IE  /*!< Enable Tamper 3 Interrupt                */
 /**
   * @}
   */
@@ -431,23 +524,122 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 /** @defgroup RTC_Flags_Definitions RTC Flags Definitions
   * @{
   */
+#if defined(RTC_ICSR_RECALPF)
+#define RTC_FLAG_RECALPF                  RTC_ICSR_RECALPF  /*!< Recalibration pending Flag */
+#endif /* RTC_ICSR_RECALPF */
+#if defined(RTC_ICSR_INITF)
+#define RTC_FLAG_INITF                    RTC_ICSR_INITF    /*!< Initialization pending flag */
+#endif /* RTC_ICSR_INITF */
+#if defined(RTC_ICSR_RSF)
+#define RTC_FLAG_RSF                      RTC_ICSR_RSF      /*!< Registers synchronization flag */
+#endif /* RTC_ICSR_RSF */
+#if defined(RTC_ICSR_INITS)
+#define RTC_FLAG_INITS                    RTC_ICSR_INITS    /*!< Initialization status flag */
+#endif /* RTC_ICSR_INITS */
+#if defined(RTC_ICSR_SHPF)
+#define RTC_FLAG_SHPF                     RTC_ICSR_SHPF     /*!< Shift operation pending flag */
+#endif /* RTC_ICSR_SHPF */
+#if defined(RTC_ICSR_WUTWF)
+#define RTC_FLAG_WUTWF                    RTC_ICSR_WUTWF    /*!< Wakeup timer write operation pending flag */
+#endif /* RTC_ICSR_WUTWF */
+#if defined(RTC_ICSR_ALRBWF)
+#define RTC_FLAG_ALRBWF                   RTC_ICSR_ALRBWF   /*!< Alarm B write operation pending flag */
+#endif /* RTC_ICSR_ALRBWF */
+#if defined(RTC_ICSR_ALRAWF)
+#define RTC_FLAG_ALRAWF                   RTC_ICSR_ALRAWF   /*!< Alarm A write operation pending flag */
+#endif /* RTC_ICSR_ALRAWF */
+#if defined(RTC_SR_ITSF)
+#define RTC_FLAG_ITSF                     RTC_SR_ITSF       /*!< Internal Time-stamp flag */
+#endif /* RTC_SR_ITSF */
+#if defined(RTC_SR_TSOVF)
+#define RTC_FLAG_TSOVF                    RTC_SR_TSOVF      /*!< Time-stamp overflow flag */
+#endif /* RTC_SR_TSOVF */
+#if defined(RTC_SR_TSF)
+#define RTC_FLAG_TSF                      RTC_SR_TSF        /*!< Time-stamp flag */
+#endif /* RTC_SR_TSF */
+#if defined(RTC_SR_WUTF)
+#define RTC_FLAG_WUTF                     RTC_SR_WUTF       /*!< Wakeup timer flag */
+#endif /* RTC_SR_WUTF */
+#if defined(RTC_SR_ALRBF)
+#define RTC_FLAG_ALRBF                    RTC_SR_ALRBF      /*!< Alarm B flag */
+#endif /* RTC_SR_ALRBF */
+#if defined(RTC_SR_ALRAF)
+#define RTC_FLAG_ALRAF                    RTC_SR_ALRAF      /*!< Alarm A flag */
+#endif /* RTC_SR_ALRAF */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions
+  * @{
+  */
+#if defined(RTC_SCR_CITSF)
+#define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */
+#endif /* RTC_SCR_CITSF */
+#if defined(RTC_SCR_CTSOVF)
+#define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */
+#endif /* RTC_SCR_CTSOVF */
+#if defined(RTC_SCR_CTSF)
+#define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */
+#endif /* RTC_SCR_CTSF */
+#if defined(RTC_SCR_CWUTF)
+#define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */
+#endif /* RTC_SCR_CWUTF */
+#if defined(RTC_SCR_CALRBF)
+#define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */
+#endif /* RTC_SCR_CALRBF */
+#if defined(RTC_SCR_CALRAF)
+#define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */
+#endif /* RTC_SCR_CALRAF */
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions
+  * @{
+  */
+#if defined(RTC_ISR_RECALPF)
 #define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF
-#define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F
-#define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F
-#define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F
+#endif /* RTC_ISR_RECALPF */
+#if defined(RTC_ISR_TSOVF)
 #define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF
+#endif /* RTC_ISR_TSOVF */
+#if defined(RTC_ISR_TSF)
 #define RTC_FLAG_TSF                      RTC_ISR_TSF
+#endif /* RTC_ISR_TSF */
+#if defined(RTC_ISR_ITSF)
 #define RTC_FLAG_ITSF                     RTC_ISR_ITSF
+#endif /* RTC_ISR_ITSF */
+#if defined(RTC_ISR_WUTF)
 #define RTC_FLAG_WUTF                     RTC_ISR_WUTF
+#endif /* RTC_ISR_WUTF */
+#if defined(RTC_ISR_ALRBF)
 #define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF
+#endif /* RTC_ISR_ALRBF */
+#if defined(RTC_ISR_ALRAF)
 #define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF
+#endif /* RTC_ISR_ALRAF */
+#if defined(RTC_ISR_INITF)
 #define RTC_FLAG_INITF                    RTC_ISR_INITF
+#endif /* RTC_ISR_INITF */
+#if defined(RTC_ISR_RSF)
 #define RTC_FLAG_RSF                      RTC_ISR_RSF
+#endif /* RTC_ISR_RSF */
+#if defined(RTC_ISR_INITS)
 #define RTC_FLAG_INITS                    RTC_ISR_INITS
+#endif /* RTC_ISR_INITS */
+#if defined(RTC_ISR_SHPF)
 #define RTC_FLAG_SHPF                     RTC_ISR_SHPF
+#endif /* RTC_ISR_SHPF */
+#if defined(RTC_ISR_WUTWF)
 #define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF
+#endif /* RTC_ISR_WUTWF */
+#if defined(RTC_ISR_ALRBWF)
 #define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF
+#endif /* RTC_ISR_ALRBWF */
+#if defined(RTC_ISR_ALRAWF)
 #define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF
+#endif /* RTC_ISR_ALRAWF */
 /**
   * @}
   */
@@ -466,10 +658,10 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   * @retval None
   */
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{\
-                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;\
-                                                      (__HANDLE__)->MspInitCallback = NULL;\
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;\
+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{                                              \
+                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;  \
+                                                      (__HANDLE__)->MspInitCallback = NULL;       \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \
                                                      }while(0u)
 #else
 #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
@@ -482,8 +674,8 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   */
 #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)              \
                         do{                                        \
-                            (__HANDLE__)->Instance->WPR = 0xCAu;   \
-                            (__HANDLE__)->Instance->WPR = 0x53u;   \
+                            (__HANDLE__)->Instance->WPR = 0xCAU;   \
+                            (__HANDLE__)->Instance->WPR = 0x53U;   \
                           } while(0u)
 
 /**
@@ -493,9 +685,42 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   */
 #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)               \
                         do{                                        \
-                            (__HANDLE__)->Instance->WPR = 0xFFu;   \
+                            (__HANDLE__)->Instance->WPR = 0xFFU;   \
                           } while(0u)
 
+/**
+  * @brief  Add 1 hour (summer time change).
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __BKP__ Backup
+  *         This parameter can be:
+  *            @arg @ref RTC_STOREOPERATION_RESET
+  *            @arg @ref RTC_STOREOPERATION_SET
+  * @retval None
+  */
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                           \
+                        do {                                                                \
+                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \
+                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);              \
+                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
+                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \
+                        } while(0u);
+
+/**
+  * @brief  Subtract 1 hour (winter time change).
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __BKP__ Backup
+  *         This parameter can be:
+  *            @arg @ref RTC_STOREOPERATION_RESET
+  *            @arg @ref RTC_STOREOPERATION_SET
+  * @retval None
+  */
+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                           \
+                        do {                                                                \
+                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \
+                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);              \
+                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \
+                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \
+                        } while(0u);
 
 /**
   * @brief  Enable the RTC ALARMA peripheral.
@@ -530,8 +755,8 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   * @param  __HANDLE__ specifies the RTC handle.
   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
   *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt
+  *             @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *             @arg @ref RTC_IT_ALRB Alarm B interrupt
   * @retval None
   */
 #define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
@@ -541,8 +766,8 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   * @param  __HANDLE__ specifies the RTC handle.
   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
   *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
   * @retval None
   */
 #define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
@@ -552,70 +777,111 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
   * @param  __HANDLE__ specifies the RTC handle.
   * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
   *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
   * @retval None
   */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__)            (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 4)) != 0u) ? 1u : 0u)
+#if defined(RTC_MISR_ALRAMF)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)
+#endif /* RTC_MISR_ALRAMF */
+#if defined(RTC_ISR_ALRAF)
+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U)
+#endif /* RTC_ISR_ALRAF */
 
+/**
+  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.
+  * @param  __HANDLE__ specifies the RTC handle.
+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt
+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt
+  * @retval None
+  */
+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
+
+#if defined(RTC_SR_ALRAF)
 /**
   * @brief  Get the selected RTC Alarm's flag status.
   * @param  __HANDLE__ specifies the RTC handle.
   * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
   *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF
-  *            @arg RTC_FLAG_ALRBWF
+  *            @arg @ref RTC_FLAG_ALRAF
+  *            @arg @ref RTC_FLAG_ALRBF
   * @retval None
   */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0u) ? 1u : 0u)
-
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)
+#endif /* RTC_SR_ALRAF */
+#if defined(RTC_ISR_ALRAF)
 /**
-  * @brief  Clear the RTC Alarm's pending flags.
+  * @brief  Get the selected RTC Alarm's flag status.
   * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
-  *          This parameter can be:
-  *             @arg RTC_FLAG_ALRAF
-  *             @arg RTC_FLAG_ALRBF
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.
+  *         This parameter can be:
+  *            @arg @ref RTC_FLAG_ALRAF
+  *            @arg @ref RTC_FLAG_ALRBF
+  *            @arg @ref RTC_FLAG_ALRAWF
+  *            @arg @ref RTC_FLAG_ALRBWF
   * @retval None
   */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
+#endif /* RTC_ISR_ALRAF */
 
 /**
-  * @brief  Check whether the specified RTC Alarm interrupt is enabled or not.
+  * @brief  Clear the RTC Alarm's pending flags.
   * @param  __HANDLE__ specifies the RTC handle.
-  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt
+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.
+  *          This parameter can be:
+  *             @arg @ref RTC_FLAG_ALRAF
+  *             @arg @ref RTC_FLAG_ALRBF
   * @retval None
   */
-#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0u) ? 1u : 0u)
+#if defined(RTC_SCR_CALRAF)
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->SCR |= __FLAG__)
+#endif /* RTC_SCR_CALRAF */
+#if defined(RTC_ISR_ALRAF)
+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))
+#endif /* RTC_ISR_ALRAF */
+
 
 /**
   * @brief  Enable interrupt on the RTC Alarm associated Exti line.
   * @retval None
   */
+#if defined(EXTI_D1)
 #define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+#else  /* EXTI */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1    |= RTC_EXTI_LINE_ALARM_EVENT)
+#endif /* EXTI_D1 */
 
 /**
   * @brief  Disable interrupt on the RTC Alarm associated Exti line.
   * @retval None
   */
+#if defined(EXTI_D1)
 #define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#else  /* EXTI */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1    &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#endif /* EXTI_D1 */
 
 /**
   * @brief  Enable event on the RTC Alarm associated Exti line.
   * @retval None.
   */
+#if defined(EXTI_D1)
 #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)
+#else  /* EXTI */
+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1    |= RTC_EXTI_LINE_ALARM_EVENT)
+#endif /* EXTI_D1 */
 
 /**
   * @brief  Disable event on the RTC Alarm associated Exti line.
   * @retval None.
   */
+#if defined(EXTI_D1)
 #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#else  /* EXTI */
+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1    &= ~(RTC_EXTI_LINE_ALARM_EVENT))
+#endif /* EXTI_D1 */
 
 #if defined(DUAL_CORE)
 /**
@@ -675,6 +941,7 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
                                                              __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \
                                                              __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \
                                                            } while(0u)
+
 /**
   * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.
   * @retval None
@@ -683,17 +950,26 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
                                                              __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \
                                                              __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \
                                                            } while(0u)
+
 /**
   * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.
   * @retval Line Status.
   */
+#if defined(EXTI_D1)
 #define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)
+#else  /* EXTI */
+#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1    & RTC_EXTI_LINE_ALARM_EVENT)
+#endif /* EXTI_D1 */
 
 /**
   * @brief Clear the RTC Alarm associated Exti line flag.
   * @retval None.
   */
+#if defined(EXTI_D1)
 #define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))
+#else  /* EXTI */
+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1    = (RTC_EXTI_LINE_ALARM_EVENT))
+#endif /* EXTI_D1 */
 
 #if defined(DUAL_CORE)
 /**
@@ -722,16 +998,17 @@ typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef * hrtc); /*!< pointer to
 #include "stm32h7xx_hal_rtc_ex.h"
 
 /* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
+/** @defgroup RTC_Exported_Functions RTC Exported Functions
   * @{
   */
 
-/** @addtogroup RTC_Exported_Functions_Group1
+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
 /* Initialization and de-initialization functions  ****************************/
 HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
 HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
+
 void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
 void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
 
@@ -739,12 +1016,12 @@ void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
 #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)
 HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);
-#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */
+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */
 /**
   * @}
   */
 
-/** @addtogroup RTC_Exported_Functions_Group2
+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
   * @{
   */
 /* RTC Time and Date functions ************************************************/
@@ -756,7 +1033,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
   * @}
   */
 
-/** @addtogroup RTC_Exported_Functions_Group3
+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
   * @{
   */
 /* RTC Alarm functions ********************************************************/
@@ -765,27 +1042,26 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef
 HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
 HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
 void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
 void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
 /**
   * @}
   */
 
-/** @addtogroup RTC_Exported_Functions_Group4
+/** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions
   * @{
   */
 /* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);
 /**
   * @}
   */
 
-/** @addtogroup RTC_Exported_Functions_Group5
+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions
   * @{
   */
 /* Peripheral State functions *************************************************/
 HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-
 /**
   * @}
   */
@@ -810,7 +1086,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
                                  RTC_DR_DU)
 
 #define RTC_INIT_MASK           0xFFFFFFFFu
-#define RTC_RSF_MASK            (~(RTC_ISR_INIT | RTC_ISR_RSF))
+
+#if defined(RTC_ICSR_INIT) && defined(RTC_ICSR_RSF)
+#define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))
+#endif /* RTC_ICSR_INIT && RTC_ICSR_RSF */
+
+#if defined(RTC_ISR_INIT) && defined(RTC_ISR_RSF)
+#define RTC_RSF_MASK                        (~(RTC_ISR_INIT | RTC_ISR_RSF))
+#endif /* RTC_ISR_INIT && RTC_ISR_RSF */
 
 #define RTC_TIMEOUT_VALUE  1000u
 
@@ -829,6 +1112,19 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   * @{
   */
 
+#if defined(RTC_CR_TAMPOE)
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP)      || \
+                               ((OUTPUT) == RTC_OUTPUT_TAMPER))
+#else  /* RTC_CR_TAMPOE not defined */
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \
+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \
+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
+#endif /* RTC_CR_TAMPOE */
+
 #define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
                                         ((FORMAT) == RTC_HOURFORMAT_24))
 
@@ -838,10 +1134,16 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 #define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
                                   ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
 
+#if defined(RTC_CR_TAMPALRM_PU)
+#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \
+                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))
+#endif /* RTC_CR_TAMPALRM_PU */
+
 #define IS_RTC_OUTPUT_REMAP(REMAP)     (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \
                                         ((REMAP) == RTC_OUTPUT_REMAP_POS1))
 
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
+#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \
+                                  ((PM) == RTC_HOURFORMAT12_PM))
 
 #define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
                                       ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
@@ -850,13 +1152,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 #define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
                                            ((OPERATION) == RTC_STOREOPERATION_SET))
 
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || ((FORMAT) == RTC_FORMAT_BCD))
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \
+                               ((FORMAT) == RTC_FORMAT_BCD))
 
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99u)
+#define IS_RTC_YEAR(YEAR)              ((YEAR)   <= 99u)
 
 #define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1u) && ((MONTH) <= 12u))
 
-#define IS_RTC_DATE(DATE)              (((DATE) >= 1u) && ((DATE) <= 31u))
+#define IS_RTC_DATE(DATE)              (((DATE)  >= 1u) && ((DATE)  <= 31u))
 
 #define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
                                  ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
@@ -879,36 +1182,23 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
 #define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
                                             ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
 
-#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & (~RTC_ALARMMASK_ALL)) == 0u)
+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0u)
 
-#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
+#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \
+                                  ((ALARM) == RTC_ALARM_B))
 
 #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)
 
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL)    || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14)    || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)          (((MASK) == 0u) || \
+                                                    (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))
 
 #define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))
 
 #define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))
 
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0u) && ((HOUR) <= 12u))
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) >  0u) && ((HOUR) <= 12u))
 
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23u)
+#define IS_RTC_HOUR24(HOUR)            ((HOUR)    <= 23u)
 
 #define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59u)
 
@@ -922,12 +1212,11 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
   * @}
   */
 
-/* Private functions ---------------------------------------------------------*/
-/** @addtogroup RTC_Private_Functions
+/* Private functions -------------------------------------------------------------*/
+/** @defgroup RTC_Private_Functions RTC Private Functions
   * @{
   */
-
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);
 uint8_t            RTC_ByteToBcd2(uint8_t Value);
 uint8_t            RTC_Bcd2ToByte(uint8_t Value);
 

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sai.h

@@ -436,12 +436,18 @@ typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);
 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization
   * @{
   */
-#define SAI_ASYNCHRONOUS              0U /*!< Asynchronous */
-#define SAI_SYNCHRONOUS               1U /*!< Synchronous with other block of same SAI */
-#define SAI_SYNCHRONOUS_EXT_SAI1      2U /*!< Synchronous with other SAI, SAI1 */
-#define SAI_SYNCHRONOUS_EXT_SAI2      3U /*!< Synchronous with other SAI, SAI2 */
-#define SAI_SYNCHRONOUS_EXT_SAI3      4U /*!< Synchronous with other SAI, SAI3 */
-#define SAI_SYNCHRONOUS_EXT_SAI4      5U /*!< Synchronous with other SAI, SAI4 */
+#define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */
+#define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */
+#define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1 */
+#if defined(SAI2)
+#define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2 */
+#endif /* SAI2 */
+#if defined(SAI3)
+#define SAI_SYNCHRONOUS_EXT_SAI3          4U /*!< Synchronous with other SAI, SAI3 */
+#endif /* SAI3 */
+#if defined(SAI4)
+#define SAI_SYNCHRONOUS_EXT_SAI4          5U /*!< Synchronous with other SAI, SAI4 */
+#endif /* SAI4 */
 /**
   * @}
   */
@@ -871,13 +877,24 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
 
 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \
                                             ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))
-
-#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)         || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS)          || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2) || \
-                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3) || \
+#if defined(SAI2) && defined(SAI3) && defined(SAI4)
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
+#elif defined(SAI2)
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))
+#else
+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \
+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \
                                        ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))
+#endif
 
 #define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \
                                         ((VALUE) == SAI_MCK_OUTPUT_DISABLE))

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd.h

@@ -66,7 +66,7 @@ typedef enum
 /** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure
   * @{
   */
-typedef uint32_t HAL_SD_CardStateTypedef;
+typedef uint32_t HAL_SD_CardStateTypeDef;
 
 #define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */
 #define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */
@@ -98,7 +98,7 @@ typedef struct
 
   uint32_t Class;                        /*!< Specifies the class of the card class           */
 
-  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address            */
+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */
 
   uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */
 
@@ -123,23 +123,23 @@ typedef struct
 {
   SD_TypeDef                   *Instance;        /*!< SD registers base address           */
 
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
+  SD_InitTypeDef               Init;             /*!< SD required parameters              */
 
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */
 
-  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer              */
+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */
 
-  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                           */
+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */
 
-  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer              */
+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */
 
-  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                           */
+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */
 
-  __IO uint32_t                Context;          /*!< SD transfer context                           */
+  __IO uint32_t                Context;          /*!< SD transfer context                 */
 
-  __IO HAL_SD_StateTypeDef     State;           /*!< SD card State                                   */
+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */
 
-  __IO uint32_t                ErrorCode;       /*!< SD Card Error codes                              */
+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */
 
   HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */
 
@@ -212,7 +212,7 @@ typedef struct
   __IO uint8_t  ECC;                  /*!< ECC code                              */
   __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
   __IO uint8_t  Reserved4;            /*!< Always 1                              */
-}HAL_SD_CardCSDTypedef;
+}HAL_SD_CardCSDTypeDef;
 /**
   * @}
   */
@@ -233,7 +233,7 @@ typedef struct
   __IO uint8_t  CID_CRC;         /*!< CID CRC               */
   __IO uint8_t  Reserved2;       /*!< Always 1              */
 
-}HAL_SD_CardCIDTypedef;
+}HAL_SD_CardCIDTypeDef;
 /**
   * @}
   */
@@ -256,7 +256,7 @@ typedef struct
   __IO uint8_t  UhsSpeedGrade;          /*!< Carries information about the speed grade of UHS card      */
   __IO uint8_t  UhsAllocationUnitSize;  /*!< Carries information about the UHS card's allocation unit size  */
   __IO uint8_t  VideoSpeedClass;        /*!< Carries information about the Video Speed Class of UHS card    */
-}HAL_SD_CardStatusTypedef;
+}HAL_SD_CardStatusTypeDef;
 /**
   * @}
   */
@@ -373,7 +373,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 #define CARD_NORMAL_SPEED        ((uint32_t)0x00000000U)    /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01    */
 #define CARD_HIGH_SPEED          ((uint32_t)0x00000100U)    /*!< High Speed Card <25Mo/s , Spec version 2.00        */
 #define CARD_ULTRA_HIGH_SPEED    ((uint32_t)0x00000200U)    /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards
-                                                                and <104Mo/s for SDR104, Spec version 3.01          */
+                                                                 and <104Mo/s for SDR104, Spec version 3.01          */
 
 #define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */
 #define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */
@@ -402,7 +402,7 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
  * @{
  */
 /** @brief Reset SD handle state.
-  * @param  __HANDLE__ : SD handle.
+  * @param  __HANDLE__ SD Handle.
   * @retval None
   */
 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -417,8 +417,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 
 /**
   * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.
   *         This parameter can be one or a combination of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -449,8 +449,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 
 /**
   * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -481,8 +481,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 
 /**
   * @brief  Check whether the specified SD flag is set or not.
-  * @param  __HANDLE__: SD Handle
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be one of the following values:
   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
@@ -496,8 +496,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
   *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold
   *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)
   *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12
-  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
   *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active
+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active
   *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty
   *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full
   *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full
@@ -519,8 +519,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 
 /**
   * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)
   *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)
@@ -548,8 +548,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 
 /**
   * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the SDMMC interrupt source to check.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -563,22 +563,16 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
   *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt
   *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt
   *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt
-  *            @arg SDMMC_IT_DPSMACT:    Data path state machine active interrupt
-  *            @arg SDMMC_IT_CPSMACT:    Command path state machine active interrupt
   *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt
   *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt
-  *            @arg SDMMC_IT_TXFIFOF:    Transmit FIFO full interrupt
   *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt
   *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt
-  *            @arg SDMMC_IT_RXFIFOE:    Receive FIFO empty interrupt
-  *            @arg SDMMC_IT_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)
   *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt
   *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt
   *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt
   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
-  *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
   * @retval The new state of SD IT (SET or RESET).
   */
@@ -586,8 +580,8 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 
 /**
   * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__: SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __HANDLE__ SD Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *          This parameter can be one or a combination of the following values:
   *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt
   *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt
@@ -607,7 +601,6 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
   *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt
   *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt
   *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt
-  *            @arg SDMMC_IT_IDMATE:     IDMA transfer error interrupt
   *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt
   * @retval None
   */
@@ -628,11 +621,11 @@ typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);
 /** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions
   * @{
   */
-HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Init     (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_DeInit   (SD_HandleTypeDef *hsd);
+void              HAL_SD_MspInit  (SD_HandleTypeDef *hsd);
+void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
 /**
   * @}
   */
@@ -641,27 +634,27 @@ void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
   * @{
   */
 /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+HAL_StatusTypeDef HAL_SD_ReadBlocks     (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_WriteBlocks    (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SD_Erase          (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
 /* Non-Blocking mode: IT */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
-HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT  (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
 /* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
 HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
 
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
+void              HAL_SD_IRQHandler     (SD_HandleTypeDef *hsd);
 
 /* Callback in non blocking modes (DMA) */
-void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd);
+void              HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd);
+void              HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);
+void              HAL_SD_ErrorCallback  (SD_HandleTypeDef *hsd);
+void              HAL_SD_AbortCallback  (SD_HandleTypeDef *hsd);
 
 #if (USE_SD_TRANSCEIVER != 0U)
 /* Callback to switch in 1.8V mode */
-void HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
+void              HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);
 #endif /* USE_SD_TRANSCEIVER */
 
 #if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)
@@ -691,11 +684,11 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t
 /** @defgroup SD_Exported_Functions_Group4 SD card related functions
   * @{
   */
-HAL_SD_CardStateTypedef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
-HAL_StatusTypeDef       HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypedef *pCID);
-HAL_StatusTypeDef       HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypedef *pCSD);
-HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pStatus);
-HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef       HAL_SD_GetCardCID   (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef       HAL_SD_GetCardCSD   (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);
+HAL_StatusTypeDef       HAL_SD_GetCardInfo  (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);
 /**
   * @}
   */
@@ -704,7 +697,7 @@ HAL_StatusTypeDef       HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInf
   * @{
   */
 HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);
-uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
+uint32_t            HAL_SD_GetError(SD_HandleTypeDef *hsd);
 /**
   * @}
   */
@@ -712,7 +705,7 @@ uint32_t HAL_SD_GetError(SD_HandleTypeDef *hsd);
 /** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management
   * @{
   */
-HAL_StatusTypeDef HAL_SD_Abort(SD_HandleTypeDef *hsd);
+HAL_StatusTypeDef HAL_SD_Abort   (SD_HandleTypeDef *hsd);
 HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sd_ex.h

@@ -75,10 +75,10 @@ HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint3
 HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);
 HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);
 
-void HAL_SDEx_Read_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SDEx_Read_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SDEx_Write_DMADoubleBuffer0CpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);
+void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);
 
 /**
   * @}
@@ -108,6 +108,6 @@ void HAL_SDEx_Write_DMADoubleBuffer1CpltCallback(SD_HandleTypeDef *hsd);
 #endif
 
 
-#endif /* stm32h7xx_HAL_SDEx_H */
+#endif /* stm32h7xx_HAL_SD_EX_H */
 
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sdram.h

@@ -6,7 +6,8 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard.h

@@ -442,7 +442,7 @@ typedef enum
   * @}
   */
 
-/** @defgroup SMARTCARD_ClockPrescaler  Clock Prescaler
+/** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler
   * @{
   */
 #define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
@@ -560,15 +560,15 @@ typedef enum
   */
 #if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1
 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
-                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
-                                                           (__HANDLE__)->MspInitCallback = NULL;                  \
-                                                           (__HANDLE__)->MspDeInitCallback = NULL;                \
+                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
+                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
+                                                            (__HANDLE__)->MspInitCallback = NULL;                 \
+                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \
                                                           } while(0U)
 #else
 #define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \
-                                                           (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;      \
-                                                           (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;     \
+                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \
+                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \
                                                           } while(0U)
 #endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */
 
@@ -576,11 +576,11 @@ typedef enum
   * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                        \
-    do{                                                                     \
-      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
-      SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
-      } while(0U)
+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \
+  do{                                                                     \
+    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \
+  } while(0U)
 
 /** @brief  Clear the specified SMARTCARD pending flag.
   * @param  __HANDLE__ specifies the SMARTCARD Handle.
@@ -729,7 +729,8 @@ typedef enum
   *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                             & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)
 
 /** @brief  Check whether the specified SmartCard interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the SMARTCARD Handle.
@@ -753,8 +754,8 @@ typedef enum
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
 #define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \
-                                                                    (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
-                                                                    (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)
+                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \
+                                                                      (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)
 
 /** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
   * @param  __HANDLE__ specifies the SMARTCARD Handle.
@@ -795,7 +796,8 @@ typedef enum
   * @param  __HANDLE__ specifies the SMARTCARD Handle.
   * @retval None
   */
-#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\
+                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable the USART associated to the SMARTCARD Handle.
   * @param  __HANDLE__ specifies the SMARTCARD Handle.
@@ -823,12 +825,156 @@ typedef enum
   * @param  __CLOCKSOURCE__ output variable.
   * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.
   */
+#if defined(UART9) && defined(USART10)
+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
+  do {                                                         \
+    if ((__HANDLE__)->Instance == USART1)                      \
+    {                                                          \
+      switch (__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                        \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if ((__HANDLE__)->Instance == USART2)                 \
+    {                                                          \
+      switch (__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                        \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if ((__HANDLE__)->Instance == USART3)                 \
+    {                                                          \
+      switch (__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                        \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if ((__HANDLE__)->Instance == USART6)                 \
+    {                                                          \
+      switch (__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                        \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if ((__HANDLE__)->Instance == USART10)                \
+    {                                                          \
+      switch (__HAL_RCC_GET_USART10_SOURCE())                  \
+      {                                                        \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else                                                       \
+    {                                                          \
+      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
+    }                                                          \
+  } while(0U)
+#else
 #define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \
   do {                                                         \
     if ((__HANDLE__)->Instance == USART1)                      \
     {                                                          \
-       switch (__HAL_RCC_GET_USART1_SOURCE())                  \
-       {                                                       \
+      switch (__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                        \
         case RCC_USART1CLKSOURCE_D2PCLK2:                      \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
           break;                                               \
@@ -850,17 +996,17 @@ typedef enum
         default:                                               \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
           break;                                               \
-       }                                                       \
+      }                                                        \
     }                                                          \
     else if ((__HANDLE__)->Instance == USART2)                 \
     {                                                          \
-       switch (__HAL_RCC_GET_USART2_SOURCE())                  \
-       {                                                       \
+      switch (__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                        \
         case RCC_USART2CLKSOURCE_D2PCLK1:                      \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
           break;                                               \
         case RCC_USART2CLKSOURCE_PLL2:                         \
-           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;    \
+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;    \
           break;                                               \
         case RCC_USART2CLKSOURCE_PLL3:                         \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \
@@ -877,12 +1023,12 @@ typedef enum
         default:                                               \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
           break;                                               \
-       }                                                       \
+      }                                                        \
     }                                                          \
     else if ((__HANDLE__)->Instance == USART3)                 \
     {                                                          \
-       switch (__HAL_RCC_GET_USART3_SOURCE())                  \
-       {                                                       \
+      switch (__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                        \
         case RCC_USART3CLKSOURCE_D2PCLK1:                      \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \
           break;                                               \
@@ -904,12 +1050,12 @@ typedef enum
         default:                                               \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
           break;                                               \
-       }                                                       \
+      }                                                        \
     }                                                          \
     else if ((__HANDLE__)->Instance == USART6)                 \
     {                                                          \
-       switch (__HAL_RCC_GET_USART6_SOURCE())                  \
-       {                                                       \
+      switch (__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                        \
         case RCC_USART6CLKSOURCE_D2PCLK2:                      \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \
           break;                                               \
@@ -931,13 +1077,14 @@ typedef enum
         default:                                               \
           (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \
           break;                                               \
-       }                                                       \
+      }                                                        \
     }                                                          \
     else                                                       \
     {                                                          \
       (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \
     }                                                          \
   } while(0U)
+#endif /* UART9 && USART10 */
 
 /** @brief  Check the Baud rate range.
   * @note   The maximum Baud Rate is derived from the maximum clock on H7 (100 MHz)
@@ -998,7 +1145,8 @@ typedef enum
   * @param __CPOL__ SMARTCARD frame polarity.
   * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)
   */
-#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW) || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\
+                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))
 
 /** @brief Ensure that SMARTCARD frame phase is valid.
   * @param __CPHA__ SMARTCARD frame phase.
@@ -1038,18 +1186,18 @@ typedef enum
   * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.
   * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
   */
-#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1) || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
-              ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
+#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \
+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))
 
 /** @brief Ensure that SMARTCARD advanced features initialization is valid.
   * @param __INIT__ SMARTCARD advanced features initialization.
@@ -1144,8 +1292,10 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);
 
 #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)
 /* Callbacks Register/UnRegister functions  ***********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
-HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,
+                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */
 
 /**
@@ -1157,8 +1307,10 @@ HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsma
   * @{
   */
 
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+                                         uint32_t Timeout);
+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,
+                                        uint32_t Timeout);
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);
 HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_smartcard_ex.h

@@ -68,7 +68,7 @@ extern "C" {
   * @}
   */
 
-/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARDEx FIFO mode
+/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode
   * @brief    SMARTCARD FIFO mode
   * @{
   */
@@ -78,7 +78,7 @@ extern "C" {
   * @}
   */
 
-/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARDEx TXFIFO threshold level
+/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level
   * @brief    SMARTCARD TXFIFO level
   * @{
   */
@@ -92,7 +92,7 @@ extern "C" {
   * @}
   */
 
-/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARDEx RXFIFO threshold level
+/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level
   * @brief    SMARTCARD RXFIFO level
   * @{
   */
@@ -207,7 +207,7 @@ extern "C" {
   do {                                                                                                       \
     if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \
     {                                                                                                        \
-     (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                       \
+      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \
     }                                                                                                        \
     else                                                                                                     \
     {                                                                                                        \
@@ -238,29 +238,29 @@ extern "C" {
   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
   */
 #define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \
-                                         ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
+                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))
 
 /** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.
   * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.
   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
   */
 #define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \
-                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))
 
 /** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.
   * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.
   * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
   */
 #define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \
-                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8)             || \
-                                          ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \
+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_spi.h

@@ -1059,7 +1059,7 @@ uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
                                                     ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \
                                                     ((LENGTH) == SPI_CRC_LENGTH_4BIT))
 
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)          (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFFFFF))
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)           ((POLYNOMIAL) >= 0x1UL)
 
 #define IS_SPI_UNDERRUN_DETECTION(MODE)            (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \
                                                     ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_sram.h

@@ -6,7 +6,8 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * All rights reserved.</center></h2>
   *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim.h

@@ -167,7 +167,7 @@ typedef struct
                                This parameter can be a value of @ref TIM_Encoder_Mode */
 
   uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
 
   uint32_t IC1Selection;  /*!< Specifies the input.
                                This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -179,7 +179,7 @@ typedef struct
                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
 
   uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
 
   uint32_t IC2Selection;  /*!< Specifies the input.
                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
@@ -235,7 +235,12 @@ typedef struct
   uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection
                                         This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
   uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection
-                                        This parameter can be a value of @ref TIM_Master_Slave_Mode */
+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode
+                                        @note When the Master/slave mode is enabled, the effect of
+                                        an event on the trigger input (TRGI) is delayed to allow a
+                                        perfect synchronization between the current timer and its
+                                        slaves (through TRGO). It is not mandatory in case of timer
+                                        synchronization mode. */
 } TIM_MasterConfigTypeDef;
 
 /**
@@ -455,7 +460,7 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 #define TIM_DMABASE_AF1                    0x00000018U
 #define TIM_DMABASE_AF2                    0x00000019U
 #endif /* TIM_BREAK_INPUT_SUPPORT */
-#define TIM_DMABASE_TISEL                  0x00000020U
+#define TIM_DMABASE_TISEL                  0x0000001AU
 /**
   * @}
   */
@@ -518,6 +523,15 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @}
   */
 
+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap
+  * @{
+  */
+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */
+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */
+/**
+  * @}
+  */
+
 /** @defgroup TIM_ClockDivision TIM Clock Division
   * @{
   */
@@ -611,6 +625,15 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   * @}
   */
 
+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
+  * @{
+  */
+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */
+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */
+/**
+  * @}
+  */
+
 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
   * @{
   */
@@ -975,6 +998,11 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
 #define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */
 #define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */
 #define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */
+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */
+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */
+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */
+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */
+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */
 #define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */
 /**
   * @}
@@ -1308,6 +1336,31 @@ typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to
   */
 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
 
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @param  __HANDLE__ TIM handle.
+  * @retval None
+mode.
+  */
+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))
+
+/**
+  * @brief  Get update interrupt flag (UIF) copy status.
+  * @param  __COUNTER__ Counter value.
+  * @retval The state of UIFCPY (TRUE or FALSE).
+mode.
+  */
+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))
+
 /**
   * @brief  Indicates whether or not the TIM Counter is used as downcounter.
   * @param  __HANDLE__ TIM handle.
@@ -1327,6 +1380,8 @@ mode.
 
 /**
   * @brief  Set the TIM Counter Register value on runtime.
+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.
+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.
   * @param  __HANDLE__ TIM handle.
   * @param  __COUNTER__ specifies the Counter register new value.
   * @retval None
@@ -1508,12 +1563,62 @@ mode.
   * @retval None
   */
 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\
-   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\
-   ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE))
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
+
+/**
+  * @brief  Enable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is enabled an active edge on the trigger input acts
+  *        like a compare match on CCx output. Delay to sample the trigger
+  *        input and to activate CCx output is reduced to 3 clock cycles.
+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @retval None
+  */
+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
+
+/**
+  * @brief  Disable fast mode for a given channel.
+  * @param  __HANDLE__ TIM handle.
+  * @param  __CHANNEL__ TIM Channels to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
+  * @note  When fast mode is disabled CCx output behaves normally depending
+  *        on counter and CCRx values even when the trigger is ON. The minimum
+  *        delay to activate CCx output when an active edge occurs on the
+  *        trigger input is 5 clock cycles.
+  * @retval None
+  */
+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
 
 /**
   * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@@ -1618,6 +1723,9 @@ mode.
                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
                                             ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
 
+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \
+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))
+
 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
                                             ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
@@ -1640,6 +1748,9 @@ mode.
 #define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
                                             ((__STATE__) == TIM_OCNIDLESTATE_RESET))
 
+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \
+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
+
 #define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \
                                             ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \
                                             ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@@ -1807,7 +1918,9 @@ mode.
                                                  ((__SELECTION__) == TIM_TS_ITR5) || \
                                                  ((__SELECTION__) == TIM_TS_ITR6) || \
                                                  ((__SELECTION__) == TIM_TS_ITR7) || \
-                                                 ((__SELECTION__) == TIM_TS_ITR8))
+                                                 ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                 ((__SELECTION__) == TIM_TS_ITR13))
 
 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
                                                                ((__SELECTION__) == TIM_TS_ITR1) || \
@@ -1818,6 +1931,8 @@ mode.
                                                                ((__SELECTION__) == TIM_TS_ITR6) || \
                                                                ((__SELECTION__) == TIM_TS_ITR7) || \
                                                                ((__SELECTION__) == TIM_TS_ITR8) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR12) || \
+                                                               ((__SELECTION__) == TIM_TS_ITR13) || \
                                                                ((__SELECTION__) == TIM_TS_NONE))
 
 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
@@ -1876,10 +1991,10 @@ mode.
    ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
 
 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
-   ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
 
 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
   (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
@@ -1888,10 +2003,10 @@ mode.
    ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
 
 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
-   ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_tim_ex.h

@@ -103,9 +103,9 @@ TIMEx_BreakInputConfigTypeDef;
 #define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */
 #define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */
 #define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */
-#define TIM_TIM8_ETR_ADC1_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC1 AWD1 */
-#define TIM_TIM8_ETR_ADC1_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC1 AWD2 */
-#define TIM_TIM8_ETR_ADC1_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC1 AWD3 */
+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */
+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */
+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */
 #define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */
 #define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */
 #define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */
@@ -123,6 +123,18 @@ TIMEx_BreakInputConfigTypeDef;
 #define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */
 #define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */
 #define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */
+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */
+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */
+
+#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */
+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */
+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */
+
+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */
+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */
+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */
+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */
+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */
 /**
   * @}
   */
@@ -184,19 +196,22 @@ TIMEx_BreakInputConfigTypeDef;
 #define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */
 #define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */
 #define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */
-#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP2 OUT OR COMP2 OUT */
+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */
 
 #define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */
 #define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */
 #define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */
 
+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */
+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */
+
 #define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */
 #define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */
 #define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */
 #define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */
-#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_3)                      /* !< TIM15_TI1 is connected to RCC LSE  */
-#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
-#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */
+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */
+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */
 
 #define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */
 #define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */
@@ -209,9 +224,19 @@ TIMEx_BreakInputConfigTypeDef;
 #define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */
 
 #define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */
-#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to RCC LSI  */
-#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC LSE  */
+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */
+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */
 #define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */
+
+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */
+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */
+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */
+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */
+
+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */
+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */
+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */
+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */
 /**
   * @}
   */
@@ -264,6 +289,8 @@ TIMEx_BreakInputConfigTypeDef;
                                   ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\
                                   ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\
                                   ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\
+                                  ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\
                                   ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\
                                   ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\
                                   ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\
@@ -282,7 +309,15 @@ TIMEx_BreakInputConfigTypeDef;
                                   ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\
                                   ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\
                                   ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\
-                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1))
+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\
+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\
+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))
 
 #define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\
                                       ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\
@@ -294,9 +329,9 @@ TIMEx_BreakInputConfigTypeDef;
                                       ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\
                                       ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\
                                       ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\
-                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD1) ||\
-                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD2) ||\
-                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC1_AWD3) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\
+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\
                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\
                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\
                                       ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\
@@ -312,8 +347,15 @@ TIMEx_BreakInputConfigTypeDef;
                                       ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\
                                       ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\
                                       ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\
-                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB))
-
+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\
+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\
+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))
 
 /**
   * @}

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart.h

@@ -133,8 +133,6 @@ typedef struct
                                        This parameter can be a value of @ref UART_MSB_First. */
 } UART_AdvFeatureInitTypeDef;
 
-
-
 /**
   * @brief HAL UART State definition
   * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).
@@ -190,7 +188,6 @@ typedef enum
   UART_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source           */
   UART_CLOCKSOURCE_LSE        = 0x40U,    /*!< LSE clock source           */
   UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */
-
 } UART_ClockSourceTypeDef;
 
 /**
@@ -225,9 +222,9 @@ typedef struct __UART_HandleTypeDef
 
   uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
 
-  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler   */
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
 
-  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler   */
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
 
   DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
 
@@ -335,8 +332,10 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 #define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */
 #define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */
 #define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */
+#define  HAL_UART_ERROR_RTO              ((uint32_t)0x00000020U)    /*!< Receiver Timeout error  */
+
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */
+#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error  */
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 /**
   * @}
@@ -441,11 +440,11 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   * @}
   */
 
-/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
   * @{
   */
-#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                 /*!< UART receiver timeout disable */
-#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN             /*!< UART receiver timeout enable  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
 /**
   * @}
   */
@@ -699,6 +698,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 #define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
 #define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
 #define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
 #define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
 #define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
 #define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
@@ -749,6 +749,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 #define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */
 #define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */
 #define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU                  /*!< UART receiver timeout interruption             */
 
 #define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */
 
@@ -773,6 +774,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
 #define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
 #define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
 #define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
 /**
   * @}
   */
@@ -811,9 +813,9 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   */
 #define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
   do{                \
-      SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
-      SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
-    }  while(0U)
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
 
 /** @brief  Clear the specified UART pending flag.
   * @param  __HANDLE__ specifies the UART Handle.
@@ -826,6 +828,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
   *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
   *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
   *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
   *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
   *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
@@ -894,6 +897,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_FLAG_TC    Transmission Complete flag
   *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
   *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
   *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
   *            @arg @ref UART_FLAG_ORE   Overrun Error flag
   *            @arg @ref UART_FLAG_NE    Noise Error flag
@@ -920,6 +924,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_IT_TC    Transmission complete interrupt
   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
   *            @arg @ref UART_IT_PE    Parity Error interrupt
   *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
@@ -947,6 +952,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_IT_TC    Transmission complete interrupt
   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
   *            @arg @ref UART_IT_PE    Parity Error interrupt
   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
@@ -973,12 +979,14 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_IT_TC    Transmission complete interrupt
   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
   *            @arg @ref UART_IT_PE    Parity Error interrupt
   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
 
 /** @brief  Check whether the specified UART interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the UART Handle.
@@ -997,14 +1005,15 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_IT_TC    Transmission complete interrupt
   *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
   *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
   *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
   *            @arg @ref UART_IT_PE    Parity Error interrupt
   *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
 #define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \
-                                                               (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
-                                                               (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)
 
 /** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
   * @param  __HANDLE__ specifies the UART Handle.
@@ -1016,6 +1025,7 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
   *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
   *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
   *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
   *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
   *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
@@ -1166,7 +1176,8 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   * @param  __CLOCKPRESCALER__ UART prescaler value.
   * @retval Division result
   */
-#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U) + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\
+                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))
 
 /** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
   * @param  __PCLK__ UART clock.
@@ -1174,7 +1185,8 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   * @param  __CLOCKPRESCALER__ UART prescaler value.
   * @retval Division result
   */
-#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))
 
 /** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
   * @param  __PCLK__ UART clock.
@@ -1182,7 +1194,8 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   * @param  __CLOCKPRESCALER__ UART prescaler value.
   * @retval Division result
   */
-#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__))) + ((__BAUD__)/2U)) / (__BAUD__))
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\
+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))
 
 /** @brief  Check whether or not UART instance is Low Power UART.
   * @param  __HANDLE__ specifies the UART Handle.
@@ -1243,10 +1256,10 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
   */
 #define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
-                                   (((__CONTROL__) == UART_HWCONTROL_NONE) || \
-                                    ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
-                                    ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
-                                    ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
 
 /**
   * @brief Ensure that UART communication mode is valid.
@@ -1294,8 +1307,15 @@ typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer
   * @param __TIMEOUT__ UART receiver timeout setting.
   * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
   */
-#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
-                                               ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
 
 /**
   * @brief Ensure that UART LIN state is valid.
@@ -1514,7 +1534,8 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 
@@ -1563,6 +1584,10 @@ void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
   */
 
 /* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
 HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
@@ -1599,7 +1624,8 @@ void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
 void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
 
 /**

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_uart_ex.h

@@ -69,9 +69,9 @@ typedef struct
 /** @defgroup UARTEx_Word_Length UARTEx Word Length
   * @{
   */
-#define UART_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long UART frame */
-#define UART_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long UART frame */
-#define UART_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long UART frame */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
 /**
   * @}
   */
@@ -79,8 +79,8 @@ typedef struct
 /** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
   * @{
   */
-#define UART_ADDRESS_DETECT_4B              0x00000000U      /*!< 4-bit long wake-up address */
-#define UART_ADDRESS_DETECT_7B              USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
 /**
   * @}
   */
@@ -89,8 +89,8 @@ typedef struct
   * @brief    UART FIFO mode
   * @{
   */
-#define UART_FIFOMODE_DISABLE        0x00000000U       /*!< FIFO mode disable */
-#define UART_FIFOMODE_ENABLE         USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
 /**
   * @}
   */
@@ -138,7 +138,8 @@ typedef struct
   */
 
 /* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime);
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
 
 /**
   * @}
@@ -165,7 +166,9 @@ void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
 HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
 HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
 HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
 HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
@@ -189,6 +192,7 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
   * @param  __CLOCKSOURCE__ output variable.
   * @retval UART clocking source, written in __CLOCKSOURCE__.
   */
+#if defined(UART9) && defined(USART10)
 #define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
   do {                                                        \
     if((__HANDLE__)->Instance == USART1)                      \
@@ -407,6 +411,60 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
           break;                                              \
       }                                                       \
     }                                                         \
+    else if((__HANDLE__)->Instance == UART9)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \
+      {                                                       \
+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART9CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART10)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \
+      {                                                       \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART10CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
     else if((__HANDLE__)->Instance == LPUART1)                \
     {                                                         \
       switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
@@ -439,6 +497,258 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
       (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
     }                                                         \
   } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if ((__HANDLE__)->Instance == UART5)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART6)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \
+      {                                                       \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_USART6CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART7)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \
+      {                                                       \
+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART7CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART8)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \
+      {                                                       \
+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_UART8CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_PLL3:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_CSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif  /* UART9 && USART10 */
 
 /** @brief  Report the UART mask to apply to retrieve the received data
   *         according to the word length and to the parity bits activation.
@@ -451,44 +761,44 @@ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint3
   */
 #define UART_MASK_COMPUTATION(__HANDLE__)                             \
   do {                                                                \
-  if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)            \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
         (__HANDLE__)->Mask = 0x01FFU ;                                \
-     }                                                                \
-     else                                                             \
-     {                                                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
         (__HANDLE__)->Mask = 0x00FFU ;                                \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
         (__HANDLE__)->Mask = 0x00FFU ;                                \
-     }                                                                \
-     else                                                             \
-     {                                                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
         (__HANDLE__)->Mask = 0x007FU ;                                \
-     }                                                                \
-  }                                                                   \
-  else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)       \
-  {                                                                   \
-     if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)               \
-     {                                                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
         (__HANDLE__)->Mask = 0x007FU ;                                \
-     }                                                                \
-     else                                                             \
-     {                                                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
         (__HANDLE__)->Mask = 0x003FU ;                                \
-     }                                                                \
-  }                                                                   \
-  else                                                                \
-  {                                                                   \
-    (__HANDLE__)->Mask = 0x0000U;                                     \
-  }                                                                   \
-} while(0U)
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
 
 /**
   * @brief Ensure that UART frame length is valid.

STM32H7xx_HAL_Driver/Inc/stm32h7xx_hal_usart.h

@@ -437,10 +437,10 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   */
 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \
-                                                      (__HANDLE__)->State = HAL_USART_STATE_RESET; \
-                                                      (__HANDLE__)->MspInitCallback = NULL;        \
-                                                      (__HANDLE__)->MspDeInitCallback = NULL;      \
-                                                    } while(0U)
+                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \
+                                                        (__HANDLE__)->MspInitCallback = NULL;        \
+                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \
+                                                      } while(0U)
 #else
 #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)
 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
@@ -594,7 +594,8 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   *            @arg @ref USART_IT_PE    Parity Error interrupt
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
-#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                         & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)
 
 /** @brief  Check whether the specified USART interrupt source is enabled or not.
   * @param  __HANDLE__ specifies the USART Handle.
@@ -617,8 +618,8 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   * @retval The new state of __INTERRUPT__ (SET or RESET).
   */
 #define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \
-                                                                (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
-                                                                (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != 0U) ? SET : RESET)
+                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \
+                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != 0U) ? SET : RESET)
 
 
 /** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.
@@ -705,13 +706,15 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
   * @param  __CLOCKPRESCALER__ UART prescaler value.
   * @retval Division result
   */
-#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\
+                                                                        + ((__BAUD__)/2U)) / (__BAUD__))
 
 /** @brief  Report the USART clock source.
   * @param  __HANDLE__ specifies the USART Handle.
   * @param  __CLOCKSOURCE__ output variable.
   * @retval the USART clocking source, written in __CLOCKSOURCE__.
   */
+#if defined(UART9) && defined(USART10)
 #define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
   do {                                                         \
     if((__HANDLE__)->Instance == USART1)                       \
@@ -749,7 +752,150 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
           break;                                               \
         case RCC_USART2CLKSOURCE_PLL2:                         \
-           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART3)                  \
+    {                                                          \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                    \
+      {                                                        \
+        case RCC_USART3CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
+          break;                                               \
+        case RCC_USART3CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART6)                  \
+    {                                                          \
+      switch(__HAL_RCC_GET_USART6_SOURCE())                    \
+      {                                                        \
+        case RCC_USART6CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
+          break;                                               \
+        case RCC_USART6CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART10)                 \
+    {                                                          \
+      switch(__HAL_RCC_GET_USART10_SOURCE())                   \
+      {                                                        \
+        case RCC_USART10CLKSOURCE_D2PCLK2:                     \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_PLL2:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_PLL3:                        \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_CSI:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
+          break;                                               \
+        case RCC_USART10CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else                                                       \
+    {                                                          \
+      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                          \
+  } while(0U)
+#else
+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                         \
+    if((__HANDLE__)->Instance == USART1)                       \
+    {                                                          \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                    \
+      {                                                        \
+        case RCC_USART1CLKSOURCE_D2PCLK2:                      \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_PLL3:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_CSI:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \
+          break;                                               \
+        case RCC_USART1CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \
+          break;                                               \
+        default:                                               \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                               \
+      }                                                        \
+    }                                                          \
+    else if((__HANDLE__)->Instance == USART2)                  \
+    {                                                          \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                    \
+      {                                                        \
+        case RCC_USART2CLKSOURCE_D2PCLK1:                      \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \
+          break;                                               \
+        case RCC_USART2CLKSOURCE_PLL2:                         \
+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \
           break;                                               \
         case RCC_USART2CLKSOURCE_PLL3:                         \
           (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \
@@ -827,6 +973,7 @@ typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< poin
       (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \
     }                                                          \
   } while(0U)
+#endif  /* UART9 && USART10 */
 
 /** @brief  Check USART Baud rate.
   * @param  __BAUDRATE__ Baudrate specified by the user.
@@ -949,7 +1096,8 @@ void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
 
 /* Callbacks Register/UnRegister functions  ***********************************/
 #if (USE_HAL_USART_REGISTER_CALLBACKS == 1)
-HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID, pUSART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,
+                                             pUSART_CallbackTypeDef pCallback);
 HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);
 #endif /* USE_HAL_USART_REGISTER_CALLBACKS */
 
@@ -964,13 +1112,16 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_
 /* IO operation functions *****************************************************/
 HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+                                            uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
 HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+                                               uint16_t Size);
 HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
 HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,
+                                                uint16_t Size);
 HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
 HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);