|
- /**
- * \file
- *
- * \brief Instance description for OSCCTRL
- *
- * Copyright (c) 2016 Atmel Corporation,
- * a wholly owned subsidiary of Microchip Technology Inc.
- *
- * \asf_license_start
- *
- * \page License
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the Licence at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * \asf_license_stop
- *
- */
-
- #ifndef _SAML21_OSCCTRL_INSTANCE_
- #define _SAML21_OSCCTRL_INSTANCE_
-
- /* ========== Register definition for OSCCTRL peripheral ========== */
- #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
- #define REG_OSCCTRL_INTENCLR (0x40000C00) /**< \brief (OSCCTRL) Interrupt Enable Clear */
- #define REG_OSCCTRL_INTENSET (0x40000C04) /**< \brief (OSCCTRL) Interrupt Enable Set */
- #define REG_OSCCTRL_INTFLAG (0x40000C08) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
- #define REG_OSCCTRL_STATUS (0x40000C0C) /**< \brief (OSCCTRL) Power and Clocks Status */
- #define REG_OSCCTRL_XOSCCTRL (0x40000C10) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
- #define REG_OSCCTRL_OSC16MCTRL (0x40000C14) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */
- #define REG_OSCCTRL_DFLLCTRL (0x40000C18) /**< \brief (OSCCTRL) DFLL48M Control */
- #define REG_OSCCTRL_DFLLVAL (0x40000C1C) /**< \brief (OSCCTRL) DFLL48M Value */
- #define REG_OSCCTRL_DFLLMUL (0x40000C20) /**< \brief (OSCCTRL) DFLL48M Multiplier */
- #define REG_OSCCTRL_DFLLSYNC (0x40000C24) /**< \brief (OSCCTRL) DFLL48M Synchronization */
- #define REG_OSCCTRL_DPLLCTRLA (0x40000C28) /**< \brief (OSCCTRL) DPLL Control */
- #define REG_OSCCTRL_DPLLRATIO (0x40000C2C) /**< \brief (OSCCTRL) DPLL Ratio Control */
- #define REG_OSCCTRL_DPLLCTRLB (0x40000C30) /**< \brief (OSCCTRL) Digital Core Configuration */
- #define REG_OSCCTRL_DPLLPRESC (0x40000C34) /**< \brief (OSCCTRL) DPLL Prescaler */
- #define REG_OSCCTRL_DPLLSYNCBUSY (0x40000C38) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
- #define REG_OSCCTRL_DPLLSTATUS (0x40000C3C) /**< \brief (OSCCTRL) DPLL Status */
- #else
- #define REG_OSCCTRL_INTENCLR (*(RwReg *)0x40000C00UL) /**< \brief (OSCCTRL) Interrupt Enable Clear */
- #define REG_OSCCTRL_INTENSET (*(RwReg *)0x40000C04UL) /**< \brief (OSCCTRL) Interrupt Enable Set */
- #define REG_OSCCTRL_INTFLAG (*(RwReg *)0x40000C08UL) /**< \brief (OSCCTRL) Interrupt Flag Status and Clear */
- #define REG_OSCCTRL_STATUS (*(RoReg *)0x40000C0CUL) /**< \brief (OSCCTRL) Power and Clocks Status */
- #define REG_OSCCTRL_XOSCCTRL (*(RwReg16*)0x40000C10UL) /**< \brief (OSCCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */
- #define REG_OSCCTRL_OSC16MCTRL (*(RwReg8 *)0x40000C14UL) /**< \brief (OSCCTRL) 16MHz Internal Oscillator (OSC16M) Control */
- #define REG_OSCCTRL_DFLLCTRL (*(RwReg16*)0x40000C18UL) /**< \brief (OSCCTRL) DFLL48M Control */
- #define REG_OSCCTRL_DFLLVAL (*(RwReg *)0x40000C1CUL) /**< \brief (OSCCTRL) DFLL48M Value */
- #define REG_OSCCTRL_DFLLMUL (*(RwReg *)0x40000C20UL) /**< \brief (OSCCTRL) DFLL48M Multiplier */
- #define REG_OSCCTRL_DFLLSYNC (*(RwReg8 *)0x40000C24UL) /**< \brief (OSCCTRL) DFLL48M Synchronization */
- #define REG_OSCCTRL_DPLLCTRLA (*(RwReg8 *)0x40000C28UL) /**< \brief (OSCCTRL) DPLL Control */
- #define REG_OSCCTRL_DPLLRATIO (*(RwReg *)0x40000C2CUL) /**< \brief (OSCCTRL) DPLL Ratio Control */
- #define REG_OSCCTRL_DPLLCTRLB (*(RwReg *)0x40000C30UL) /**< \brief (OSCCTRL) Digital Core Configuration */
- #define REG_OSCCTRL_DPLLPRESC (*(RwReg8 *)0x40000C34UL) /**< \brief (OSCCTRL) DPLL Prescaler */
- #define REG_OSCCTRL_DPLLSYNCBUSY (*(RoReg8 *)0x40000C38UL) /**< \brief (OSCCTRL) DPLL Synchronization Busy */
- #define REG_OSCCTRL_DPLLSTATUS (*(RoReg8 *)0x40000C3CUL) /**< \brief (OSCCTRL) DPLL Status */
- #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
-
- /* ========== Instance parameters for OSCCTRL peripheral ========== */
- #define OSCCTRL_DFLL48M_COARSE_MSB 5
- #define OSCCTRL_DFLL48M_FINE_MSB 9
- #define OSCCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
- #define OSCCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
- #define OSCCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
- #define OSCCTRL_DFLL48M_VERSION 0x320
- #define OSCCTRL_FDPLL_VERSION 0x200
- #define OSCCTRL_OSC16M_VERSION 0x100
- #define OSCCTRL_XOSC_VERSION 0x120
-
- #endif /* _SAML21_OSCCTRL_INSTANCE_ */
|
