Implement a secure ICS protocol targeting LoRa Node151 microcontroller for controlling irrigation.
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  1. /**
  2. ******************************************************************************
  3. * @file stm32l1xx_hal_tim.h
  4. * @author MCD Application Team
  5. * @brief Header file of TIM HAL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by ST under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. */
  19. /* Define to prevent recursive inclusion -------------------------------------*/
  20. #ifndef STM32L1xx_HAL_TIM_H
  21. #define STM32L1xx_HAL_TIM_H
  22. #ifdef __cplusplus
  23. extern "C" {
  24. #endif
  25. /* Includes ------------------------------------------------------------------*/
  26. #include "stm32l1xx_hal_def.h"
  27. /** @addtogroup STM32L1xx_HAL_Driver
  28. * @{
  29. */
  30. /** @addtogroup TIM
  31. * @{
  32. */
  33. /* Exported types ------------------------------------------------------------*/
  34. /** @defgroup TIM_Exported_Types TIM Exported Types
  35. * @{
  36. */
  37. /**
  38. * @brief TIM Time base Configuration Structure definition
  39. */
  40. typedef struct
  41. {
  42. uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
  43. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  44. uint32_t CounterMode; /*!< Specifies the counter mode.
  45. This parameter can be a value of @ref TIM_Counter_Mode */
  46. uint32_t Period; /*!< Specifies the period value to be loaded into the active
  47. Auto-Reload Register at the next update event.
  48. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
  49. uint32_t ClockDivision; /*!< Specifies the clock division.
  50. This parameter can be a value of @ref TIM_ClockDivision */
  51. uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
  52. This parameter can be a value of @ref TIM_AutoReloadPreload */
  53. } TIM_Base_InitTypeDef;
  54. /**
  55. * @brief TIM Output Compare Configuration Structure definition
  56. */
  57. typedef struct
  58. {
  59. uint32_t OCMode; /*!< Specifies the TIM mode.
  60. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  61. uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  62. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  63. uint32_t OCPolarity; /*!< Specifies the output polarity.
  64. This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  65. uint32_t OCFastMode; /*!< Specifies the Fast mode state.
  66. This parameter can be a value of @ref TIM_Output_Fast_State
  67. @note This parameter is valid only in PWM1 and PWM2 mode. */
  68. } TIM_OC_InitTypeDef;
  69. /**
  70. * @brief TIM One Pulse Mode Configuration Structure definition
  71. */
  72. typedef struct
  73. {
  74. uint32_t OCMode; /*!< Specifies the TIM mode.
  75. This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
  76. uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
  77. This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
  78. uint32_t OCPolarity; /*!< Specifies the output polarity.
  79. This parameter can be a value of @ref TIM_Output_Compare_Polarity */
  80. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  81. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  82. uint32_t ICSelection; /*!< Specifies the input.
  83. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  84. uint32_t ICFilter; /*!< Specifies the input capture filter.
  85. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  86. } TIM_OnePulse_InitTypeDef;
  87. /**
  88. * @brief TIM Input Capture Configuration Structure definition
  89. */
  90. typedef struct
  91. {
  92. uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
  93. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  94. uint32_t ICSelection; /*!< Specifies the input.
  95. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  96. uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
  97. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  98. uint32_t ICFilter; /*!< Specifies the input capture filter.
  99. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  100. } TIM_IC_InitTypeDef;
  101. /**
  102. * @brief TIM Encoder Configuration Structure definition
  103. */
  104. typedef struct
  105. {
  106. uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
  107. This parameter can be a value of @ref TIM_Encoder_Mode */
  108. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
  109. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  110. uint32_t IC1Selection; /*!< Specifies the input.
  111. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  112. uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
  113. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  114. uint32_t IC1Filter; /*!< Specifies the input capture filter.
  115. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  116. uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
  117. This parameter can be a value of @ref TIM_Input_Capture_Polarity */
  118. uint32_t IC2Selection; /*!< Specifies the input.
  119. This parameter can be a value of @ref TIM_Input_Capture_Selection */
  120. uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
  121. This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
  122. uint32_t IC2Filter; /*!< Specifies the input capture filter.
  123. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  124. } TIM_Encoder_InitTypeDef;
  125. /**
  126. * @brief Clock Configuration Handle Structure definition
  127. */
  128. typedef struct
  129. {
  130. uint32_t ClockSource; /*!< TIM clock sources
  131. This parameter can be a value of @ref TIM_Clock_Source */
  132. uint32_t ClockPolarity; /*!< TIM clock polarity
  133. This parameter can be a value of @ref TIM_Clock_Polarity */
  134. uint32_t ClockPrescaler; /*!< TIM clock prescaler
  135. This parameter can be a value of @ref TIM_Clock_Prescaler */
  136. uint32_t ClockFilter; /*!< TIM clock filter
  137. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  138. } TIM_ClockConfigTypeDef;
  139. /**
  140. * @brief TIM Clear Input Configuration Handle Structure definition
  141. */
  142. typedef struct
  143. {
  144. uint32_t ClearInputState; /*!< TIM clear Input state
  145. This parameter can be ENABLE or DISABLE */
  146. uint32_t ClearInputSource; /*!< TIM clear Input sources
  147. This parameter can be a value of @ref TIM_ClearInput_Source */
  148. uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity
  149. This parameter can be a value of @ref TIM_ClearInput_Polarity */
  150. uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler
  151. This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */
  152. uint32_t ClearInputFilter; /*!< TIM Clear Input filter
  153. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  154. } TIM_ClearInputConfigTypeDef;
  155. /**
  156. * @brief TIM Master configuration Structure definition
  157. */
  158. typedef struct
  159. {
  160. uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
  161. This parameter can be a value of @ref TIM_Master_Mode_Selection */
  162. uint32_t MasterSlaveMode; /*!< Master/slave mode selection
  163. This parameter can be a value of @ref TIM_Master_Slave_Mode */
  164. } TIM_MasterConfigTypeDef;
  165. /**
  166. * @brief TIM Slave configuration Structure definition
  167. */
  168. typedef struct
  169. {
  170. uint32_t SlaveMode; /*!< Slave mode selection
  171. This parameter can be a value of @ref TIM_Slave_Mode */
  172. uint32_t InputTrigger; /*!< Input Trigger source
  173. This parameter can be a value of @ref TIM_Trigger_Selection */
  174. uint32_t TriggerPolarity; /*!< Input Trigger polarity
  175. This parameter can be a value of @ref TIM_Trigger_Polarity */
  176. uint32_t TriggerPrescaler; /*!< Input trigger prescaler
  177. This parameter can be a value of @ref TIM_Trigger_Prescaler */
  178. uint32_t TriggerFilter; /*!< Input trigger filter
  179. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
  180. } TIM_SlaveConfigTypeDef;
  181. /**
  182. * @brief HAL State structures definition
  183. */
  184. typedef enum
  185. {
  186. HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
  187. HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
  188. HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
  189. HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
  190. HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
  191. } HAL_TIM_StateTypeDef;
  192. /**
  193. * @brief HAL Active channel structures definition
  194. */
  195. typedef enum
  196. {
  197. HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
  198. HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
  199. HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
  200. HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
  201. HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
  202. } HAL_TIM_ActiveChannel;
  203. /**
  204. * @brief TIM Time Base Handle Structure definition
  205. */
  206. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  207. typedef struct __TIM_HandleTypeDef
  208. #else
  209. typedef struct
  210. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  211. {
  212. TIM_TypeDef *Instance; /*!< Register base address */
  213. TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
  214. HAL_TIM_ActiveChannel Channel; /*!< Active channel */
  215. DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
  216. This array is accessed by a @ref DMA_Handle_index */
  217. HAL_LockTypeDef Lock; /*!< Locking object */
  218. __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
  219. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  220. void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
  221. void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
  222. void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
  223. void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
  224. void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
  225. void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
  226. void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
  227. void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
  228. void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
  229. void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
  230. void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
  231. void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
  232. void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
  233. void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */
  234. void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
  235. void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */
  236. void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
  237. void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */
  238. void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
  239. void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
  240. void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */
  241. void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
  242. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  243. } TIM_HandleTypeDef;
  244. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  245. /**
  246. * @brief HAL TIM Callback ID enumeration definition
  247. */
  248. typedef enum
  249. {
  250. HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
  251. ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
  252. ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
  253. ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
  254. ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
  255. ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
  256. ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
  257. ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
  258. ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
  259. ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
  260. ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
  261. ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
  262. ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
  263. ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
  264. ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
  265. ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
  266. ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
  267. ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
  268. ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
  269. ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
  270. ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
  271. ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
  272. } HAL_TIM_CallbackIDTypeDef;
  273. /**
  274. * @brief HAL TIM Callback pointer definition
  275. */
  276. typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */
  277. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  278. /**
  279. * @}
  280. */
  281. /* End of exported types -----------------------------------------------------*/
  282. /* Exported constants --------------------------------------------------------*/
  283. /** @defgroup TIM_Exported_Constants TIM Exported Constants
  284. * @{
  285. */
  286. /** @defgroup TIM_ClearInput_Source TIM Clear Input Source
  287. * @{
  288. */
  289. #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U /*!< OCREF_CLR is disabled */
  290. #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */
  291. #define TIM_CLEARINPUTSOURCE_OCREFCLR 0x00000002U /*!< OCREF_CLR is connected to OCREF_CLR_INT */
  292. /**
  293. * @}
  294. */
  295. /** @defgroup TIM_DMA_Base_address TIM DMA Base Address
  296. * @{
  297. */
  298. #define TIM_DMABASE_CR1 0x00000000U
  299. #define TIM_DMABASE_CR2 0x00000001U
  300. #define TIM_DMABASE_SMCR 0x00000002U
  301. #define TIM_DMABASE_DIER 0x00000003U
  302. #define TIM_DMABASE_SR 0x00000004U
  303. #define TIM_DMABASE_EGR 0x00000005U
  304. #define TIM_DMABASE_CCMR1 0x00000006U
  305. #define TIM_DMABASE_CCMR2 0x00000007U
  306. #define TIM_DMABASE_CCER 0x00000008U
  307. #define TIM_DMABASE_CNT 0x00000009U
  308. #define TIM_DMABASE_PSC 0x0000000AU
  309. #define TIM_DMABASE_ARR 0x0000000BU
  310. #define TIM_DMABASE_CCR1 0x0000000DU
  311. #define TIM_DMABASE_CCR2 0x0000000EU
  312. #define TIM_DMABASE_CCR3 0x0000000FU
  313. #define TIM_DMABASE_CCR4 0x00000010U
  314. #define TIM_DMABASE_DCR 0x00000012U
  315. #define TIM_DMABASE_DMAR 0x00000013U
  316. #define TIM_DMABASE_OR 0x00000014U
  317. /**
  318. * @}
  319. */
  320. /** @defgroup TIM_Event_Source TIM Event Source
  321. * @{
  322. */
  323. #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */
  324. #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */
  325. #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */
  326. #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */
  327. #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */
  328. #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */
  329. /**
  330. * @}
  331. */
  332. /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity
  333. * @{
  334. */
  335. #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */
  336. #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */
  337. #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
  338. /**
  339. * @}
  340. */
  341. /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
  342. * @{
  343. */
  344. #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */
  345. #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */
  346. /**
  347. * @}
  348. */
  349. /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
  350. * @{
  351. */
  352. #define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */
  353. #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */
  354. #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */
  355. #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */
  356. /**
  357. * @}
  358. */
  359. /** @defgroup TIM_Counter_Mode TIM Counter Mode
  360. * @{
  361. */
  362. #define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */
  363. #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */
  364. #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */
  365. #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */
  366. #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */
  367. /**
  368. * @}
  369. */
  370. /** @defgroup TIM_ClockDivision TIM Clock Division
  371. * @{
  372. */
  373. #define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */
  374. #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */
  375. #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */
  376. /**
  377. * @}
  378. */
  379. /** @defgroup TIM_Output_Compare_State TIM Output Compare State
  380. * @{
  381. */
  382. #define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */
  383. #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */
  384. /**
  385. * @}
  386. */
  387. /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
  388. * @{
  389. */
  390. #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */
  391. #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */
  392. /**
  393. * @}
  394. */
  395. /** @defgroup TIM_Output_Fast_State TIM Output Fast State
  396. * @{
  397. */
  398. #define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */
  399. #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */
  400. /**
  401. * @}
  402. */
  403. /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
  404. * @{
  405. */
  406. #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */
  407. #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */
  408. /**
  409. * @}
  410. */
  411. /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
  412. * @{
  413. */
  414. #define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */
  415. #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */
  416. /**
  417. * @}
  418. */
  419. /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
  420. * @{
  421. */
  422. #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */
  423. #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */
  424. #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/
  425. /**
  426. * @}
  427. */
  428. /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
  429. * @{
  430. */
  431. #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be
  432. connected to IC1, IC2, IC3 or IC4, respectively */
  433. #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be
  434. connected to IC2, IC1, IC4 or IC3, respectively */
  435. #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
  436. /**
  437. * @}
  438. */
  439. /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
  440. * @{
  441. */
  442. #define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */
  443. #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */
  444. #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */
  445. #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */
  446. /**
  447. * @}
  448. */
  449. /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
  450. * @{
  451. */
  452. #define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */
  453. #define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */
  454. /**
  455. * @}
  456. */
  457. /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
  458. * @{
  459. */
  460. #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */
  461. #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */
  462. #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */
  463. /**
  464. * @}
  465. */
  466. /** @defgroup TIM_Interrupt_definition TIM interrupt Definition
  467. * @{
  468. */
  469. #define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */
  470. #define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */
  471. #define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */
  472. #define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */
  473. #define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */
  474. #define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */
  475. /**
  476. * @}
  477. */
  478. /** @defgroup TIM_DMA_sources TIM DMA Sources
  479. * @{
  480. */
  481. #define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */
  482. #define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */
  483. #define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */
  484. #define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */
  485. #define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */
  486. #define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */
  487. /**
  488. * @}
  489. */
  490. /** @defgroup TIM_Flag_definition TIM Flag Definition
  491. * @{
  492. */
  493. #define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */
  494. #define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */
  495. #define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */
  496. #define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */
  497. #define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */
  498. #define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */
  499. #define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */
  500. #define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */
  501. #define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */
  502. #define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */
  503. /**
  504. * @}
  505. */
  506. /** @defgroup TIM_Channel TIM Channel
  507. * @{
  508. */
  509. #define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */
  510. #define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */
  511. #define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */
  512. #define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */
  513. #define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */
  514. /**
  515. * @}
  516. */
  517. /** @defgroup TIM_Clock_Source TIM Clock Source
  518. * @{
  519. */
  520. #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */
  521. #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */
  522. #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */
  523. #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */
  524. #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */
  525. #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */
  526. #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */
  527. #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */
  528. #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */
  529. #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */
  530. /**
  531. * @}
  532. */
  533. /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
  534. * @{
  535. */
  536. #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
  537. #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
  538. #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
  539. #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
  540. #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
  541. /**
  542. * @}
  543. */
  544. /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
  545. * @{
  546. */
  547. #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  548. #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
  549. #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
  550. #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
  551. /**
  552. * @}
  553. */
  554. /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
  555. * @{
  556. */
  557. #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
  558. #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
  559. /**
  560. * @}
  561. */
  562. /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
  563. * @{
  564. */
  565. #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  566. #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
  567. #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
  568. #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
  569. /**
  570. * @}
  571. */
  572. /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
  573. * @{
  574. */
  575. #define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */
  576. #define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */
  577. #define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */
  578. #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */
  579. #define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */
  580. #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */
  581. #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */
  582. #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */
  583. /**
  584. * @}
  585. */
  586. /** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode
  587. * @{
  588. */
  589. #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */
  590. #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */
  591. /**
  592. * @}
  593. */
  594. /** @defgroup TIM_Slave_Mode TIM Slave mode
  595. * @{
  596. */
  597. #define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */
  598. #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */
  599. #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */
  600. #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */
  601. #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */
  602. /**
  603. * @}
  604. */
  605. /** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes
  606. * @{
  607. */
  608. #define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */
  609. #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */
  610. #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */
  611. #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */
  612. #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */
  613. #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */
  614. #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */
  615. #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */
  616. /**
  617. * @}
  618. */
  619. /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
  620. * @{
  621. */
  622. #define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */
  623. #define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */
  624. #define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */
  625. #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */
  626. #define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */
  627. #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */
  628. #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */
  629. #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */
  630. #define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */
  631. /**
  632. * @}
  633. */
  634. /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
  635. * @{
  636. */
  637. #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
  638. #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
  639. #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  640. #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  641. #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
  642. /**
  643. * @}
  644. */
  645. /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
  646. * @{
  647. */
  648. #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
  649. #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
  650. #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
  651. #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
  652. /**
  653. * @}
  654. */
  655. /** @defgroup TIM_TI1_Selection TIM TI1 Input Selection
  656. * @{
  657. */
  658. #define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */
  659. #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */
  660. /**
  661. * @}
  662. */
  663. /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
  664. * @{
  665. */
  666. #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */
  667. #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  668. #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  669. #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  670. #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  671. #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  672. #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  673. #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  674. #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  675. #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  676. #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  677. #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  678. #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  679. #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  680. #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  681. #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  682. #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  683. #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */
  684. /**
  685. * @}
  686. */
  687. /** @defgroup DMA_Handle_index TIM DMA Handle Index
  688. * @{
  689. */
  690. #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */
  691. #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
  692. #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
  693. #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
  694. #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
  695. #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */
  696. /**
  697. * @}
  698. */
  699. /** @defgroup Channel_CC_State TIM Capture/Compare Channel State
  700. * @{
  701. */
  702. #define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */
  703. #define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */
  704. /**
  705. * @}
  706. */
  707. /**
  708. * @}
  709. */
  710. /* End of exported constants -------------------------------------------------*/
  711. /* Exported macros -----------------------------------------------------------*/
  712. /** @defgroup TIM_Exported_Macros TIM Exported Macros
  713. * @{
  714. */
  715. /** @brief Reset TIM handle state.
  716. * @param __HANDLE__ TIM handle.
  717. * @retval None
  718. */
  719. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  720. #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
  721. (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
  722. (__HANDLE__)->Base_MspInitCallback = NULL; \
  723. (__HANDLE__)->Base_MspDeInitCallback = NULL; \
  724. (__HANDLE__)->IC_MspInitCallback = NULL; \
  725. (__HANDLE__)->IC_MspDeInitCallback = NULL; \
  726. (__HANDLE__)->OC_MspInitCallback = NULL; \
  727. (__HANDLE__)->OC_MspDeInitCallback = NULL; \
  728. (__HANDLE__)->PWM_MspInitCallback = NULL; \
  729. (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
  730. (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
  731. (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
  732. (__HANDLE__)->Encoder_MspInitCallback = NULL; \
  733. (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
  734. } while(0)
  735. #else
  736. #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
  737. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  738. /**
  739. * @brief Enable the TIM peripheral.
  740. * @param __HANDLE__ TIM handle
  741. * @retval None
  742. */
  743. #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
  744. /**
  745. * @brief Disable the TIM peripheral.
  746. * @param __HANDLE__ TIM handle
  747. * @retval None
  748. */
  749. #define __HAL_TIM_DISABLE(__HANDLE__) \
  750. do { \
  751. if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
  752. { \
  753. (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
  754. } \
  755. } while(0)
  756. /** @brief Enable the specified TIM interrupt.
  757. * @param __HANDLE__ specifies the TIM Handle.
  758. * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
  759. * This parameter can be one of the following values:
  760. * @arg TIM_IT_UPDATE: Update interrupt
  761. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  762. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  763. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  764. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  765. * @arg TIM_IT_TRIGGER: Trigger interrupt
  766. * @retval None
  767. */
  768. #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
  769. /** @brief Disable the specified TIM interrupt.
  770. * @param __HANDLE__ specifies the TIM Handle.
  771. * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
  772. * This parameter can be one of the following values:
  773. * @arg TIM_IT_UPDATE: Update interrupt
  774. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  775. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  776. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  777. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  778. * @arg TIM_IT_TRIGGER: Trigger interrupt
  779. * @retval None
  780. */
  781. #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
  782. /** @brief Enable the specified DMA request.
  783. * @param __HANDLE__ specifies the TIM Handle.
  784. * @param __DMA__ specifies the TIM DMA request to enable.
  785. * This parameter can be one of the following values:
  786. * @arg TIM_DMA_UPDATE: Update DMA request
  787. * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
  788. * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
  789. * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
  790. * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
  791. * @arg TIM_DMA_TRIGGER: Trigger DMA request
  792. * @retval None
  793. */
  794. #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
  795. /** @brief Disable the specified DMA request.
  796. * @param __HANDLE__ specifies the TIM Handle.
  797. * @param __DMA__ specifies the TIM DMA request to disable.
  798. * This parameter can be one of the following values:
  799. * @arg TIM_DMA_UPDATE: Update DMA request
  800. * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
  801. * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
  802. * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
  803. * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
  804. * @arg TIM_DMA_TRIGGER: Trigger DMA request
  805. * @retval None
  806. */
  807. #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
  808. /** @brief Check whether the specified TIM interrupt flag is set or not.
  809. * @param __HANDLE__ specifies the TIM Handle.
  810. * @param __FLAG__ specifies the TIM interrupt flag to check.
  811. * This parameter can be one of the following values:
  812. * @arg TIM_FLAG_UPDATE: Update interrupt flag
  813. * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  814. * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  815. * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  816. * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  817. * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  818. * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  819. * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  820. * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  821. * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  822. * @retval The new state of __FLAG__ (TRUE or FALSE).
  823. */
  824. #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
  825. /** @brief Clear the specified TIM interrupt flag.
  826. * @param __HANDLE__ specifies the TIM Handle.
  827. * @param __FLAG__ specifies the TIM interrupt flag to clear.
  828. * This parameter can be one of the following values:
  829. * @arg TIM_FLAG_UPDATE: Update interrupt flag
  830. * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
  831. * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
  832. * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
  833. * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
  834. * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
  835. * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
  836. * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
  837. * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
  838. * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
  839. * @retval The new state of __FLAG__ (TRUE or FALSE).
  840. */
  841. #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
  842. /**
  843. * @brief Check whether the specified TIM interrupt source is enabled or not.
  844. * @param __HANDLE__ TIM handle
  845. * @param __INTERRUPT__ specifies the TIM interrupt source to check.
  846. * This parameter can be one of the following values:
  847. * @arg TIM_IT_UPDATE: Update interrupt
  848. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  849. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  850. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  851. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  852. * @arg TIM_IT_TRIGGER: Trigger interrupt
  853. * @retval The state of TIM_IT (SET or RESET).
  854. */
  855. #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
  856. /** @brief Clear the TIM interrupt pending bits.
  857. * @param __HANDLE__ TIM handle
  858. * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
  859. * This parameter can be one of the following values:
  860. * @arg TIM_IT_UPDATE: Update interrupt
  861. * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
  862. * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
  863. * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
  864. * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
  865. * @arg TIM_IT_TRIGGER: Trigger interrupt
  866. * @retval None
  867. */
  868. #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
  869. /**
  870. * @brief Indicates whether or not the TIM Counter is used as downcounter.
  871. * @param __HANDLE__ TIM handle.
  872. * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
  873. * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
  874. mode.
  875. */
  876. #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
  877. /**
  878. * @brief Set the TIM Prescaler on runtime.
  879. * @param __HANDLE__ TIM handle.
  880. * @param __PRESC__ specifies the Prescaler new value.
  881. * @retval None
  882. */
  883. #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
  884. /**
  885. * @brief Set the TIM Counter Register value on runtime.
  886. * @param __HANDLE__ TIM handle.
  887. * @param __COUNTER__ specifies the Counter register new value.
  888. * @retval None
  889. */
  890. #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
  891. /**
  892. * @brief Get the TIM Counter Register value on runtime.
  893. * @param __HANDLE__ TIM handle.
  894. * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
  895. */
  896. #define __HAL_TIM_GET_COUNTER(__HANDLE__) \
  897. ((__HANDLE__)->Instance->CNT)
  898. /**
  899. * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
  900. * @param __HANDLE__ TIM handle.
  901. * @param __AUTORELOAD__ specifies the Counter register new value.
  902. * @retval None
  903. */
  904. #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
  905. do{ \
  906. (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
  907. (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
  908. } while(0)
  909. /**
  910. * @brief Get the TIM Autoreload Register value on runtime.
  911. * @param __HANDLE__ TIM handle.
  912. * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
  913. */
  914. #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \
  915. ((__HANDLE__)->Instance->ARR)
  916. /**
  917. * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
  918. * @param __HANDLE__ TIM handle.
  919. * @param __CKD__ specifies the clock division value.
  920. * This parameter can be one of the following value:
  921. * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  922. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  923. * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  924. * @retval None
  925. */
  926. #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
  927. do{ \
  928. (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
  929. (__HANDLE__)->Instance->CR1 |= (__CKD__); \
  930. (__HANDLE__)->Init.ClockDivision = (__CKD__); \
  931. } while(0)
  932. /**
  933. * @brief Get the TIM Clock Division value on runtime.
  934. * @param __HANDLE__ TIM handle.
  935. * @retval The clock division can be one of the following values:
  936. * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
  937. * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
  938. * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
  939. */
  940. #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \
  941. ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
  942. /**
  943. * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
  944. * @param __HANDLE__ TIM handle.
  945. * @param __CHANNEL__ TIM Channels to be configured.
  946. * This parameter can be one of the following values:
  947. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  948. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  949. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  950. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  951. * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
  952. * This parameter can be one of the following values:
  953. * @arg TIM_ICPSC_DIV1: no prescaler
  954. * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  955. * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  956. * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  957. * @retval None
  958. */
  959. #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
  960. do{ \
  961. TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
  962. TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
  963. } while(0)
  964. /**
  965. * @brief Get the TIM Input Capture prescaler on runtime.
  966. * @param __HANDLE__ TIM handle.
  967. * @param __CHANNEL__ TIM Channels to be configured.
  968. * This parameter can be one of the following values:
  969. * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
  970. * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
  971. * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
  972. * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
  973. * @retval The input capture prescaler can be one of the following values:
  974. * @arg TIM_ICPSC_DIV1: no prescaler
  975. * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
  976. * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
  977. * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
  978. */
  979. #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
  980. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
  981. ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
  982. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
  983. (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
  984. /**
  985. * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.
  986. * @param __HANDLE__ TIM handle.
  987. * @param __CHANNEL__ TIM Channels to be configured.
  988. * This parameter can be one of the following values:
  989. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  990. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  991. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  992. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  993. * @param __COMPARE__ specifies the Capture Compare register new value.
  994. * @retval None
  995. */
  996. #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
  997. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
  998. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
  999. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
  1000. ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
  1001. /**
  1002. * @brief Get the TIM Capture Compare Register value on runtime.
  1003. * @param __HANDLE__ TIM handle.
  1004. * @param __CHANNEL__ TIM Channel associated with the capture compare register
  1005. * This parameter can be one of the following values:
  1006. * @arg TIM_CHANNEL_1: get capture/compare 1 register value
  1007. * @arg TIM_CHANNEL_2: get capture/compare 2 register value
  1008. * @arg TIM_CHANNEL_3: get capture/compare 3 register value
  1009. * @arg TIM_CHANNEL_4: get capture/compare 4 register value
  1010. * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
  1011. */
  1012. #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
  1013. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
  1014. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
  1015. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
  1016. ((__HANDLE__)->Instance->CCR4))
  1017. /**
  1018. * @brief Set the TIM Output compare preload.
  1019. * @param __HANDLE__ TIM handle.
  1020. * @param __CHANNEL__ TIM Channels to be configured.
  1021. * This parameter can be one of the following values:
  1022. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1023. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1024. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1025. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1026. * @retval None
  1027. */
  1028. #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
  1029. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
  1030. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
  1031. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
  1032. ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
  1033. /**
  1034. * @brief Reset the TIM Output compare preload.
  1035. * @param __HANDLE__ TIM handle.
  1036. * @param __CHANNEL__ TIM Channels to be configured.
  1037. * This parameter can be one of the following values:
  1038. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1039. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1040. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1041. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1042. * @retval None
  1043. */
  1044. #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
  1045. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\
  1046. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\
  1047. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\
  1048. ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE))
  1049. /**
  1050. * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
  1051. * @param __HANDLE__ TIM handle.
  1052. * @note When the URS bit of the TIMx_CR1 register is set, only counter
  1053. * overflow/underflow generates an update interrupt or DMA request (if
  1054. * enabled)
  1055. * @retval None
  1056. */
  1057. #define __HAL_TIM_URS_ENABLE(__HANDLE__) \
  1058. ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
  1059. /**
  1060. * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
  1061. * @param __HANDLE__ TIM handle.
  1062. * @note When the URS bit of the TIMx_CR1 register is reset, any of the
  1063. * following events generate an update interrupt or DMA request (if
  1064. * enabled):
  1065. * _ Counter overflow underflow
  1066. * _ Setting the UG bit
  1067. * _ Update generation through the slave mode controller
  1068. * @retval None
  1069. */
  1070. #define __HAL_TIM_URS_DISABLE(__HANDLE__) \
  1071. ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
  1072. /**
  1073. * @brief Set the TIM Capture x input polarity on runtime.
  1074. * @param __HANDLE__ TIM handle.
  1075. * @param __CHANNEL__ TIM Channels to be configured.
  1076. * This parameter can be one of the following values:
  1077. * @arg TIM_CHANNEL_1: TIM Channel 1 selected
  1078. * @arg TIM_CHANNEL_2: TIM Channel 2 selected
  1079. * @arg TIM_CHANNEL_3: TIM Channel 3 selected
  1080. * @arg TIM_CHANNEL_4: TIM Channel 4 selected
  1081. * @param __POLARITY__ Polarity for TIx source
  1082. * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
  1083. * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
  1084. * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
  1085. * @retval None
  1086. */
  1087. #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  1088. do{ \
  1089. TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
  1090. TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
  1091. }while(0)
  1092. /**
  1093. * @}
  1094. */
  1095. /* End of exported macros ----------------------------------------------------*/
  1096. /* Private constants ---------------------------------------------------------*/
  1097. /** @defgroup TIM_Private_Constants TIM Private Constants
  1098. * @{
  1099. */
  1100. /* The counter of a timer instance is disabled only if all the CCx and CCxN
  1101. channels have been disabled */
  1102. #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
  1103. /**
  1104. * @}
  1105. */
  1106. /* End of private constants --------------------------------------------------*/
  1107. /* Private macros ------------------------------------------------------------*/
  1108. /** @defgroup TIM_Private_Macros TIM Private Macros
  1109. * @{
  1110. */
  1111. #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
  1112. ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \
  1113. ((__MODE__) == TIM_CLEARINPUTSOURCE_OCREFCLR))
  1114. #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
  1115. ((__BASE__) == TIM_DMABASE_CR2) || \
  1116. ((__BASE__) == TIM_DMABASE_SMCR) || \
  1117. ((__BASE__) == TIM_DMABASE_DIER) || \
  1118. ((__BASE__) == TIM_DMABASE_SR) || \
  1119. ((__BASE__) == TIM_DMABASE_EGR) || \
  1120. ((__BASE__) == TIM_DMABASE_CCMR1) || \
  1121. ((__BASE__) == TIM_DMABASE_CCMR2) || \
  1122. ((__BASE__) == TIM_DMABASE_CCER) || \
  1123. ((__BASE__) == TIM_DMABASE_CNT) || \
  1124. ((__BASE__) == TIM_DMABASE_PSC) || \
  1125. ((__BASE__) == TIM_DMABASE_ARR) || \
  1126. ((__BASE__) == TIM_DMABASE_CCR1) || \
  1127. ((__BASE__) == TIM_DMABASE_CCR2) || \
  1128. ((__BASE__) == TIM_DMABASE_CCR3) || \
  1129. ((__BASE__) == TIM_DMABASE_CCR4) || \
  1130. ((__BASE__) == TIM_DMABASE_OR))
  1131. #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
  1132. #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
  1133. ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
  1134. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
  1135. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
  1136. ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
  1137. #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
  1138. ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
  1139. ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
  1140. #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
  1141. ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
  1142. #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
  1143. ((__STATE__) == TIM_OCFAST_ENABLE))
  1144. #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
  1145. ((__POLARITY__) == TIM_OCPOLARITY_LOW))
  1146. #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
  1147. ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
  1148. ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
  1149. #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
  1150. ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
  1151. ((__SELECTION__) == TIM_ICSELECTION_TRC))
  1152. #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
  1153. ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
  1154. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
  1155. ((__PRESCALER__) == TIM_ICPSC_DIV8))
  1156. #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
  1157. ((__MODE__) == TIM_OPMODE_REPETITIVE))
  1158. #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
  1159. ((__MODE__) == TIM_ENCODERMODE_TI2) || \
  1160. ((__MODE__) == TIM_ENCODERMODE_TI12))
  1161. #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
  1162. #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
  1163. ((__CHANNEL__) == TIM_CHANNEL_2) || \
  1164. ((__CHANNEL__) == TIM_CHANNEL_3) || \
  1165. ((__CHANNEL__) == TIM_CHANNEL_4) || \
  1166. ((__CHANNEL__) == TIM_CHANNEL_ALL))
  1167. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
  1168. ((__CHANNEL__) == TIM_CHANNEL_2))
  1169. #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
  1170. ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
  1171. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
  1172. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
  1173. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
  1174. ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
  1175. ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
  1176. ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
  1177. ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
  1178. ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
  1179. #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
  1180. ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
  1181. ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
  1182. ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
  1183. ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
  1184. #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
  1185. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
  1186. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
  1187. ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
  1188. #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1189. #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
  1190. ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
  1191. #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
  1192. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
  1193. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
  1194. ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
  1195. #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1196. #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
  1197. ((__SOURCE__) == TIM_TRGO_ENABLE) || \
  1198. ((__SOURCE__) == TIM_TRGO_UPDATE) || \
  1199. ((__SOURCE__) == TIM_TRGO_OC1) || \
  1200. ((__SOURCE__) == TIM_TRGO_OC1REF) || \
  1201. ((__SOURCE__) == TIM_TRGO_OC2REF) || \
  1202. ((__SOURCE__) == TIM_TRGO_OC3REF) || \
  1203. ((__SOURCE__) == TIM_TRGO_OC4REF))
  1204. #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
  1205. ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
  1206. #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
  1207. ((__MODE__) == TIM_SLAVEMODE_RESET) || \
  1208. ((__MODE__) == TIM_SLAVEMODE_GATED) || \
  1209. ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
  1210. ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
  1211. #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
  1212. ((__MODE__) == TIM_OCMODE_PWM2))
  1213. #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
  1214. ((__MODE__) == TIM_OCMODE_ACTIVE) || \
  1215. ((__MODE__) == TIM_OCMODE_INACTIVE) || \
  1216. ((__MODE__) == TIM_OCMODE_TOGGLE) || \
  1217. ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
  1218. ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
  1219. #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
  1220. ((__SELECTION__) == TIM_TS_ITR1) || \
  1221. ((__SELECTION__) == TIM_TS_ITR2) || \
  1222. ((__SELECTION__) == TIM_TS_ITR3) || \
  1223. ((__SELECTION__) == TIM_TS_TI1F_ED) || \
  1224. ((__SELECTION__) == TIM_TS_TI1FP1) || \
  1225. ((__SELECTION__) == TIM_TS_TI2FP2) || \
  1226. ((__SELECTION__) == TIM_TS_ETRF))
  1227. #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
  1228. ((__SELECTION__) == TIM_TS_ITR1) || \
  1229. ((__SELECTION__) == TIM_TS_ITR2) || \
  1230. ((__SELECTION__) == TIM_TS_ITR3) || \
  1231. ((__SELECTION__) == TIM_TS_NONE))
  1232. #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
  1233. ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
  1234. ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
  1235. ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
  1236. ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
  1237. #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
  1238. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
  1239. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
  1240. ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
  1241. #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1242. #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
  1243. ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
  1244. #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
  1245. ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
  1246. ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
  1247. ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
  1248. ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
  1249. ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
  1250. ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
  1251. ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
  1252. ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
  1253. ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
  1254. ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
  1255. ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
  1256. ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
  1257. ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
  1258. ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
  1259. ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
  1260. ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
  1261. ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
  1262. #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
  1263. #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
  1264. #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
  1265. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
  1266. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
  1267. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
  1268. ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
  1269. #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
  1270. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
  1271. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
  1272. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
  1273. ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
  1274. #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
  1275. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
  1276. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
  1277. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
  1278. ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
  1279. #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
  1280. (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
  1281. ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
  1282. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
  1283. ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
  1284. /**
  1285. * @}
  1286. */
  1287. /* End of private macros -----------------------------------------------------*/
  1288. /* Include TIM HAL Extended module */
  1289. #include "stm32l1xx_hal_tim_ex.h"
  1290. /* Exported functions --------------------------------------------------------*/
  1291. /** @addtogroup TIM_Exported_Functions TIM Exported Functions
  1292. * @{
  1293. */
  1294. /** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions
  1295. * @brief Time Base functions
  1296. * @{
  1297. */
  1298. /* Time Base functions ********************************************************/
  1299. HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
  1300. HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
  1301. void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
  1302. void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
  1303. /* Blocking mode: Polling */
  1304. HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
  1305. HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
  1306. /* Non-Blocking mode: Interrupt */
  1307. HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
  1308. HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
  1309. /* Non-Blocking mode: DMA */
  1310. HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
  1311. HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
  1312. /**
  1313. * @}
  1314. */
  1315. /** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions
  1316. * @brief TIM Output Compare functions
  1317. * @{
  1318. */
  1319. /* Timer Output Compare functions *********************************************/
  1320. HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
  1321. HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
  1322. void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
  1323. void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
  1324. /* Blocking mode: Polling */
  1325. HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1326. HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1327. /* Non-Blocking mode: Interrupt */
  1328. HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1329. HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1330. /* Non-Blocking mode: DMA */
  1331. HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1332. HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1333. /**
  1334. * @}
  1335. */
  1336. /** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions
  1337. * @brief TIM PWM functions
  1338. * @{
  1339. */
  1340. /* Timer PWM functions ********************************************************/
  1341. HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
  1342. HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
  1343. void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
  1344. void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
  1345. /* Blocking mode: Polling */
  1346. HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1347. HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1348. /* Non-Blocking mode: Interrupt */
  1349. HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1350. HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1351. /* Non-Blocking mode: DMA */
  1352. HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1353. HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1354. /**
  1355. * @}
  1356. */
  1357. /** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions
  1358. * @brief TIM Input Capture functions
  1359. * @{
  1360. */
  1361. /* Timer Input Capture functions **********************************************/
  1362. HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
  1363. HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
  1364. void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
  1365. void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
  1366. /* Blocking mode: Polling */
  1367. HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1368. HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1369. /* Non-Blocking mode: Interrupt */
  1370. HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1371. HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1372. /* Non-Blocking mode: DMA */
  1373. HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
  1374. HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1375. /**
  1376. * @}
  1377. */
  1378. /** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions
  1379. * @brief TIM One Pulse functions
  1380. * @{
  1381. */
  1382. /* Timer One Pulse functions **************************************************/
  1383. HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
  1384. HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
  1385. void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
  1386. void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
  1387. /* Blocking mode: Polling */
  1388. HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1389. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1390. /* Non-Blocking mode: Interrupt */
  1391. HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1392. HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
  1393. /**
  1394. * @}
  1395. */
  1396. /** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions
  1397. * @brief TIM Encoder functions
  1398. * @{
  1399. */
  1400. /* Timer Encoder functions ****************************************************/
  1401. HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
  1402. HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
  1403. void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
  1404. void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
  1405. /* Blocking mode: Polling */
  1406. HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
  1407. HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
  1408. /* Non-Blocking mode: Interrupt */
  1409. HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1410. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
  1411. /* Non-Blocking mode: DMA */
  1412. HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
  1413. HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
  1414. /**
  1415. * @}
  1416. */
  1417. /** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management
  1418. * @brief IRQ handler management
  1419. * @{
  1420. */
  1421. /* Interrupt Handler functions ***********************************************/
  1422. void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
  1423. /**
  1424. * @}
  1425. */
  1426. /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
  1427. * @brief Peripheral Control functions
  1428. * @{
  1429. */
  1430. /* Control functions *********************************************************/
  1431. HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
  1432. HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
  1433. HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
  1434. HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel);
  1435. HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel);
  1436. HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
  1437. HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
  1438. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
  1439. HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
  1440. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
  1441. uint32_t *BurstBuffer, uint32_t BurstLength);
  1442. HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1443. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
  1444. uint32_t *BurstBuffer, uint32_t BurstLength);
  1445. HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
  1446. HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
  1447. uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
  1448. /**
  1449. * @}
  1450. */
  1451. /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
  1452. * @brief TIM Callbacks functions
  1453. * @{
  1454. */
  1455. /* Callback in non blocking modes (Interrupt and DMA) *************************/
  1456. void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
  1457. void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
  1458. void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
  1459. void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
  1460. void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
  1461. void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
  1462. void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
  1463. void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
  1464. void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
  1465. void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
  1466. /* Callbacks Register/UnRegister functions ***********************************/
  1467. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1468. HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
  1469. HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
  1470. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1471. /**
  1472. * @}
  1473. */
  1474. /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
  1475. * @brief Peripheral State functions
  1476. * @{
  1477. */
  1478. /* Peripheral State functions ************************************************/
  1479. HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
  1480. HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
  1481. HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
  1482. HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
  1483. HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
  1484. HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
  1485. /**
  1486. * @}
  1487. */
  1488. /**
  1489. * @}
  1490. */
  1491. /* End of exported functions -------------------------------------------------*/
  1492. /* Private functions----------------------------------------------------------*/
  1493. /** @defgroup TIM_Private_Functions TIM Private Functions
  1494. * @{
  1495. */
  1496. void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
  1497. void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
  1498. void TIM_DMAError(DMA_HandleTypeDef *hdma);
  1499. void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
  1500. void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
  1501. #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
  1502. void TIM_ResetCallback(TIM_HandleTypeDef *htim);
  1503. #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
  1504. /**
  1505. * @}
  1506. */
  1507. /* End of private functions --------------------------------------------------*/
  1508. /**
  1509. * @}
  1510. */
  1511. /**
  1512. * @}
  1513. */
  1514. #ifdef __cplusplus
  1515. }
  1516. #endif
  1517. #endif /* STM32L1xx_HAL_TIM_H */
  1518. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/