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Implement a secure ICS protocol targeting LoRa Node151 microcontroller for controlling irrigation.
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lora-irrigation/stm32/l151ccux/stm32l1xx_hal.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32l1xx_hal.h

  4.   * @author  MCD Application Team

  5.   * @brief   This file contains all the functions prototypes for the HAL

  6.   *          module driver.

  7.   ******************************************************************************

  8.   * @attention

  9.   *

  10.   * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

  11.   * All rights reserved.</center></h2>

  12.   *

  13.   * This software component is licensed by ST under BSD 3-Clause license,

  14.   * the "License"; You may not use this file except in compliance with the

  15.   * License. You may obtain a copy of the License at:

  16.   *                        opensource.org/licenses/BSD-3-Clause

  17.   *

  18.   ******************************************************************************

  19.   */

  20. 

  21. /* Define to prevent recursive inclusion -------------------------------------*/

  22. #ifndef __STM32L1xx_HAL_H

  23. #define __STM32L1xx_HAL_H

  24. 

  25. #ifdef __cplusplus

  26.  extern "C" {

  27. #endif

  28. 

  29. /* Includes ------------------------------------------------------------------*/

  30. #include "stm32l1xx_hal_conf.h"

  31. 

  32. /** @addtogroup STM32L1xx_HAL_Driver

  33.   * @{

  34.   */

  35. 

  36. /** @addtogroup HAL

  37.   * @{

  38.   */

  39. 

  40. /* Exported types ------------------------------------------------------------*/

  41. /* Exported constants --------------------------------------------------------*/

  42. 

  43. /** @defgroup HAL_Exported_Constants HAL Exported Constants

  44.   * @{

  45.   */

  46. 

  47. /** @defgroup HAL_TICK_FREQ Tick Frequency

  48.   * @{

  49.   */

  50. #define  HAL_TICK_FREQ_10HZ         100U

  51. #define  HAL_TICK_FREQ_100HZ        10U

  52. #define  HAL_TICK_FREQ_1KHZ         1U

  53. #define  HAL_TICK_FREQ_DEFAULT      HAL_TICK_FREQ_1KHZ

  54. 

  55. #define IS_TICKFREQ(__FREQ__) (((__FREQ__) == HAL_TICK_FREQ_10HZ)  || \

  56.                                ((__FREQ__) == HAL_TICK_FREQ_100HZ) || \

  57.                                ((__FREQ__) == HAL_TICK_FREQ_1KHZ))

  58. 

  59. /**

  60.   * @}

  61.   */

  62. 

  63. /**

  64.   * @}

  65.   */

  66. 

  67. /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants

  68.   * @{

  69.   */

  70. 

  71. /** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG

  72.   * @{

  73.   */

  74. 

  75. /** @defgroup SYSCFG_BootMode Boot Mode

  76.   * @{

  77.   */

  78. 

  79. #define SYSCFG_BOOT_MAINFLASH          (0x00000000U)

  80. #define SYSCFG_BOOT_SYSTEMFLASH        ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)

  81. #if defined(FSMC_R_BASE)

  82. #define SYSCFG_BOOT_FSMC               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)

  83. #endif /* FSMC_R_BASE  */

  84. #define SYSCFG_BOOT_SRAM               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)

  85. 

  86. /**

  87.   * @}

  88.   */

  89. 

  90. /**

  91.   * @}

  92.   */

  93. 

  94. /** @defgroup RI_Constants RI: Routing Interface

  95.   * @{

  96.   */

  97. 

  98. /** @defgroup RI_InputCapture Input Capture

  99.   * @{

  100.   */

  101. 

  102. #define RI_INPUTCAPTURE_IC1  RI_ICR_IC1    /*!< Input Capture 1 */

  103. #define RI_INPUTCAPTURE_IC2  RI_ICR_IC2    /*!< Input Capture 2 */

  104. #define RI_INPUTCAPTURE_IC3  RI_ICR_IC3    /*!< Input Capture 3 */

  105. #define RI_INPUTCAPTURE_IC4  RI_ICR_IC4    /*!< Input Capture 4 */

  106. 

  107. /**

  108.   * @}

  109.   */

  110. 

  111. /** @defgroup TIM_Select TIM Select

  112.   * @{

  113.   */

  114. 

  115. #define TIM_SELECT_NONE  (0x00000000U)    /*!< None selected */

  116. #define TIM_SELECT_TIM2  ((uint32_t)RI_ICR_TIM_0)  /*!< Timer 2 selected */

  117. #define TIM_SELECT_TIM3  ((uint32_t)RI_ICR_TIM_1)  /*!< Timer 3 selected */

  118. #define TIM_SELECT_TIM4  ((uint32_t)RI_ICR_TIM)    /*!< Timer 4 selected */

  119. 

  120. #define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \

  121.                         ((__TIM__) == TIM_SELECT_TIM2) || \

  122.                         ((__TIM__) == TIM_SELECT_TIM3) || \

  123.                         ((__TIM__) == TIM_SELECT_TIM4))

  124. 

  125. /**

  126.   * @}

  127.   */

  128. 

  129. /** @defgroup RI_InputCaptureRouting Input Capture Routing

  130.   * @{

  131.   */

  132.                                                           /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */

  133. #define RI_INPUTCAPTUREROUTING_0   (0x00000000U) /* PA0       PA1      PA2       PA3      */

  134. #define RI_INPUTCAPTUREROUTING_1   (0x00000001U) /* PA4       PA5      PA6       PA7      */

  135. #define RI_INPUTCAPTUREROUTING_2   (0x00000002U) /* PA8       PA9      PA10      PA11     */

  136. #define RI_INPUTCAPTUREROUTING_3   (0x00000003U) /* PA12      PA13     PA14      PA15     */

  137. #define RI_INPUTCAPTUREROUTING_4   (0x00000004U) /* PC0       PC1      PC2       PC3      */

  138. #define RI_INPUTCAPTUREROUTING_5   (0x00000005U) /* PC4       PC5      PC6       PC7      */

  139. #define RI_INPUTCAPTUREROUTING_6   (0x00000006U) /* PC8       PC9      PC10      PC11     */

  140. #define RI_INPUTCAPTUREROUTING_7   (0x00000007U) /* PC12      PC13     PC14      PC15     */

  141. #define RI_INPUTCAPTUREROUTING_8   (0x00000008U) /* PD0       PD1      PD2       PD3      */

  142. #define RI_INPUTCAPTUREROUTING_9   (0x00000009U) /* PD4       PD5      PD6       PD7      */

  143. #define RI_INPUTCAPTUREROUTING_10  (0x0000000AU) /* PD8       PD9      PD10      PD11     */

  144. #define RI_INPUTCAPTUREROUTING_11  (0x0000000BU) /* PD12      PD13     PD14      PD15     */

  145. #define RI_INPUTCAPTUREROUTING_12  (0x0000000CU) /* PE0       PE1      PE2       PE3      */

  146. #define RI_INPUTCAPTUREROUTING_13  (0x0000000DU) /* PE4       PE5      PE6       PE7      */

  147. #define RI_INPUTCAPTUREROUTING_14  (0x0000000EU) /* PE8       PE9      PE10      PE11     */

  148. #define RI_INPUTCAPTUREROUTING_15  (0x0000000FU) /* PE12      PE13     PE14      PE15     */

  149. 

  150. #define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \

  151.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \

  152.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \

  153.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \

  154.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \

  155.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \

  156.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \

  157.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \

  158.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \

  159.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \

  160.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \

  161.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \

  162.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \

  163.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \

  164.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \

  165.                                              ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))

  166. 

  167. /**

  168.   * @}

  169.   */

  170. 

  171. /** @defgroup RI_IOSwitch IO Switch

  172.   * @{

  173.   */

  174. #define RI_ASCR1_REGISTER       (0x80000000U)

  175. /* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */

  176. #define RI_IOSWITCH_CH0         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)

  177. #define RI_IOSWITCH_CH1         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)

  178. #define RI_IOSWITCH_CH2         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)

  179. #define RI_IOSWITCH_CH3         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)

  180. #define RI_IOSWITCH_CH4         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)

  181. #define RI_IOSWITCH_CH5         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)

  182. #define RI_IOSWITCH_CH6         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)

  183. #define RI_IOSWITCH_CH7         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)

  184. #define RI_IOSWITCH_CH8         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)

  185. #define RI_IOSWITCH_CH9         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)

  186. #define RI_IOSWITCH_CH10        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)

  187. #define RI_IOSWITCH_CH11        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)

  188. #define RI_IOSWITCH_CH12        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)

  189. #define RI_IOSWITCH_CH13        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)

  190. #define RI_IOSWITCH_CH14        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)

  191. #define RI_IOSWITCH_CH15        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)

  192. #define RI_IOSWITCH_CH18        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)

  193. #define RI_IOSWITCH_CH19        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)

  194. #define RI_IOSWITCH_CH20        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)

  195. #define RI_IOSWITCH_CH21        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)

  196. #define RI_IOSWITCH_CH22        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)

  197. #define RI_IOSWITCH_CH23        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)

  198. #define RI_IOSWITCH_CH24        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)

  199. #define RI_IOSWITCH_CH25        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)

  200. #define RI_IOSWITCH_VCOMP       ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */

  201. #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */

  202. #define RI_IOSWITCH_CH27        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)

  203. #define RI_IOSWITCH_CH28        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)

  204. #define RI_IOSWITCH_CH29        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)

  205. #define RI_IOSWITCH_CH30        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)

  206. #define RI_IOSWITCH_CH31        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)

  207. #endif /* RI_ASCR2_CH1b */

  208. 

  209. /* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */

  210. #define RI_IOSWITCH_GR10_1      ((uint32_t)RI_ASCR2_GR10_1)

  211. #define RI_IOSWITCH_GR10_2      ((uint32_t)RI_ASCR2_GR10_2)

  212. #define RI_IOSWITCH_GR10_3      ((uint32_t)RI_ASCR2_GR10_3)

  213. #define RI_IOSWITCH_GR10_4      ((uint32_t)RI_ASCR2_GR10_4)

  214. #define RI_IOSWITCH_GR6_1       ((uint32_t)RI_ASCR2_GR6_1)

  215. #define RI_IOSWITCH_GR6_2       ((uint32_t)RI_ASCR2_GR6_2)

  216. #define RI_IOSWITCH_GR5_1       ((uint32_t)RI_ASCR2_GR5_1)

  217. #define RI_IOSWITCH_GR5_2       ((uint32_t)RI_ASCR2_GR5_2)

  218. #define RI_IOSWITCH_GR5_3       ((uint32_t)RI_ASCR2_GR5_3)

  219. #define RI_IOSWITCH_GR4_1       ((uint32_t)RI_ASCR2_GR4_1)

  220. #define RI_IOSWITCH_GR4_2       ((uint32_t)RI_ASCR2_GR4_2)

  221. #define RI_IOSWITCH_GR4_3       ((uint32_t)RI_ASCR2_GR4_3)

  222. #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */

  223. #define RI_IOSWITCH_CH0b        ((uint32_t)RI_ASCR2_CH0b)

  224. #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */

  225. #define RI_IOSWITCH_CH1b        ((uint32_t)RI_ASCR2_CH1b)

  226. #define RI_IOSWITCH_CH2b        ((uint32_t)RI_ASCR2_CH2b)

  227. #define RI_IOSWITCH_CH3b        ((uint32_t)RI_ASCR2_CH3b)

  228. #define RI_IOSWITCH_CH6b        ((uint32_t)RI_ASCR2_CH6b)

  229. #define RI_IOSWITCH_CH7b        ((uint32_t)RI_ASCR2_CH7b)

  230. #define RI_IOSWITCH_CH8b        ((uint32_t)RI_ASCR2_CH8b)

  231. #define RI_IOSWITCH_CH9b        ((uint32_t)RI_ASCR2_CH9b)

  232. #define RI_IOSWITCH_CH10b       ((uint32_t)RI_ASCR2_CH10b)

  233. #define RI_IOSWITCH_CH11b       ((uint32_t)RI_ASCR2_CH11b)

  234. #define RI_IOSWITCH_CH12b       ((uint32_t)RI_ASCR2_CH12b)

  235. #endif /* RI_ASCR2_CH1b */

  236. #define RI_IOSWITCH_GR6_3       ((uint32_t)RI_ASCR2_GR6_3)

  237. #define RI_IOSWITCH_GR6_4       ((uint32_t)RI_ASCR2_GR6_4)

  238. #endif /* RI_ASCR2_CH0b */

  239. 

  240. 

  241. #if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */

  242. 

  243. #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \

  244.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \

  245.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \

  246.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \

  247.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \

  248.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \

  249.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \

  250.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \

  251.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \

  252.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \

  253.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \

  254.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \

  255.                                   ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_CH27)   || \

  256.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH28)    || ((__IOSWITCH__) == RI_IOSWITCH_CH29)   || \

  257.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH30)    || ((__IOSWITCH__) == RI_IOSWITCH_CH31)   || \

  258.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_1)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \

  259.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_3)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \

  260.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)  || \

  261.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4)  || \

  262.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)  || \

  263.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)  || \

  264.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)  || \

  265.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH0b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH1b)   || \

  266.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH3b)   || \

  267.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH7b)   || \

  268.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH9b)   || \

  269.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10b)   || ((__IOSWITCH__) == RI_IOSWITCH_CH11b)  || \

  270.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12b))

  271. 

  272. #else /* !RI_ASCR2_CH1b */

  273. 

  274. #if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */

  275. 

  276. #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \

  277.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \

  278.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \

  279.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \

  280.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \

  281.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \

  282.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \

  283.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \

  284.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \

  285.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \

  286.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \

  287.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \

  288.                                   ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \

  289.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \

  290.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \

  291.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \

  292.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \

  293.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \

  294.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)   || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))

  295. 

  296. #else /* !RI_ASCR2_CH0b */  /* STM32L1 devices category Cat.1 and Cat.2 */

  297. 

  298. #define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \

  299.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \

  300.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \

  301.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \

  302.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \

  303.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \

  304.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \

  305.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \

  306.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \

  307.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \

  308.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \

  309.                                   ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \

  310.                                   ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \

  311.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \

  312.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \

  313.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \

  314.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \

  315.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \

  316.                                   ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))

  317. 

  318. #endif /* RI_ASCR2_CH0b */

  319. #endif /* RI_ASCR2_CH1b */

  320. 

  321. /**

  322.   * @}

  323.   */

  324. 

  325. /** @defgroup RI_Pin PIN define

  326.   * @{

  327.   */

  328. #define RI_PIN_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */

  329. #define RI_PIN_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */

  330. #define RI_PIN_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */

  331. #define RI_PIN_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */

  332. #define RI_PIN_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */

  333. #define RI_PIN_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */

  334. #define RI_PIN_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */

  335. #define RI_PIN_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */

  336. #define RI_PIN_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */

  337. #define RI_PIN_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */

  338. #define RI_PIN_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */

  339. #define RI_PIN_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */

  340. #define RI_PIN_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */

  341. #define RI_PIN_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */

  342. #define RI_PIN_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */

  343. #define RI_PIN_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */

  344. #define RI_PIN_ALL               ((uint16_t)0xFFFF)  /*!< All pins selected */

  345. 

  346. #define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)

  347. 

  348. /**

  349.   * @}

  350.   */

  351. 

  352. /**

  353.   * @}

  354.   */

  355. 

  356. /**

  357.   * @}

  358.   */

  359. 

  360. /* Exported macros -----------------------------------------------------------*/

  361. 

  362. /** @defgroup HAL_Exported_Macros HAL Exported Macros

  363.   * @{

  364.   */

  365. 

  366. /** @defgroup DBGMCU_Macros DBGMCU: Debug MCU

  367.   * @{

  368.   */

  369. 

  370. /** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode

  371.   * @brief   Freeze/Unfreeze Peripherals in Debug mode

  372.   * @{

  373.   */

  374. 

  375. /**

  376.   * @brief  TIM2 Peripherals Debug mode

  377.   */

  378. #if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)

  379. #define __HAL_DBGMCU_FREEZE_TIM2()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)

  380. #define __HAL_DBGMCU_UNFREEZE_TIM2()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)

  381. #endif

  382. 

  383. /**

  384.   * @brief  TIM3 Peripherals Debug mode

  385.   */

  386. #if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)

  387. #define __HAL_DBGMCU_FREEZE_TIM3()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)

  388. #define __HAL_DBGMCU_UNFREEZE_TIM3()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)

  389. #endif

  390. 

  391. /**

  392.   * @brief  TIM4 Peripherals Debug mode

  393.   */

  394. #if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)

  395. #define __HAL_DBGMCU_FREEZE_TIM4()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)

  396. #define __HAL_DBGMCU_UNFREEZE_TIM4()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)

  397. #endif

  398. 

  399. /**

  400.   * @brief  TIM5 Peripherals Debug mode

  401.   */

  402. #if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)

  403. #define __HAL_DBGMCU_FREEZE_TIM5()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)

  404. #define __HAL_DBGMCU_UNFREEZE_TIM5()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)

  405. #endif

  406. 

  407. /**

  408.   * @brief  TIM6 Peripherals Debug mode

  409.   */

  410. #if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)

  411. #define __HAL_DBGMCU_FREEZE_TIM6()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)

  412. #define __HAL_DBGMCU_UNFREEZE_TIM6()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)

  413. #endif

  414. 

  415. /**

  416.   * @brief  TIM7 Peripherals Debug mode

  417.   */

  418. #if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)

  419. #define __HAL_DBGMCU_FREEZE_TIM7()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)

  420. #define __HAL_DBGMCU_UNFREEZE_TIM7()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)

  421. #endif

  422. 

  423. /**

  424.   * @brief  RTC Peripherals Debug mode

  425.   */

  426. #if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)

  427. #define __HAL_DBGMCU_FREEZE_RTC()             SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)

  428. #define __HAL_DBGMCU_UNFREEZE_RTC()           CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)

  429. #endif

  430. 

  431. /**

  432.   * @brief  WWDG Peripherals Debug mode

  433.   */

  434. #if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)

  435. #define __HAL_DBGMCU_FREEZE_WWDG()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)

  436. #define __HAL_DBGMCU_UNFREEZE_WWDG()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)

  437. #endif

  438. 

  439. /**

  440.   * @brief  IWDG Peripherals Debug mode

  441.   */

  442. #if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)

  443. #define __HAL_DBGMCU_FREEZE_IWDG()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)

  444. #define __HAL_DBGMCU_UNFREEZE_IWDG()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)

  445. #endif

  446. 

  447. /**

  448.   * @brief  I2C1 Peripherals Debug mode

  449.   */

  450. #if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)

  451. #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)

  452. #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)

  453. #endif

  454. 

  455. /**

  456.   * @brief  I2C2 Peripherals Debug mode

  457.   */

  458. #if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)

  459. #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)

  460. #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)

  461. #endif

  462. 

  463. /**

  464.   * @brief  TIM9 Peripherals Debug mode

  465.   */

  466. #if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)

  467. #define __HAL_DBGMCU_FREEZE_TIM9()            SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)

  468. #define __HAL_DBGMCU_UNFREEZE_TIM9()          CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)

  469. #endif

  470. 

  471. /**

  472.   * @brief  TIM10 Peripherals Debug mode

  473.   */

  474. #if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)

  475. #define __HAL_DBGMCU_FREEZE_TIM10()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)

  476. #define __HAL_DBGMCU_UNFREEZE_TIM10()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)

  477. #endif

  478. 

  479. /**

  480.   * @brief  TIM11 Peripherals Debug mode

  481.   */

  482. #if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)

  483. #define __HAL_DBGMCU_FREEZE_TIM11()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)

  484. #define __HAL_DBGMCU_UNFREEZE_TIM11()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)

  485. #endif

  486. 

  487. 

  488. /**

  489.   * @}

  490.   */

  491. 

  492. /**

  493.   * @}

  494.   */

  495. 

  496. /** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG

  497.   * @{

  498.   */

  499. 

  500. /** @defgroup SYSCFG_VrefInt VREFINT configuration

  501.   * @{

  502.   */

  503. 

  504. /**

  505.   * @brief  Enables or disables the output of internal reference voltage

  506.   *         (VrefInt) on I/O pin.

  507.   * @note   The VrefInt output can be routed to any I/O in group 3:

  508.   *          - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).

  509.   *          - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).

  510.   *          - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2),

  511.   *            CH1b (PF11) or CH2b (PF12).

  512.   *         Note: Comparator peripheral clock must be preliminarily enabled,

  513.   *               either in COMP user function "HAL_COMP_MspInit()" (should be

  514.   *               done if comparators are used) or by direct clock enable:

  515.   *               Refer to macro "__HAL_RCC_COMP_CLK_ENABLE()".

  516.   *         Note: In addition with this macro, VrefInt output buffer must be

  517.   *               connected to the selected I/O pin. Refer to macro

  518.   *               "__HAL_RI_IOSWITCH_CLOSE()".

  519.   * @note  VrefInt output enable: Internal reference voltage connected to I/O group 3

  520.   *        VrefInt output disable: Internal reference voltage disconnected from I/O group 3

  521.   * @retval None

  522.   */

  523. #define __HAL_SYSCFG_VREFINT_OUT_ENABLE()       SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)

  524. #define __HAL_SYSCFG_VREFINT_OUT_DISABLE()      CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)

  525. 

  526. /**

  527.   * @}

  528.   */

  529. 

  530. /** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration

  531.   * @{

  532.   */

  533. 

  534. /**

  535.   * @brief  Main Flash memory mapped at 0x00000000

  536.   */

  537. #define __HAL_SYSCFG_REMAPMEMORY_FLASH()             CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)

  538. 

  539. /** @brief  System Flash memory mapped at 0x00000000

  540.   */

  541. #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH()       MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)

  542. 

  543. /** @brief  Embedded SRAM mapped at 0x00000000

  544.   */

  545. #define __HAL_SYSCFG_REMAPMEMORY_SRAM()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)

  546. 

  547. #if defined(FSMC_R_BASE)

  548. /** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000

  549.   */

  550. #define __HAL_SYSCFG_REMAPMEMORY_FSMC()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)

  551. 

  552. #endif /* FSMC_R_BASE */

  553. 

  554. /**

  555.   * @brief  Returns the boot mode as configured by user.

  556.   * @retval The boot mode as configured by user. The returned value can be one

  557.   *         of the following values:

  558.   *           @arg SYSCFG_BOOT_MAINFLASH

  559.   *           @arg SYSCFG_BOOT_SYSTEMFLASH

  560.   *           @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)

  561.   *           @arg SYSCFG_BOOT_SRAM

  562.   */

  563. #define __HAL_SYSCFG_GET_BOOT_MODE()          READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)

  564. 

  565. /**

  566.   * @}

  567.   */

  568. 

  569. /** @defgroup SYSCFG_USBConfig USB DP line Configuration

  570.   * @{

  571.   */

  572. 

  573. /**

  574.   * @brief  Control the internal pull-up on USB DP line.

  575.   */

  576. #define __HAL_SYSCFG_USBPULLUP_ENABLE()       SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)

  577. 

  578. #define __HAL_SYSCFG_USBPULLUP_DISABLE()      CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)

  579. 

  580. /**

  581.   * @}

  582.   */

  583. 

  584. /**

  585.   * @}

  586.   */

  587. 

  588. /** @defgroup RI_Macris RI: Routing Interface

  589.   * @{

  590.   */

  591. 

  592. /** @defgroup RI_InputCaputureConfig Input Capture configuration

  593.   * @{

  594.   */

  595. 

  596. /**

  597.   * @brief  Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.

  598.   * @param  __TIMSELECT__ Timer select.

  599.   *   This parameter can be one of the following values:

  600.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.

  601.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.

  602.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.

  603.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.

  604.   * @param  __INPUT__ selects which pin to be routed to Input Capture.

  605.   *   This parameter must be a value of @ref RI_InputCaptureRouting

  606.   *     e.g.

  607.   *       __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)

  608.   *       allows routing of Input capture IC1 of TIM2 to PA4.

  609.   *       For details about correspondence between RI_INPUTCAPTUREROUTING_x

  610.   *       and I/O pins refer to the parameters' description in the header file

  611.   *       or refer to the product reference manual.

  612.   * @note Input capture selection bits are not reset by this function.

  613.   *       To reset input capture selection bits, use SYSCFG_RIDeInit() function.

  614.   * @note The I/O should be configured in alternate function mode (AF14) using

  615.   *       GPIO_PinAFConfig() function.

  616.   * @retval None.

  617.   */

  618. #define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__)  \

  619.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \

  620.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \

  621.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \

  622.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \

  623.               MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \

  624.           }while(0)

  625. 

  626. /**

  627.   * @brief  Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.

  628.   * @param  __TIMSELECT__ Timer select.

  629.   *   This parameter can be one of the following values:

  630.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.

  631.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.

  632.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.

  633.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.

  634.   * @param  __INPUT__ selects which pin to be routed to Input Capture.

  635.   *   This parameter must be a value of @ref RI_InputCaptureRouting

  636.   * @retval None.

  637.   */

  638. #define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__)  \

  639.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \

  640.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \

  641.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \

  642.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \

  643.               MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \

  644.           }while(0)

  645. 

  646. /**

  647.   * @brief  Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.

  648.   * @param  __TIMSELECT__ Timer select.

  649.   *   This parameter can be one of the following values:

  650.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.

  651.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.

  652.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.

  653.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.

  654.   * @param  __INPUT__ selects which pin to be routed to Input Capture.

  655.   *   This parameter must be a value of @ref RI_InputCaptureRouting

  656.   * @retval None.

  657.   */

  658. #define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__)  \

  659.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \

  660.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \

  661.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \

  662.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \

  663.               MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \

  664.           }while(0)

  665. 

  666. /**

  667.   * @brief  Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.

  668.   * @param  __TIMSELECT__ Timer select.

  669.   *   This parameter can be one of the following values:

  670.   *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.

  671.   *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.

  672.   *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.

  673.   *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.

  674.   * @param  __INPUT__ selects which pin to be routed to Input Capture.

  675.   *   This parameter must be a value of @ref RI_InputCaptureRouting

  676.   * @retval None.

  677.   */

  678. #define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__)  \

  679.           do {assert_param(IS_RI_TIM(__TIMSELECT__)); \

  680.               assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \

  681.               MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \

  682.               SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \

  683.               MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \

  684.           }while(0)

  685. 

  686. /**

  687.   * @}

  688.   */

  689. 

  690. /** @defgroup RI_SwitchControlConfig Switch Control configuration

  691.   * @{

  692.   */

  693. 

  694. /**

  695.   * @brief  Enable or disable the switch control mode.

  696.   * @note  ENABLE: ADC analog switches closed if the corresponding

  697.   *                    I/O switch is also closed.

  698.   *                    When using COMP1, switch control mode must be enabled.

  699.   * @note  DISABLE: ADC analog switches open or controlled by the ADC interface.

  700.   *                    When using the ADC for acquisition, switch control mode

  701.   *                    must be disabled.

  702.   * @note COMP1 comparator and ADC cannot be used at the same time since

  703.   *       they share the ADC switch matrix.

  704.   * @retval None

  705.   */

  706. #define __HAL_RI_SWITCHCONTROLMODE_ENABLE()       SET_BIT(RI->ASCR1, RI_ASCR1_SCM)

  707. 

  708. #define __HAL_RI_SWITCHCONTROLMODE_DISABLE()      CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)

  709. 

  710. /*

  711.   * @brief  Close or Open the routing interface Input Output switches.

  712.   * @param  __IOSWITCH__ selects the I/O analog switch number.

  713.   *   This parameter must be a value of @ref RI_IOSwitch

  714.   * @retval None

  715.   */

  716. #define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \

  717.             if ((__IOSWITCH__) >> 31 != 0 ) \

  718.             { \

  719.               SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \

  720.             } \

  721.             else \

  722.             { \

  723.               SET_BIT(RI->ASCR2, (__IOSWITCH__)); \

  724.             } \

  725.           }while(0)

  726. 

  727. #define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \

  728.             if ((__IOSWITCH__) >> 31 != 0 ) \

  729.             { \

  730.               CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \

  731.             } \

  732.             else \

  733.             { \

  734.               CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \

  735.             } \

  736.           }while(0)

  737. 

  738. #if defined (COMP_CSR_SW1)

  739. /**

  740.   * @brief  Close or open the internal switch COMP1_SW1.

  741.   *         This switch connects I/O pin PC3 (can be used as ADC channel 13)

  742.   *         and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel

  743.   *         26) and COMP1 non-inverting input.

  744.   *         Pin PC3 connection depends on another switch setting, refer to

  745.   *         macro "__HAL_ADC_CHANNEL_SPEED_FAST()".

  746.   * @retval None.

  747.   */

  748. #define __HAL_RI_SWITCH_COMP1_SW1_CLOSE()  SET_BIT(COMP->CSR, COMP_CSR_SW1)

  749. 

  750. #define __HAL_RI_SWITCH_COMP1_SW1_OPEN()   CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)

  751. #endif /* COMP_CSR_SW1 */

  752. 

  753. /**

  754.   * @}

  755.   */

  756. 

  757. /** @defgroup RI_HystConfig Hysteresis Activation and Deactivation

  758.   * @{

  759.   */

  760. 

  761. /**

  762.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A

  763.   *         When the I/Os are programmed in input mode by standard I/O port

  764.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  765.   *         When hysteresis is disabled, it is possible to read the

  766.   *         corresponding port with a trigger level of VDDIO/2.

  767.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  768.   *   This parameter must be a value of @ref RI_Pin

  769.   * @retval None

  770.   */

  771. #define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  772.             CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \

  773.           } while(0)

  774. 

  775. #define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  776.             SET_BIT(RI->HYSCR1, (__IOPIN__)); \

  777.           } while(0)

  778. 

  779. /**

  780.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports B

  781.   *         When the I/Os are programmed in input mode by standard I/O port

  782.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  783.   *         When hysteresis is disabled, it is possible to read the

  784.   *         corresponding port with a trigger level of VDDIO/2.

  785.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  786.   *   This parameter must be a value of @ref RI_Pin

  787.   * @retval None

  788.   */

  789. #define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  790.             CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \

  791.           } while(0)

  792. 

  793. #define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  794.             SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \

  795.           } while(0)

  796. 

  797. /**

  798.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports C

  799.   *         When the I/Os are programmed in input mode by standard I/O port

  800.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  801.   *         When hysteresis is disabled, it is possible to read the

  802.   *         corresponding port with a trigger level of VDDIO/2.

  803.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  804.   *   This parameter must be a value of @ref RI_Pin

  805.   * @retval None

  806.   */

  807. #define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  808.             CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \

  809.           } while(0)

  810. 

  811. #define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  812.             SET_BIT(RI->HYSCR2, (__IOPIN__)); \

  813.           } while(0)

  814. 

  815. /**

  816.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports D

  817.   *         When the I/Os are programmed in input mode by standard I/O port

  818.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  819.   *         When hysteresis is disabled, it is possible to read the

  820.   *         corresponding port with a trigger level of VDDIO/2.

  821.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  822.   *   This parameter must be a value of @ref RI_Pin

  823.   * @retval None

  824.   */

  825. #define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  826.             CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \

  827.           } while(0)

  828. 

  829. #define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  830.             SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \

  831.           } while(0)

  832. 

  833. #if defined (GPIOE_BASE)

  834. 

  835. /**

  836.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports E

  837.   *         When the I/Os are programmed in input mode by standard I/O port

  838.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  839.   *         When hysteresis is disabled, it is possible to read the

  840.   *         corresponding port with a trigger level of VDDIO/2.

  841.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  842.   *   This parameter must be a value of @ref RI_Pin

  843.   * @retval None

  844.   */

  845. #define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  846.             CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \

  847.           } while(0)

  848. 

  849. #define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  850.             SET_BIT(RI->HYSCR3, (__IOPIN__)); \

  851.           } while(0)

  852. 

  853. #endif /* GPIOE_BASE */

  854. 

  855. #if defined(GPIOF_BASE) || defined(GPIOG_BASE)

  856. 

  857. /**

  858.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports F

  859.   *         When the I/Os are programmed in input mode by standard I/O port

  860.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  861.   *         When hysteresis is disabled, it is possible to read the

  862.   *         corresponding port with a trigger level of VDDIO/2.

  863.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  864.   *   This parameter must be a value of @ref RI_Pin

  865.   * @retval None

  866.   */

  867. #define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  868.             CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \

  869.           } while(0)

  870. 

  871. #define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  872.             SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \

  873.           } while(0)

  874. 

  875. /**

  876.   * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports G

  877.   *         When the I/Os are programmed in input mode by standard I/O port

  878.   *         registers, the Schmitt trigger and the hysteresis are enabled by default.

  879.   *         When hysteresis is disabled, it is possible to read the

  880.   *         corresponding port with a trigger level of VDDIO/2.

  881.   *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.

  882.   *   This parameter must be a value of @ref RI_Pin

  883.   * @retval None

  884.   */

  885. #define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  886.             CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \

  887.           } while(0)

  888. 

  889. #define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \

  890.             SET_BIT(RI->HYSCR4, (__IOPIN__)); \

  891.           } while(0)

  892. 

  893. #endif /* GPIOF_BASE || GPIOG_BASE */

  894. 

  895. /**

  896.   * @}

  897.   */

  898. 

  899. /**

  900.   * @}

  901.   */

  902. 

  903. /**

  904.   * @}

  905.   */

  906. 

  907. /* Exported variables --------------------------------------------------------*/

  908. /** @defgroup HAL_Exported_Variables HAL Exported Variables

  909.   * @{

  910.   */

  911. extern __IO uint32_t uwTick;

  912. extern uint32_t uwTickPrio;

  913. extern uint32_t uwTickFreq;

  914. /**

  915.   * @}

  916.   */

  917. 

  918. /* Exported functions --------------------------------------------------------*/

  919. /** @addtogroup HAL_Exported_Functions

  920.   * @{

  921.   */

  922. 

  923. /** @addtogroup HAL_Exported_Functions_Group1

  924.   * @{

  925.   */

  926. 

  927. /* Initialization and de-initialization functions  ******************************/

  928. HAL_StatusTypeDef HAL_Init(void);

  929. HAL_StatusTypeDef HAL_DeInit(void);

  930. void              HAL_MspInit(void);

  931. void              HAL_MspDeInit(void);

  932. HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);

  933. 

  934. /**

  935.   * @}

  936.   */

  937. 

  938. /** @addtogroup HAL_Exported_Functions_Group2

  939.   * @{

  940.   */

  941. 

  942. /* Peripheral Control functions  ************************************************/

  943. void               HAL_IncTick(void);

  944. void               HAL_Delay(uint32_t Delay);

  945. uint32_t           HAL_GetTick(void);

  946. uint32_t           HAL_GetTickPrio(void);

  947. HAL_StatusTypeDef  HAL_SetTickFreq(uint32_t Freq);

  948. uint32_t           HAL_GetTickFreq(void);

  949. void               HAL_SuspendTick(void);

  950. void               HAL_ResumeTick(void);

  951. uint32_t           HAL_GetHalVersion(void);

  952. uint32_t           HAL_GetREVID(void);

  953. uint32_t           HAL_GetDEVID(void);

  954. uint32_t           HAL_GetUIDw0(void);

  955. uint32_t           HAL_GetUIDw1(void);

  956. uint32_t           HAL_GetUIDw2(void);

  957. 

  958. /**

  959.   * @}

  960.   */

  961. 

  962. /** @addtogroup HAL_Exported_Functions_Group3

  963.   * @{

  964.   */

  965. 

  966. /* DBGMCU Peripheral Control functions  *****************************************/

  967. void              HAL_DBGMCU_EnableDBGSleepMode(void);

  968. void              HAL_DBGMCU_DisableDBGSleepMode(void);

  969. void              HAL_DBGMCU_EnableDBGStopMode(void);

  970. void              HAL_DBGMCU_DisableDBGStopMode(void);

  971. void              HAL_DBGMCU_EnableDBGStandbyMode(void);

  972. void              HAL_DBGMCU_DisableDBGStandbyMode(void);

  973. 

  974. /**

  975.   * @}

  976.   */

  977. 

  978. /**

  979.   * @}

  980.   */

  981. 

  982. /**

  983.   * @}

  984.   */

  985. 

  986. /**

  987.   * @}

  988.   */

  989. 

  990. #ifdef __cplusplus

  991. }

  992. #endif

  993. 

  994. #endif /* __STM32L1xx_HAL_H */

  995. 

  996. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/