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Implement a secure ICS protocol targeting LoRa Node151 microcontroller for controlling irrigation.
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lora-irrigation/stm32/l151ccux/stm32l1xx_hal_rcc_ex.h

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  1. /**

  2.   ******************************************************************************

  3.   * @file    stm32l1xx_hal_rcc_ex.h

  4.   * @author  MCD Application Team

  5.   * @brief   Header file of RCC HAL Extension module.

  6.   ******************************************************************************

  7.   * @attention

  8.   *

  9.   * <h2><center>&copy; Copyright(c) 2017 STMicroelectronics.

  10.   * All rights reserved.</center></h2>

  11.   *

  12.   * This software component is licensed by ST under BSD 3-Clause license,

  13.   * the "License"; You may not use this file except in compliance with the

  14.   * License. You may obtain a copy of the License at:

  15.   *                        opensource.org/licenses/BSD-3-Clause

  16.   *

  17.   ******************************************************************************

  18.   */

  19. 

  20. /* Define to prevent recursive inclusion -------------------------------------*/

  21. #ifndef __STM32L1xx_HAL_RCC_EX_H

  22. #define __STM32L1xx_HAL_RCC_EX_H

  23. 

  24. #ifdef __cplusplus

  25.  extern "C" {

  26. #endif

  27. 

  28. /* Includes ------------------------------------------------------------------*/

  29. #include "stm32l1xx_hal_def.h"

  30. 

  31. /** @addtogroup STM32L1xx_HAL_Driver

  32.   * @{

  33.   */

  34. 

  35. /** @addtogroup RCCEx

  36.   * @{

  37.   */

  38. 

  39. /** @addtogroup RCCEx_Private_Constants

  40.  * @{

  41.  */

  42. 

  43. #if defined(STM32L100xBA) || defined(STM32L151xBA) || defined(STM32L152xBA)\

  44.  || defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  45.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  46.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  47.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX)\

  48.  || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  49. 

  50. /* Alias word address of LSECSSON bit */

  51. #define LSECSSON_BITNUMBER      RCC_CSR_LSECSSON_Pos

  52. #define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (LSECSSON_BITNUMBER * 4U)))

  53. 

  54. #endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX*/

  55. 

  56. /**

  57.   * @}

  58.   */

  59. 

  60. /** @addtogroup RCCEx_Private_Macros

  61.   * @{

  62.   */

  63. #if defined(LCD)

  64. 

  65. #define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))

  66. 

  67. #else /* Not LCD LINE */

  68. 

  69. #define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)

  70. 

  71. #endif /* LCD */

  72. 

  73. /**

  74.   * @}

  75.   */

  76. 

  77. /* Exported types ------------------------------------------------------------*/

  78. 

  79. /** @defgroup RCCEx_Exported_Types RCCEx Exported Types

  80.   * @{

  81.   */

  82. 

  83. /**

  84.   * @brief  RCC extended clocks structure definition

  85.   */

  86. typedef struct

  87. {

  88.   uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.

  89.                                       This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */

  90. 

  91.   uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.

  92.                                        This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */

  93. 

  94. #if defined(LCD)

  95. 

  96.   uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.

  97.                                        This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */

  98. 

  99. #endif /* LCD */

  100. } RCC_PeriphCLKInitTypeDef;

  101. 

  102. /**

  103.   * @}

  104.   */

  105. 

  106. /* Exported constants --------------------------------------------------------*/

  107. 

  108. /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants

  109.   * @{

  110.   */

  111. 

  112. /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection

  113.   * @{

  114.   */

  115. #define RCC_PERIPHCLK_RTC           (0x00000001U)

  116. 

  117. #if defined(LCD)

  118. 

  119. #define RCC_PERIPHCLK_LCD           (0x00000002U)

  120. 

  121. #endif /* LCD */

  122. 

  123. /**

  124.   * @}

  125.   */

  126. 

  127. #if defined(RCC_LSECSS_SUPPORT)

  128. /** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line

  129.   * @{

  130.   */

  131. #define RCC_EXTI_LINE_LSECSS             (EXTI_IMR_IM19)         /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */

  132. /**

  133.   * @}

  134.   */

  135. #endif /* RCC_LSECSS_SUPPORT */

  136. 

  137. /**

  138.   * @}

  139.   */

  140. 

  141. /* Exported macro ------------------------------------------------------------*/

  142. /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros

  143.  * @{

  144.  */

  145. 

  146. /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable

  147.   * @brief  Enables or disables the AHB1 peripheral clock.

  148.   * @note   After reset, the peripheral clock (used for registers read/write access)

  149.   *         is disabled and the application software has to enable this clock before

  150.   *         using it.

  151.   * @{

  152.   */

  153. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\

  154.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\

  155.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  156.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  157.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  158.  || defined(STM32L162xE) || defined(STM32L162xDX)

  159. 

  160. #define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \

  161.                                         __IO uint32_t tmpreg; \

  162.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\

  163.                                         /* Delay after an RCC peripheral clock enabling */ \

  164.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOEEN);\

  165.                                         UNUSED(tmpreg); \

  166.                                       } while(0U)

  167. #define __HAL_RCC_GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))

  168. 

  169. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  170. 

  171. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  172.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  173.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  174. 

  175. #define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \

  176.                                         __IO uint32_t tmpreg; \

  177.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\

  178.                                         /* Delay after an RCC peripheral clock enabling */ \

  179.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOFEN);\

  180.                                         UNUSED(tmpreg); \

  181.                                       } while(0U)

  182. #define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \

  183.                                         __IO uint32_t tmpreg; \

  184.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\

  185.                                         /* Delay after an RCC peripheral clock enabling */ \

  186.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_GPIOGEN);\

  187.                                         UNUSED(tmpreg); \

  188.                                       } while(0U)

  189. 

  190. #define __HAL_RCC_GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))

  191. #define __HAL_RCC_GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))

  192. 

  193. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  194. 

  195. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  196.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  197.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  198.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  199.  || defined(STM32L162xE) || defined(STM32L162xDX)

  200. 

  201. #define __HAL_RCC_DMA2_CLK_ENABLE()   do { \

  202.                                         __IO uint32_t tmpreg; \

  203.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\

  204.                                         /* Delay after an RCC peripheral clock enabling */ \

  205.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA2EN);\

  206.                                         UNUSED(tmpreg); \

  207.                                       } while(0U)

  208. 

  209. #define __HAL_RCC_DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))

  210. 

  211. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  212. 

  213. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\

  214.  || defined(STM32L162xE) || defined(STM32L162xDX)

  215. 

  216. #define __HAL_RCC_AES_CLK_ENABLE()    do { \

  217.                                         __IO uint32_t tmpreg; \

  218.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\

  219.                                         /* Delay after an RCC peripheral clock enabling */ \

  220.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_AESEN);\

  221.                                         UNUSED(tmpreg); \

  222.                                       } while(0U)

  223. #define __HAL_RCC_AES_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))

  224. 

  225. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */

  226. 

  227. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  228. 

  229. #define __HAL_RCC_FSMC_CLK_ENABLE()   do { \

  230.                                         __IO uint32_t tmpreg; \

  231.                                         SET_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\

  232.                                         /* Delay after an RCC peripheral clock enabling */ \

  233.                                         tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FSMCEN);\

  234.                                         UNUSED(tmpreg); \

  235.                                       } while(0U)

  236. #define __HAL_RCC_FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))

  237. 

  238. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  239. 

  240. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\

  241.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\

  242.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\

  243.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\

  244.  || defined(STM32L162xE) || defined(STM32L162xDX)

  245. 

  246. #define __HAL_RCC_LCD_CLK_ENABLE()   do { \

  247.                                         __IO uint32_t tmpreg; \

  248.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\

  249.                                         /* Delay after an RCC peripheral clock enabling */ \

  250.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LCDEN);\

  251.                                         UNUSED(tmpreg); \

  252.                                       } while(0U)

  253. #define __HAL_RCC_LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))

  254. 

  255. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  256. 

  257. /** @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.

  258.   * @note   After reset, the peripheral clock (used for registers read/write access)

  259.   *         is disabled and the application software has to enable this clock before

  260.   *         using it.

  261.   */

  262. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\

  263.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  264.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  265.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  266. 

  267. #define __HAL_RCC_TIM5_CLK_ENABLE()   do { \

  268.                                         __IO uint32_t tmpreg; \

  269.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\

  270.                                         /* Delay after an RCC peripheral clock enabling */ \

  271.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\

  272.                                         UNUSED(tmpreg); \

  273.                                       } while(0U)

  274. #define __HAL_RCC_TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))

  275. 

  276. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  277. 

  278. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  279.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  280.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  281.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  282.  || defined(STM32L162xE) || defined(STM32L162xDX)

  283. 

  284. #define __HAL_RCC_SPI3_CLK_ENABLE()   do { \

  285.                                         __IO uint32_t tmpreg; \

  286.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\

  287.                                         /* Delay after an RCC peripheral clock enabling */ \

  288.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\

  289.                                         UNUSED(tmpreg); \

  290.                                       } while(0U)

  291. #define __HAL_RCC_SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))

  292. 

  293. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  294. 

  295. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\

  296.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  297. 

  298. #define __HAL_RCC_UART4_CLK_ENABLE()   do { \

  299.                                         __IO uint32_t tmpreg; \

  300.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\

  301.                                         /* Delay after an RCC peripheral clock enabling */ \

  302.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\

  303.                                         UNUSED(tmpreg); \

  304.                                       } while(0U)

  305. #define __HAL_RCC_UART5_CLK_ENABLE()   do { \

  306.                                         __IO uint32_t tmpreg; \

  307.                                         SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\

  308.                                         /* Delay after an RCC peripheral clock enabling */ \

  309.                                         tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\

  310.                                         UNUSED(tmpreg); \

  311.                                       } while(0U)

  312. 

  313. #define __HAL_RCC_UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))

  314. #define __HAL_RCC_UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))

  315. 

  316. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || (...) || STM32L152xDX || STM32L162xE || STM32L162xDX */

  317. 

  318. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  319.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  320.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE)\

  321.  || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\

  322.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)

  323. 

  324. #define __HAL_RCC_OPAMP_CLK_ENABLE()      __HAL_RCC_COMP_CLK_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */

  325. #define __HAL_RCC_OPAMP_CLK_DISABLE()     __HAL_RCC_COMP_CLK_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */

  326. 

  327. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || (...) || STM32L162xC || STM32L152xC || STM32L151xC */

  328. 

  329. /** @brief  Enables or disables the High Speed APB (APB2) peripheral clock.

  330.   * @note   After reset, the peripheral clock (used for registers read/write access)

  331.   *         is disabled and the application software has to enable this clock before

  332.   *         using it.

  333.   */

  334. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  335. 

  336. #define __HAL_RCC_SDIO_CLK_ENABLE()   do { \

  337.                                         __IO uint32_t tmpreg; \

  338.                                         SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\

  339.                                         /* Delay after an RCC peripheral clock enabling */ \

  340.                                         tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\

  341.                                         UNUSED(tmpreg); \

  342.                                       } while(0U)

  343. #define __HAL_RCC_SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))

  344. 

  345. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  346. 

  347. /**

  348.     * @}

  349.     */

  350. 

  351. 

  352. /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset

  353.   * @brief  Forces or releases AHB peripheral reset.

  354.   * @{

  355.   */

  356. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\

  357.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\

  358.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  359.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  360.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  361.  || defined(STM32L162xE) || defined(STM32L162xDX)

  362. 

  363. #define __HAL_RCC_GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))

  364. #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))

  365. 

  366. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  367. 

  368. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  369.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  370.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  371. 

  372. #define __HAL_RCC_GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))

  373. #define __HAL_RCC_GPIOG_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))

  374. 

  375. #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))

  376. #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))

  377. 

  378. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  379. 

  380. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  381.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  382.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  383.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  384.  || defined(STM32L162xE) || defined(STM32L162xDX)

  385. 

  386. #define __HAL_RCC_DMA2_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))

  387. #define __HAL_RCC_DMA2_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))

  388. 

  389. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  390. 

  391. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\

  392.  || defined(STM32L162xE) || defined(STM32L162xDX)

  393. 

  394. #define __HAL_RCC_AES_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))

  395. #define __HAL_RCC_AES_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))

  396. 

  397. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */

  398. 

  399. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  400. 

  401. #define __HAL_RCC_FSMC_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))

  402. #define __HAL_RCC_FSMC_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))

  403. 

  404. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  405. 

  406. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\

  407.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\

  408.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\

  409.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\

  410.  || defined(STM32L162xE) || defined(STM32L162xDX)

  411. 

  412. #define __HAL_RCC_LCD_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))

  413. #define __HAL_RCC_LCD_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))

  414. 

  415. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  416. 

  417. /** @brief  Forces or releases APB1 peripheral reset.

  418.   */

  419. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\

  420.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  421.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  422.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  423. 

  424. #define __HAL_RCC_TIM5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))

  425. #define __HAL_RCC_TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))

  426. 

  427. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  428. 

  429. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  430.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  431.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  432.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  433.  || defined(STM32L162xE) || defined(STM32L162xDX)

  434. 

  435. #define __HAL_RCC_SPI3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))

  436. #define __HAL_RCC_SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))

  437. 

  438. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  439. 

  440. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\

  441.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  442. 

  443. #define __HAL_RCC_UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))

  444. #define __HAL_RCC_UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))

  445. 

  446. #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))

  447. #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))

  448. 

  449. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  450. 

  451. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  452.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  453.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\

  454.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)

  455. 

  456. #define __HAL_RCC_OPAMP_FORCE_RESET()     __HAL_RCC_COMP_FORCE_RESET()   /* Peripherals COMP and OPAMP share the same clock domain */

  457. #define __HAL_RCC_OPAMP_RELEASE_RESET()   __HAL_RCC_COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */

  458. 

  459. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */

  460. 

  461. /** @brief  Forces or releases APB2 peripheral reset.

  462.   */

  463. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  464. 

  465. #define __HAL_RCC_SDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))

  466. #define __HAL_RCC_SDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))

  467. 

  468. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  469. 

  470. /**

  471.   * @}

  472.   */

  473. 

  474. /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable

  475.   * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.

  476.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  477.   *         power consumption.

  478.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  479.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  480.   * @{

  481.   */

  482. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\

  483.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\

  484.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  485.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  486.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  487.  || defined(STM32L162xE) || defined(STM32L162xDX)

  488. 

  489. #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))

  490. #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))

  491. 

  492. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  493. 

  494. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  495.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  496.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  497. 

  498. #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))

  499. #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))

  500. 

  501. #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))

  502. #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))

  503. 

  504. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  505. 

  506. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  507.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  508.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  509.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  510.  || defined(STM32L162xE) || defined(STM32L162xDX)

  511. 

  512. #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))

  513. #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))

  514. 

  515. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  516. 

  517. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE) || defined(STM32L162xDX)

  518. 

  519. #define __HAL_RCC_AES_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))

  520. #define __HAL_RCC_AES_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))

  521. 

  522. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */

  523. 

  524. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  525. 

  526. #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))

  527. #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))

  528. 

  529. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  530. 

  531. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\

  532.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\

  533.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\

  534.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\

  535.  || defined(STM32L162xE) || defined(STM32L162xDX)

  536. 

  537. #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))

  538. #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))

  539. 

  540. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  541. 

  542. /** @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.

  543.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  544.   *           power consumption.

  545.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  546.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  547.   */

  548. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\

  549.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  550.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  551.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  552. 

  553. #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))

  554. #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))

  555. 

  556. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  557. 

  558. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  559.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  560.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  561.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  562.  || defined(STM32L162xE) || defined(STM32L162xDX)

  563. 

  564. #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))

  565. #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))

  566. 

  567. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  568. 

  569. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\

  570.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  571. 

  572. #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))

  573. #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))

  574. 

  575. #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))

  576. #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))

  577. 

  578. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  579. 

  580. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  581.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  582.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\

  583.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)

  584. 

  585. #define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()      __HAL_RCC_COMP_CLK_SLEEP_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */

  586. #define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()     __HAL_RCC_COMP_CLK_SLEEP_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */

  587. 

  588. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */

  589. 

  590. /** @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.

  591.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  592.   *           power consumption.

  593.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  594.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  595.   */

  596. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  597. 

  598. #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))

  599. #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))

  600. 

  601. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  602. 

  603. /**

  604.   * @}

  605.   */

  606. 

  607. /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status

  608.   * @brief  Get the enable or disable status of peripheral clock.

  609.   * @note   After reset, the peripheral clock (used for registers read/write access)

  610.   *         is disabled and the application software has to enable this clock before

  611.   *         using it.

  612.   * @{

  613.   */

  614. 

  615. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\

  616.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\

  617.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  618.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  619.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  620.  || defined(STM32L162xE) || defined(STM32L162xDX)

  621. 

  622. #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) != 0U)

  623. #define __HAL_RCC_GPIOE_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOEEN)) == 0U)

  624. 

  625. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  626. 

  627. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  628.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  629.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  630. 

  631. #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) != 0U)

  632. #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()       ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) != 0U)

  633. #define __HAL_RCC_GPIOF_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOFEN)) == 0U)

  634. #define __HAL_RCC_GPIOG_IS_CLK_DISABLED()      ((RCC->AHBENR & (RCC_AHBENR_GPIOGEN)) == 0U)

  635. 

  636. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  637. 

  638. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  639.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  640.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  641.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  642.  || defined(STM32L162xE) || defined(STM32L162xDX)

  643. 

  644. #define __HAL_RCC_DMA2_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) != 0U)

  645. #define __HAL_RCC_DMA2_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_DMA2EN)) == 0U)

  646. 

  647. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  648. 

  649. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\

  650.  || defined(STM32L162xE) || defined(STM32L162xDX)

  651. 

  652. #define __HAL_RCC_AES_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_AESEN)) != 0U)

  653. #define __HAL_RCC_AES_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_AESEN)) == 0U)

  654. 

  655. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */

  656. 

  657. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  658. 

  659. #define __HAL_RCC_FSMC_IS_CLK_ENABLED()        ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) != 0U)

  660. #define __HAL_RCC_FSMC_IS_CLK_DISABLED()       ((RCC->AHBENR & (RCC_AHBENR_FSMCEN)) == 0U)

  661. 

  662. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  663. 

  664. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\

  665.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\

  666.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\

  667.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\

  668.  || defined(STM32L162xE) || defined(STM32L162xDX)

  669. 

  670. #define __HAL_RCC_LCD_IS_CLK_ENABLED()         ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) != 0U)

  671. #define __HAL_RCC_LCD_IS_CLK_DISABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_LCDEN)) == 0U)

  672. 

  673. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  674. 

  675. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\

  676.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  677.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  678.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  679. 

  680. #define __HAL_RCC_TIM5_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != 0U)

  681. #define __HAL_RCC_TIM5_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == 0U)

  682. 

  683. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  684. 

  685. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  686.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  687.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  688.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  689.  || defined(STM32L162xE) || defined(STM32L162xDX)

  690. 

  691. #define __HAL_RCC_SPI3_IS_CLK_ENABLED()        ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != 0U)

  692. #define __HAL_RCC_SPI3_IS_CLK_DISABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == 0U)

  693. 

  694. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  695. 

  696. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\

  697.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  698. 

  699. #define __HAL_RCC_UART4_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != 0U)

  700. #define __HAL_RCC_UART5_IS_CLK_ENABLED()       ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != 0U)

  701. #define __HAL_RCC_UART4_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == 0U)

  702. #define __HAL_RCC_UART5_IS_CLK_DISABLED()      ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == 0U)

  703. 

  704. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  705. 

  706. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  707.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  708.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\

  709.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)

  710. 

  711. #define __HAL_RCC_OPAMP_IS_CLK_ENABLED()       __HAL_RCC_COMP_IS_CLK_ENABLED()

  712. #define __HAL_RCC_OPAMP_IS_CLK_DISABLED()      __HAL_RCC_COMP_IS_CLK_DISABLED()

  713. 

  714. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */

  715. 

  716. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  717. 

  718. #define __HAL_RCC_SDIO_IS_CLK_ENABLED()        ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) != 0U)

  719. #define __HAL_RCC_SDIO_IS_CLK_DISABLED()       ((RCC->APB2ENR & (RCC_APB2ENR_SDIOEN)) == 0U)

  720. 

  721. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  722. 

  723. /**

  724.   * @}

  725.   */

  726. 

  727. /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable_Status Peripheral Clock Sleep Enable Disable Status

  728.   * @brief  Get the enable or disable status of peripheral clock during Low Power (Sleep) mode.

  729.   * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

  730.   *         power consumption.

  731.   * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

  732.   * @note   By default, all peripheral clocks are enabled during SLEEP mode.

  733.   * @{

  734.   */

  735. 

  736. #if defined(STM32L151xB) || defined(STM32L152xB) || defined(STM32L151xBA)\

  737.  || defined(STM32L152xBA) || defined(STM32L151xC) || defined(STM32L152xC)\

  738.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  739.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  740.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  741.  || defined(STM32L162xE) || defined(STM32L162xDX)

  742. 

  743. #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) != 0U)

  744. #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOELPEN)) == 0U)

  745. 

  746. #endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  747. 

  748. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  749.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  750.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  751. 

  752. #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) != 0U)

  753. #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) != 0U)

  754. #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOFLPEN)) == 0U)

  755. #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()      ((RCC->AHBLPENR & (RCC_AHBLPENR_GPIOGLPEN)) == 0U)

  756. 

  757. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  758. 

  759. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  760.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  761.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  762.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  763.  || defined(STM32L162xE) || defined(STM32L162xDX)

  764. 

  765. #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) != 0U)

  766. #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_DMA2LPEN)) == 0U)

  767. 

  768. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  769. 

  770. #if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD)\

  771.  || defined(STM32L162xE) || defined(STM32L162xDX)

  772. 

  773. #define __HAL_RCC_AES_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) != 0U)

  774. #define __HAL_RCC_AES_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_AESLPEN)) == 0U)

  775. 

  776. #endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE || STM32L162xDX */

  777. 

  778. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  779. 

  780. #define __HAL_RCC_FSMC_IS_CLK_SLEEP_ENABLED()        ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) != 0U)

  781. #define __HAL_RCC_FSMC_IS_CLK_SLEEP_DISABLED()       ((RCC->AHBLPENR & (RCC_AHBLPENR_FSMCLPEN)) == 0U)

  782. 

  783. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  784. 

  785. #if defined(STM32L100xB) || defined(STM32L100xBA) || defined(STM32L100xC)\

  786.  || defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC)\

  787.  || defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD)\

  788.  || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || defined(STM32L152xDX)\

  789.  || defined(STM32L162xE) || defined(STM32L162xDX)

  790. 

  791. #define __HAL_RCC_LCD_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) != 0U)

  792. #define __HAL_RCC_LCD_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_LCDLPEN)) == 0U)

  793. 

  794. #endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  795. 

  796. #if defined(STM32L151xC) || defined(STM32L152xC) || defined(STM32L162xC)\

  797.  || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  798.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  799.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  800. 

  801. #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != 0U)

  802. #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == 0U)

  803. 

  804. #endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  805. 

  806. #if defined(STM32L100xC) || defined(STM32L151xC) || defined(STM32L152xC)\

  807.  || defined(STM32L162xC) || defined(STM32L151xCA) || defined(STM32L151xD)\

  808.  || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L162xCA)\

  809.  || defined(STM32L162xD) || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX)\

  810.  || defined(STM32L162xE) || defined(STM32L162xDX)

  811. 

  812. #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()        ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != 0U)

  813. #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == 0U)

  814. 

  815. #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  816. 

  817. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)\

  818.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)

  819. 

  820. #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != 0U)

  821. #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()       ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != 0U)

  822. #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == 0U)

  823. #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()      ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == 0U)

  824. 

  825. #endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */

  826. 

  827. #if defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L152xCA)\

  828.  || defined(STM32L152xD) || defined(STM32L162xCA) || defined(STM32L162xD)\

  829.  || defined(STM32L151xE) || defined(STM32L151xDX) || defined(STM32L152xE) || defined(STM32L152xDX) || defined(STM32L162xE) || defined(STM32L162xDX)\

  830.  || defined(STM32L162xC) || defined(STM32L152xC) || defined(STM32L151xC)

  831. 

  832. #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()       __HAL_RCC_COMP_IS_CLK_SLEEP_ENABLED()

  833. #define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()      __HAL_RCC_COMP_IS_CLK_SLEEP_DISABLED()

  834. 

  835. #endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */

  836. 

  837. #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)

  838. 

  839. #define __HAL_RCC_SDIO_IS_CLK_SLEEP_ENABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) != 0U)

  840. #define __HAL_RCC_SDIO_IS_CLK_SLEEP_DISABLED()       ((RCC->APB2LPENR & (RCC_APB2LPENR_SDIOLPEN)) == 0U)

  841. 

  842. #endif /* STM32L151xD || STM32L152xD || STM32L162xD */

  843. 

  844. /**

  845.   * @}

  846.   */

  847. 

  848. 

  849. #if defined(RCC_LSECSS_SUPPORT)

  850. 

  851. /**

  852.   * @brief Enable interrupt on RCC LSE CSS EXTI Line 19.

  853.   * @retval None

  854.   */

  855. #define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)

  856. 

  857. /**

  858.   * @brief Disable interrupt on RCC LSE CSS EXTI Line 19.

  859.   * @retval None

  860.   */

  861. #define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR, RCC_EXTI_LINE_LSECSS)

  862. 

  863. /**

  864.   * @brief Enable event on RCC LSE CSS EXTI Line 19.

  865.   * @retval None.

  866.   */

  867. #define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)

  868. 

  869. /**

  870.   * @brief Disable event on RCC LSE CSS EXTI Line 19.

  871.   * @retval None.

  872.   */

  873. #define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR, RCC_EXTI_LINE_LSECSS)

  874. 

  875. 

  876. /**

  877.   * @brief  RCC LSE CSS EXTI line configuration: set falling edge trigger.

  878.   * @retval None.

  879.   */

  880. #define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)

  881. 

  882. 

  883. /**

  884.   * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

  885.   * @retval None.

  886.   */

  887. #define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR, RCC_EXTI_LINE_LSECSS)

  888. 

  889. 

  890. /**

  891.   * @brief  RCC LSE CSS EXTI line configuration: set rising edge trigger.

  892.   * @retval None.

  893.   */

  894. #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)

  895. 

  896. /**

  897.   * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

  898.   * @retval None.

  899.   */

  900. #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR, RCC_EXTI_LINE_LSECSS)

  901. 

  902. /**

  903.   * @brief  RCC LSE CSS EXTI line configuration: set rising & falling edge trigger.

  904.   * @retval None.

  905.   */

  906. #define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \

  907.   do {                                                      \

  908.     __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \

  909.     __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \

  910.   } while(0U)

  911. 

  912. /**

  913.   * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

  914.   * @retval None.

  915.   */

  916. #define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \

  917.   do {                                                       \

  918.     __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \

  919.     __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \

  920.   } while(0U)

  921. 

  922. /**

  923.   * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

  924.   * @retval EXTI RCC LSE CSS Line Status.

  925.   */

  926. #define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (EXTI->PR & (RCC_EXTI_LINE_LSECSS))

  927. 

  928. /**

  929.   * @brief Clear the RCC LSE CSS EXTI flag.

  930.   * @retval None.

  931.   */

  932. #define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     (EXTI->PR = (RCC_EXTI_LINE_LSECSS))

  933. 

  934. /**

  935.   * @brief Generate a Software interrupt on selected EXTI line.

  936.   * @retval None.

  937.   */

  938. #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER, RCC_EXTI_LINE_LSECSS)

  939. 

  940. #endif /* RCC_LSECSS_SUPPORT */

  941. 

  942. #if defined(LCD)

  943. 

  944. /** @defgroup RCCEx_LCD_Configuration LCD Configuration

  945.   * @brief  Macros to configure clock source of LCD peripherals.

  946.   * @{

  947.   */

  948. 

  949. /** @brief Macro to configures LCD clock (LCDCLK).

  950.   *  @note   LCD and RTC use the same configuration

  951.   *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the

  952.   *          LCD clock source.

  953.   *

  954.   *  @param  __LCD_CLKSOURCE__ specifies the LCD clock source.

  955.   *          This parameter can be one of the following values:

  956.   *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as LCD clock

  957.   *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as LCD clock

  958.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV2 HSE divided by 2 selected as LCD clock

  959.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV4 HSE divided by 4 selected as LCD clock

  960.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV8 HSE divided by 8 selected as LCD clock

  961.   *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV16 HSE divided by 16 selected as LCD clock

  962.   */

  963. #define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)

  964. 

  965. /** @brief Macro to get the LCD clock source.

  966.   */

  967. #define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()

  968. 

  969. /** @brief Macro to get the LCD clock pre-scaler.

  970.   */

  971. #define  __HAL_RCC_GET_LCD_HSE_PRESCALER()      __HAL_RCC_GET_RTC_HSE_PRESCALER()

  972. 

  973. /**

  974.   * @}

  975.   */

  976. 

  977. #endif /* LCD */

  978. 

  979. 

  980. /**

  981.   * @}

  982.   */

  983. 

  984. /* Exported functions --------------------------------------------------------*/

  985. /** @addtogroup RCCEx_Exported_Functions

  986.   * @{

  987.   */

  988. 

  989. /** @addtogroup RCCEx_Exported_Functions_Group1

  990.   * @{

  991.   */

  992. 

  993. HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

  994. void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

  995. uint32_t          HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);

  996. 

  997. #if defined(RCC_LSECSS_SUPPORT)

  998. 

  999. void              HAL_RCCEx_EnableLSECSS(void);

  1000. void              HAL_RCCEx_DisableLSECSS(void);

  1001. void              HAL_RCCEx_EnableLSECSS_IT(void);

  1002. void              HAL_RCCEx_LSECSS_IRQHandler(void);

  1003. void              HAL_RCCEx_LSECSS_Callback(void);

  1004. 

  1005. #endif /* RCC_LSECSS_SUPPORT */

  1006. 

  1007. /**

  1008.   * @}

  1009.   */

  1010. 

  1011. /**

  1012.   * @}

  1013.   */

  1014. 

  1015. /**

  1016.   * @}

  1017.   */

  1018. 

  1019. /**

  1020.   * @}

  1021.   */

  1022. 

  1023. #ifdef __cplusplus

  1024. }

  1025. #endif

  1026. 

  1027. #endif /* __STM32L1xx_HAL_RCC_EX_H */

  1028. 

  1029. /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/